iC-Haus iC-PVS User manual

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 1/51
FEATURES
•High-performance Hall sensors with analog output for
downstream high-resolution A/D conversion
•Fits magnetic scales of 1.0 up to 2.5 mm pole width or gear
tooth modules of 0.3 up to 1.5
• Absolute position data with battery-buffered period counting up
to 56 bits
•Adjustable period count per revolution:
FlexCount®logic for 1 to 65536 magnetic periods
•Backup battery current consumption of only
2µA to 30 µA in typical applications
•Internal 6-bit ash interpolation
•Incremental output (ABZ) with up to 64 increments per
magnetic period
•Serial I/O interfaces (BiSS, SSI, SPI, and I2C)
•Tracking speed of up to 75 m/s (1.5 mm poles)
or 46 000 rpm (32 pole pairs)
•Differential scanning for high immunity to external magnetic
stray elds
•I2C master function for initial boot-up from EEPROM
• Overspeed, battery, loss-of-magnet and RAM (CRC) monitoring
APPLICATIONS
•Freely scalable hollow-shaft
absolute multiturn position
sensors
•Freely scalable linear absolute
position sensors
•Ferrous gear wheel or magnetic
scale scanning
•Congurable magnetic sensing
heads
PACKAGES
dra_qfn38-1_pack_2, 2.4:1
38-pin QFN
5 mm x 7 mm
RoHS compliant
BLOCK DIAGRAM
iC-PVS
SerialI/OInterface-AbsoluteData
SerialInterface
CounterLogic
HallControlandSelect
HallControl
HallSensorLine
PeriodCounter
AnalogOutput
SupplySwitch
VBATMonitor VDDMonitor
MultiMaster
FlexCount
Amplitude
Power-Up
6bitParallel
Oscillator
Purpose
orSlave
General
Position
Encode
Monitor
Control
6bitABZ
NWRN
ExtSSI
GPIO2
GPIO0
GPIO1
GPIO3
Config
NCOS
NERR
Status
PCOS
VDDS
VBAT
NSIN
PSIN
BiSS
DIG
GND
RAM
VDD
NCS
SDA
SIN
PRE
SCL
CLK
SPI
+
SO
I/O
SCLK
MOSI
MISO 0
11
0
1 1
SI
NCS
GPIO3
NCS
SDA
VDDS
GPIO1
SO
VBAT
NERR
NWRN
PSIN
VDD
PCOS
GPIO0
CLK
SCL
GND
SI
NCOS
GPIO2
NSIN
PRE
-
SLO SLO
+
+
+
+
C
MA MA
SLI
-
-
-
-
I
B
B
B
B
2
NSIN
SO
NCS
GPIO3
NCOS
VBAT
GPIO1
NERR
GPIO0
SCL
SDA
PSIN
GND
GPIO2
CLK
PCOS
SI
VDD
PRE
NWRN
VDDS
Copyright ©2021 iC-Haus http://www.ichaus.com

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 2/51
DESCRIPTION
iC-PVS is a high performance hall sensor used for
incremental or absolute position sensing. It generates
analog sine/cosine signals usable as inputs to down-
stream high resolution A/D conversion.
Additionally, an ultra low power magnetic period
counter, used for linear and off-axis absolute position
sensing is integrated. On main power shutdown,
iC-PVS automatically switches to battery supply and
continues scanning solely the absolute position. To
save power, the high resolution analog signal output
is inactive in battery mode.
iC-PVS operates with pole wheels or linear scales
with a pole width of 1.0 mm up to 2.5 mm. Ferrous
gear wheels with a gear tooth module of 0.3 up to 1.5
can be scanned with the help of a back-bias magnet.
The iC-PVS delivers the analog signal for further in-
terpolation, as well as the absolute position reference
value. In combination with suitable iC-Haus interpola-
tor devices like iC-TW29 an entire true absolute, high
resolution encoder system can be created with just
these two devices.
Coming with an integrated interpolation stage, the
iC-PVS can also be used as a stand-alone absolute
encoder with up to 6-bit electrical resolution per mag-
netic pole period.
Various interfaces for conguration and data commu-
nication are available. The serial I/O interface can
act as a sensor interface using either the BiSS C
protocol (up to 10 MHz, bidirectional), SSI protocol
(up to 4 MHz) or SPI protocol (4-pin SPI, 4 MHz).
Additionally incremental and parallel output modes
are available.
After power-on, the iC-PVS collects its CRC protected
conguration data from an external I
2
C-EEPROM
or waits for the conguration from one of the I/O
interfaces. An undervoltage reset zeroes internal reg-
isters. Furthermore, the pin PRE serves as a preset
input (high active). Additional to EEPROM readout,
the I
2
C interface can also be used for direct register
communication via the I2C protocol.
The period counter stage is designed for ultra low
power applications and can be congured to support
angular accelerations up to 80 000 rad/s
2
with 32
magnetic periods per revolution. The maximum mag-
netic signal frequency is 25 kHz. This corresponds
to a rotational frequency of 46 000 rpm for magnetic
scales with 32 pole pairs. With higher demands
on acceleration, the battery power consumption in-
creases. The maximum supported acceleration is
congurable, therefore an optimal trade-off between
power consumption and supported acceleration can
be individually chosen to meet the demands of the
individual application.
The device offered here is a multi-functional iC that contains in-
tegrated BiSS C interface components. The BiSS C process is
protected by patent DE 10310622 B4 owned by iC-Haus GmbH.
Users benet from the open BiSS C protocol with a free license
which is necessary when using the BiSS C protocol in conjunction
with this iC.
Download the license at
www.biss-interface.com/bua
General notice on application-specic programming
Parameters dened in the datasheet represent supplier’s
attentive tests and validations, but - by principle - do not imply
any warranty or guarantee as to their accuracy, completeness or
correctness under all application conditions. In particular, setup
conditions, register settings and power-up have to be thoroughly
validated by the user within his specic application environment
and requirements (system responsibility).
The performance of iC-PVS in application is impacted by
system conditions like quality of the magnetic target and its
adjustment, eld strength and stray elds, temperature and
mechanical stress and initial calibration.

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 3/51
CONTENTS
PACKAGING INFORMATION 5
PIN CONFIGURATION QFN38 5 x 7 mm². . 5
PACKAGE DIMENSIONS . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS 7
THERMAL DATA 7
ELECTRICAL CHARACTERISTICS 8
OPERATING REQUIREMENTS 11
Serial I/O Interface: BiSS/SSI Protocol . . . . 11
Serial I/O Interface: SPI Protocol . . . . . . . 12
CONFIGURATION PARAMETERS 13
REGISTER MAP: On-Chip RAM (Banks 0x00 -
0x0F, Address 0x00 - 0x3F) 14
DIRECT ACCESS REGISTER (All Banks,
Address 0x40 - 0x7F) 16
BASIC OPERATION AND SIGNAL
DEFINITIONS 17
DEVICE OPERATING STATES 19
Initial Startup and Power-On-Reset . . . . . . 19
Device Operating States . . . . . . . . . . . . 20
MEMORY ORGANIZATION, EEPROM &
REGISTER PROTECTION LEVEL 22
Conguration Address Range and Bank
Selection (BSEL) . . . . . . . . . . . . . 22
EEPROM .................... 22
EEPROM device requirements . . . . . . . . 22
Register Protection Level (RPL) . . . . . . . 23
Bankoverview ................. 23
I/O INTERFACE OPERATING MODES 25
DISI2C: Disable I2C Slave Interface . . . . . 25
DIOMODE: Serial Interface Operating Mode 25
GPIOMODE: General Purpose I/O Operating
Mode ................... 25
ABSOLUTE DATA FORMAT 26
Absolute data protocol overview for all serial
protocols ................. 26
RCL_ADI: Revolution Counter Length . . . . 26
SBL_ADI: Synchronization Bit Length . . . . 26
PCR_ADI : Period Counts per (mech.)
Revolution................. 26
ERR_ADI: Transmission of Error Bit . . . . . 27
WRN_ADI: Transmission of Warning Bit . . . 27
DIR_ADI: Code Direction Inversion . . . . . . 27
ERR_PDR: Error on Power Down Reset and
Preset................... 27
OS_ADI: Code Offset of Absolute Position . . 28
ENSOL: Enable Sign-Of-Life Counter . . . . 28
CRCS_BISS and CRC16_BISS : BiSS CRC 28
PERIOD COUNTER 29
Position Preload . . . . . . . . . . . . . . . . 29
SUPPLY SWITCH AND MONITORING 29
BAT_MON: Battery Monitor Enable . . . . . . 29
BAT_THR: Battery Monitor Thresholds . . . 30
MON_FRQ: Battery Monitor Sampling
Frequency................. 30
VON5: Set Typical Supply Voltage . . . . . . 30
MAGNETIC SIGNAL CONDITIONING 31
POLEWID: Pole Size of Magnetic Scale . . . 31
DCCOMP: High Magnetic Field Strength
Compensation . . . . . . . . . . . . . . 31
LOWPOW: Low Power Mode . . . . . . . . . 31
NOMAG: Behaviour of NoMagnet Detection . 31
MAG_THR: Magnetic Field Amplitude
Working Threshold . . . . . . . . . . . . 31
ANALOG OUTPUT 32
OSS and OSC: Sine and Cosine Offset Factors 32
OSD: Double Offset Factor . . . . . . . . . . 32
ENOG: Enable Offset Generation Block . . . 32
GCOARSE: Coarse Gain Factor . . . . . . . 32
GAINF and GAINX: Fine Gain Factors Sine
and Cosine Channel . . . . . . . . . . . 32
AGAINS and AGAINC: Actual Fine Gain
Factor Sine and Cosine Channel (Read
only).................... 33
VCMOUT: Common Mode Output Voltage . . 33
ENAC: Amplitude Control Unit Activation . . 33
CURRENT CONSUMPTION IN BATTERY
MODE 34
FREQUENCY AND BIAS CURRENT
ADJUSTMENT 35

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 4/51
ABZ INCREMENTAL OUTPUT 35
AB_IPO : AB Interpolation . . . . . . . . . . . 35
ZGATE : Z Pulse Gating Scheme . . . . . . . 35
MTD : Minimum Transition Distance . . . . . 36
BISS Slave Interface 36
General protocol description . . . . . . . . . 36
Single Cycle Data (SCD) . . . . . . . . . . . 36
NTOA_BISS : Fixed or Adaptive BiSS Timeout 37
Control Communication . . . . . . . . . . . . 37
BiSS protocol commands . . . . . . . . 37
EXTENDED SSI SLAVE INTERFACE 38
General protocol description . . . . . . . . . 38
SPI SLAVE INTERFACE 39
General Protocol Description . . . . . . . . . 39
ReadRegister ................. 40
Write Register . . . . . . . . . . . . . . . . . 40
ReadPosition.................. 40
Write Command . . . . . . . . . . . . . . . . 40
Read Status Register . . . . . . . . . . . . . 41
Read Register - I2C Slave Access . . . . . . 41
Write Register - I2C Slave Access . . . . . . 41
Get Register Communication Status . . . . . 41
Multi-slave congurations with iC-PVS . . . . 42
Activate Slave In Chain . . . . . . . . . . . . 43
I2C EEPROM INTERFACE 44
I2C SLAVE INTERFACE 45
COMMANDS 46
REBOOT .................... 47
RESET ..................... 47
SLEEP ..................... 47
STANDBY.................... 47
SCLEAR .................... 47
FORCE_REQ and UNFORCE_REQ . . . . . 47
CHIP_ID .................... 47
STATUS REGISTERS 48
Status Register Overview . . . . . . . . . . . 48
STUP_ERR: Startup Error . . . . . . . . . . . 48
CFG_ERR: Internal Conguration Error . . . 48
CTR_ERR: Internal Counter Error . . . . . . 48
POS_ERR: Position Error . . . . . . . . . . . 48
BAT_ERR: Battery Error . . . . . . . . . . . . 48
AMPL_ERR: Amplitude Error . . . . . . . . . 48
NOMAG_L: NoMagnet Working State (latched) 48
ANA_STUP: Analog startup phase . . . . . . 48
BAT_WRN: Battery Early Warning . . . . . . 48
REBOOT: Reboot Detected . . . . . . . . . . 48
PDR: Power Down Reset Detected . . . . . . 49
PRESET: Pin Preset Detected . . . . . . . . 49
AC_MIN: Signal Amplitude Low . . . . . . . . 49
AC_MAX: Signal Amplitude High . . . . . . . 49
MAG_ERR: Magnet Error . . . . . . . . . . . 49
Error Output NERR . . . . . . . . . . . . . . 49
Warning Output NWRN . . . . . . . . . . . . 49
ChipRevision.................. 49
DESIGN REVIEW: Notes On Chip Functions 50
REVISION HISTORY 51

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 5/51
PACKAGING INFORMATION
PIN CONFIGURATION QFN38 5 x 7 mm²
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19
20
21
22
23
24
25
26
27
28
29
30
31
3233 34 35363738
<D-CODE>
<A-CODE>
<P-CODE>
PIN FUNCTIONS
No. Name Function
1 GPIO3 General Purpose I/O 3
2 GPIO2 General Purpose I/O 2
3 GPIO1 General Purpose I/O 1
4 GPIO0 General Purpose I/O 0
5 n.c. Pins marked n.c. are not connected
6 n.c.
7 n.c.
8 n.c.
9 n.c.
10 NWRN Battery Early Warning (active low)
11 NCS SPI Not Chip Select
12 SI Serial Interface, Slave In
13 CLK Serial Interface, Clock Line
14 SO Serial Interface, Slave Out
15 PRE Preset Trigger Input
16 GND Ground
17 SCL I2C Interface, Clock Line
18 SDA I2C Interface, Data Line
19 NERR Error Output (active low)
20 n.c.
21 n.c.
22 n.c.
23 n.c.
24 n.c.
25 n.c.
26 n.c.
27 n.c.
28 n.c.
29 n.c.
30 n.c.
31 n.c.
32 NCOS Analog Output Negative Cosine
33 PCOS Analog Output Positive Cosine
34 NSIN Analog Output Negative Sine
35 PSIN Analog Output Positive Sine
36 VDD +3.15V to 5.5V Main Supply Voltage
37 VDDS 1Switched Supply Voltage Output
38 VBAT2 Battery Supply Voltage Input (typ.
3.6 V)
BP3Backside Paddle
IC top marking: <P-CODE> = product code, <A-CODE> = assembly code (subject to changes), <D-CODE> = date code (subject to changes); dashed lines are
used for visible or hidden outlines.
1Connect bypass capacitor according to Elec. Char. 011. The output must not be further loaded.
2Do not leave pin open. Connect pin to VDD if iC-PVS is used without a backup power source (e.g. battery, supercap).
3To improve the heat dissipation connect the backside paddle to an extended copper area connected to GND. Avoid any current ow across the paddle.
The heat distribution can be supported by connecting further PCB layers using thermal vias. If those need to be placed below the paddle, prefer blind vias.

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 6/51
PACKAGE DIMENSIONS
5
4.73
0.10
TOP
*)
*): Center package vs. center hall sensor array
3.65
5.65
0.22
0.40
0.50
BOTTOM
0.90 ±0.10
0.48
SIDE
4.90
3.65
5.65 6.90
R0.15
0.50 0.30
0.70
RECOMMENDED PCB-FOOTPRINT
dra_qfn38-5x7-1_pvs_z_pack_1, 10:1
All dimensions given in mm.
Tolerances of form and position according to JEDEC MO-220.
Tolerance of sensor pattern: ±0.10mm / ±1° (with respect to center of backside pad).

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iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 7/51
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol Parameter Conditions Unit
No. Min. Max.
G001 V(VDD) Voltage at VDD -0.25 6 V
G002 V(VBAT) Voltage at VBAT -0.25 6 V
G003 V(VDDS) Voltage at VDDS -0.25 6 V
G004 V() Voltage at all other pins except VDD,
VBAT, VDDS and GND
-0.25 6 V
G005 I(VDD) Current in VDD 0 100 mA
G006 I(VBAT) Current in VBAT -10 50 mA
G007 I(VDDS) Current in VDDS -100 100 mA
G008 I(GND) Current in GND -100 10 mA
G009 I() Current in all other pins except VDD,
VBAT, VDDS and GND
-30 30 mA
G010 Vd() ESD Susceptibility at All Pins HBM, 100 pF discharged through 1.5 kΩ, all
pins relative to GND
2 kV
G011 Tj Chip Junction Temperature -40 150 °C
THERMAL DATA
Operating conditions:
VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
T01 Ta Operating Ambient Temperature Range QFN38-5x7 surface mounted to PCB
according to JEDEC 51 thermal measurement
standards
-40 125 °C
T02 Rthja Thermal Resistance Chip/Ambience QFN38-5x7 surface mounted to PCB
according to JEDEC 51 thermal measurement
standards
25 K/W
T03 Ts Storage Temperature QFN38-5x7 -40 125 °C
All voltages are referenced to ground unless otherwise stated.
All currents owing into the device pins are positive; all currents owing out of the device pins are negative.

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 8/51
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
General
001 V(VDD) Permissible Main Supply Voltage VON5 = 0 3.15 3.3 5.5 V
VON5 = 1 4.50 5.0 5.5 V
002 I(VDD) Supply Current in VDD Tj = 27 °C, no load,
VDD = 3.3 V 40 60 mA
VDD = 5.0 V 50 80 mA
003 SR(VDD) Permissible Slew Rate at VDD 0.1 V/µs
004 V(VBAT) Permissible Battery Voltage 3.0 3.6 5.0 V
005 Iavg(VBAT) Average Supply Current in VBAT VBAT = 3.6 V, Tj = 27 °C, 10 1500 µA
depending on fmag and A_MAX, see Table 44
006 Ipls(VBAT) Pulse Current in VBAT pulsed operation, tpulse < 10 µs, Tj = 27 °C, 8.0 20.0 mA
007 Vc()hi Clamp Voltage hi at All Pins
except VDD
Vc()hi = V() - V(VDDS), I() = +1 mA 0.3 0.7 1.6 V
008 V() Voltage at all other pins except
VDD, VBAT, VDDS and GND
general -0.25 VDDS+0.3 V
V(VDD) > Von ( VDD supply ) -0.25 VDD+0.3 V
V(VDD) < Von ( Battery supply) -0.25 VBAT+0.3 V
009 Vc()lo Clamp Voltage lo at All Pins
except VDDS
I() = -1 mA -1.6 -0.7 -0.25 V
010 C(VBAT) External Bypass Capacitor
at Pin VBAT
ceramic capacitor placed as close as possible
to the pin
1 1 µF
011 C(VDDS) External Bypass Capacitor
at Pin VDDS
ceramic capacitor placed as close as possible
to the pin
1 1 µF
012 C(VDD) External Bypass Capacitor
at Pin VDD
ceramic capacitor placed as close as possible
to the pin
1 1 µF
013 tstup(VDD) Startup Time Analog Signal Path
after VDD Power Cycle, Standby
or Sleep
ENAC = 0 1 2 ms
ENAC = 1 3 6 ms
Magnetic Signal Conditioning
101 hpac Sensor-to-Package-Surface
Distance
QFN38 5x7 0.4 mm
102 Hmax Permissible Maximum Magnetic
Field Strength, see Figure 11
AC+DC Field at chip surface
DCCOMP = 0 -180 180 kA/m
DCCOMP = 1 -380 380 kA/m
103 Bmax Permissible Maximum Magnetic
Flux Density, see Figure 11
AC+DC Field at chip surface in air
DCCOMP = 0 -225 225 mT
DCCOMP = 1 -475 475 mT
104 Hamp Permissible Operating Magnetic
Field Amplitude, see Figure 11
at chip surface
DCCOMP = 0: 10 100 kA/m
DCCOMP = 1: 13 100 kA/m
105 Bamp Permissible Operating Amplitude
of Magnetic Flux Density, see
Figure 11
at chip surface in air
DCCOMP = 0: 12.5 125 mT
DCCOMP = 1: 16.25 125 mT
106 fmag Permissible Magnetic Input Fre-
quency
VDDS = 5.0 V, tested via electrical input 25 kHz
107 frot Permissible Rotation of Pole
Wheel with
32 pole pairs 46000 rpm
64 pole pairs 23000 rpm
108 vmax Permissible Movement Speed
(Linear)
1.0 mm pole width (2 mm magnetic period) 50 m/s
1.5 mm pole width (3 mm magnetic period) 75 m/s
109 Ht No Magnet Detection Threshold
(Magnetic Field )
MAGTHR = 0x00 5.0 kA/m
MAGTHR = 0x01 2.5 kA/m
MAGTHR = 0x02 1.25 kA/m
MAGTHR = 0x03 10.0 kA/m
device is in NoMagnet working state if eld
amplitude (at chip surface) is below this value

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 9/51
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
110 Bt No Magnet Detection Threshold
(Magnetic Flux Density)
MAGTHR = 0x00 6.25 mT
MAGTHR = 0x01 3.13 mT
MAGTHR = 0x02 0.78 mT
MAGTHR = 0x03 12.5 mT
device is in NoMagnet working state if ux
density amplitude (at chip surface in air) is
below this value
Analog Output: PSIN, NSIN, PCOS, NCOS
201 Vout()sig Amplitude, individual output
signal at: PSIN, NSIN, PCOS,
NCOS (controller setpoint)
ENAC = 1, automatic gain control active 300 500 700 mVpp
set GCOARSE according to Table 36 and 37
202 Vout()cm Sine Cosine Common Mode
Output Voltage in Absolute Mode
VCMOUT = 0x00 1.0 1.25 1.5 V
VCMOUT = 0x01, V(VDD) = 5 V 2.0 2.5 3.0 V
203 Vout()cm Sine Cosine Common Mode
Output Voltage in Relative Mode
VCMOUT = 0x02 40 50 60 %
VDDS
204 C()load Permissible Capacitive Load at
Pin PSIN/NSIN/PCOS/NCOS
Capacitance vs. GND 0.5 nF
205 fout() Signal Output Frequency VDDS = 5.0 V, 25 kHz
206 Isc()hi Short-Circuit Current hi V() = GND -2.5 mA
207 Isc()lo Short-Circuit Current lo V() = VDD 2.5 mA
Oscillator Frequencies
301 fslow Slow Oscillator Frequency calibrated to 34 kHz with IBIAS 32 34 36 kHz
302 ffast Fast Oscillator Frequency fslow calibrated with IBIAS 5.0 6.0 7.0 MHz
Supply Switch and Monitoring
401 Vpor Internal Power-On-Reset increasing voltage at VBAT, V(VDD) < Von 2.70 2.80 2.95 V
402 Vpdr Internal Power-Down-Reset decreasing voltage at VBAT, V(VDD) < Von 1.25 1.80 2.35 V
BAT_MON = "00", battery monitoring disabled
403 Vbout Battery Monitoring Brown-Out
Threshold Voltage
BAT_MON =/ "00", battery monitoring enabled 2.65 2.75 2.90 V
405 Von Switch to VDD Supply
(VDD Power On)
increasing voltage at VDD; VBAT > 3.0 V
VON5 = ’0’, 3.3 V supply 2.95 3.05 3.15 V
VON5 = ’1’, 5.0 V supply 3.70 4.10 4.40 V
406 Voff Switch Back to Battery Supply
(VDD Power Off)
decreasing voltage at VDD; VBAT > 3.0 V
VON5 = ’0’, 3.3 V supply 2.90 3.00 3.10 V
VON5 = ’1’, 5.0 V supply 3.60 4.00 4.30 V
407 Vhys Hysteresis (VDD Switch) Vhys = Von - Voff
VON5 = ’0’, 3.3 V supply 20 50 120 mV
VON5 = ’1’, 5.0 V supply 30 80 150 mV
408 Vt()err Battery Monitoring Error
Threshold Voltage
BAT_THR = "100" 2.90 3.00 3.15 V
BAT_THR = "011" 3.00 3.10 3.25 V
BAT_THR = "010" 3.10 3.20 3.35 V
BAT_THR = "001" 3.20 3.30 3.45 V
BAT_THR = "000" 3.30 3.40 3.55 V
BAT_THR = others reserved V
409 Vhys()err Hysteresis Error Threshold 20 50 80 mV
410 Vt()wrn Battery Monitoring Warning
Threshold Voltage
BAT_THR = "100" 3.00 3.10 3.25 V
BAT_THR = "011" 3.10 3.20 3.35 V
BAT_THR = "010" 3.20 3.30 3.45 V
BAT_THR = "001" 3.30 3.40 3.55 V
BAT_THR = "000" 3.40 3.50 3.65 V
BAT_THR = others reserved V
411 Vhys()wrn Hysteresis Warning Threshold 20 50 80 mV
412 Vew Difference Battery Error-to-Warn-
ing Threshold
∆Vew = Vt()wrn - Vt()err 40 100 175 mV
Status Monitoring Output: NERR, NWRN
601 Vs()lo Saturation Voltage lo I() = 1.6 mA 0.05 0.4 V
602 Isc()lo Short-Circuit Current lo VDDS = 3.15 V, V() = VDDS 4 15 mA

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 10/51
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Typ. Max.
I2C EEPROM Interface: SCL, SDA
701 Vt()hi Input Threshold Voltage hi 1.7 2 V
702 Vt()lo Input Threshold Voltage lo 0.8 1.4 V
703 Vt()hys Input Hysteresis Vt()hys = Vt()hi - Vt()lo 75 200 500 mV
704 Vs()lo Saturation Voltage lo I() = 4 mA 0.05 0.4 V
705 Isc()lo Short-Circuit Current lo VDDS = 3.15 V, V() = VDDS 8 30 mA
706 Ipu() Pull-Up Current V() = 0 V...VDDS - 1 V -1000 -300 -30 µA
707 fclk(SCL) I2C Output Frequency at SCL 30 ffast /128 70 kHz
708 tbusy()cfg Duration of Conguration Phase IBP not adjusted; without EEPROM
(SDA stuck at GND)
0.5 1 ms
EEPROM access without I2C read error 30 40 ms
EEPROM access with I2C read error 250 500 ms
Digital Inputs CLK, SI, NCS and GPIOx
801 fclk(CLK) Permissible Clock Frequency at
CLK
SPI protocol 4 MHz
SSI protocol 4 MHz
BiSS C protocol 10 MHz
802 Vt()hi Threshold Voltage hi 1.7 2 V
803 Vt()lo Threshold Voltage lo 0.8 1.4 V
804 Vt()hys Hysteresis Vt()hys = Vt()hi - Vt()lo 100 250 500 mV
805 Ipu() Pull-Up Current at CLK, SI, NCS V() = 0 V...VDDS - 1 V -75 -30 -3 µA
806 Ipd() Pull-Down Current at GPIOx V() = 0 V...1 V 3 30 75 µA
Preset Input: PRE
901 T pulse ( PRE ) Permissible hi pulse length on
Pin PRE
2µs
902 Vt(PRE)hi Threshold Voltage hi 1.7 2 V
903 Vt(PRE)lo Threshold Voltage lo 0.8 1.4 V
904 Vt(PRE)hys Hysteresis Vt()hys = Vt()hi - Vt()lo 100 250 500 mV
905 Ipd(PRE) Pull-Down Current V() = 1 V...VDDS 8 120 300 µA
Digital Outputs SO and GPIOx
A01 tout(SO) Adaptive Slave Timeout at SO NTOA = 0
refer to timing Figure 4
tinit measured as rst 1.5 ·T(CLK) each frame.
2 / ffast tinit +
4 / ffast
120 /
ffast
A02 tout(SO) Fixed Slave Timeout at SO NTOA = ’1’, (120 / ffast) 20 µs
A03 Vs()hi Saturation Voltage hi Vs()hi = VDDS - V(), I() = -1.6 mA 0.05 0.4 V
A04 Vs()lo Saturation Voltage lo I() = 1.6 mA 0.05 0.4 V
A05 Isc()hi Short-Circuit Current hi VDDS = 3.15 V, V() = GND -15 -4 mA
A06 Isc()lo Short-Circuit Current lo VDDS = 3.15 V, V() = VDDS 4 15 mA
50%
± AArel
0% 100%
Figure 1: Denition of AB duty cycle ratio

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 11/51
OPERATING REQUIREMENTS: Serial I/O Interface: BiSS/SSI Protocol
Operating conditions:
VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Max.
SSI protocol (DIOMODE = 0x1)
I001 tframe Permissible Frame Duration *) indenite
I002 tCPermissible Clock Period refer to Elec. Char. 801 for clock frequency. 250 ns
I003 tL1 Clock Signal Hi-Level Duration 125 tout ns
I004 tL2 Clock Signal Lo-Level Duration 125 tout ns
I005 tRQ REQ Signal Lo-Level Duration 125 tout ns
I006 tP3 Propagation Delay 10 50 ns
I007 tout Slave Timeout see Elec. Char. A01
BiSS C protocol (DIOMODE = 0x0)
I008 tframe Permissible Frame Duration *) indenite
I009 tCPermissible Clock Period refer to Elec. Char. 801 for clock frequency. 100 ns
I010 tL1 Clock Signal Hi-Level Duration 50 tout ns
I011 tL2 Clock Signal Lo-Level Duration 50 tout ns
I012 tbusy Processing Time 2 tC
I013 tP3 Propagation Delay 10 50 ns
I014 tout Slave Timeout see Elec. Char. A01
I015 tS1 Setup Time:
SLI stable before MAI hi →lo
25 ns
I016 tH1 Hold Time: SLI stable after MAI hi →lo 10 ns
Note: *) Allow tout to elapse.
CLK: MA
SO: SLO
tP3
DATA
tC
DATA
tout
tframe
tL2 tL1
DATADATADATA
tRQ
Figure 2: SSI protocol timing
tinit
tout
CLK: MA
SO: SLO
Figure 3: Adaptive timeout
CLK: MA
SO: SLO
START DATA
tC
DATA
tframe
tL2 tL1
ACK
tbusy
tout
tout
tP3
Figure 4: BiSS C protocol timing

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 12/51
OPERATING REQUIREMENTS: Serial I/O Interface: SPI Protocol
Operating conditions:
VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
Item Symbol Parameter Conditions Unit
No. Min. Max.
SPI protocol (DIOMODE = 0x3)
I101 tC1 Permissible Clock Period 250 ns
I102 tW1 Wait Time:
between NCS lo →hi and NCS hi →lo
2µs
I103 tS1 Setup Time:
NCS lo before SCK lo →hi
100 ns
I104 tP1 Propagation Delay:
MISO stable after NCS hi →lo
100 ns
I105 tP2 Propagation Delay:
MISO high impedance after NCS lo → hi
100 ns
I106 tH1 Hold Time:
NCS lo after SCK lo →hi
valid for SPI mode 3 100 ns
I107 tS2 Setup Time:
MOSI stable before SCK lo →hi
100 ns
I108 tH2 Hold Time:
MOSI stable after SCK lo →hi
20 ns
I109 tP3 Propagation Delay:
MISO stable after MOSI change
mode: repeating MOSI on MISO 100 ns
I110 tP4 Propagation Delay:
MISO stable after SCK hi →lo
mode: sending data on MISO 100 ns
I111 tW2 Wait Time:
SCK stable after NCS lo →hi
2µs
I112 tH3 Hold Time:
NCS lo after SCK hi →lo
Valid for SPI mode 0 100 ns
I113 tL1 Clock Signal lo Level Duration 125 ns
I114 tL2 Clock Signal hi Level Duration 125 ns
CLK: SCLK
NCS
SI: MOSI
SO: MISO
tW1
tS1 tS2 tH2 tC1
tP1 tP2
tP3 tP4
MSB in LSB in
MSB in LSB in MSB out LSB out
tH1
tH3 tW2
tL1 tL2
Figure 5: SPI protocol timing

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 13/51
CONFIGURATION PARAMETERS
Register Map .............................. Page 14
I/O Interface Operating Modes ............ Page25
DIOMODE Serial Interface Operating Mode
GPIOMODE General Purpose I/O Operating Mode
DISI2C Disable I2C Slave Interface
Absolute Data Format ..................... Page26
RCL_ADI Revolution Counter Length
PCR_ADI Period Counts per (mech.) Revolution
ERR_PDR Error on Power Down Reset and Pre-
set
ERR_ADI Transmission of Error Bit
WRN_ADI Transmission of Warning Bit
DIR_ADI Code Direction Inversion
SBL_ADI Synchronization Bit Length
PCR_OUT Enable Period Counter Output
OS_ADI Code Offset of Absolute Position
ENSOL Enable Sign-Of-Life Counter
ABZ Incremental Output .................. Page 35
ZGATE Z Pulse Gating Scheme
MTD Minimum Transition Distance
AB_IPO AB Interpolation
BiSS Slave Interface ...................... Page36
CRCS_BiSS CRC Start Value for BiSS
CRC16_BiSS 16 Bit CRC Checksum for BiSS
NTOA_BiSS Fixed or Adaptive BiSS Timeout
Supply Switch and Monitoring ............ Page 29
BAT_THR Battery Monitor Thresholds
BAT_MON Battery Monitor Enable
MON_FRQ Battery Monitor Sampling Frequency
VON5 Set Typical Supply Voltage
Magnetic Signal Conditioning ............ Page 31
POLEWID Pole Size of Magnetic Scale
DCCOMP High Magnetic Field Strength Compen-
sation
A_MAX Maximum Angle Acceleration
MAGTHR Magnetic Field Amplitude Working
Threshold
NOMAG Behaviour of NoMagnet Detection
OSS Sine Offset Factor
OSC Cosine Offset Factor
OSD Double Offset Factor
ENOG Enable Offset Generation Block
LOWPOW Low Power Mode
Frequency and Bias Current Adjustment . Page 35
IBIAS Bias Current Calibration
Analog Output ............................ Page 32
GCOARSE Coarse Gain Factor
GAINF Fine Gain Factor
VCMOUT Common Mode Output Voltage
GAINX Cosine Channel Gain Adjustment
ENAC Amplitude Control Unit Activation
Position Preload .......................... Page 29
PCTR_PREL Period Counter Preload Value
RCTR_PREL Revolution Counter Preload Value
CRC Checksums .......................... Page44
CRC_CFG Checksum for Chip Conguration
Area: 0x00 - 0x16
CRC_PREL Checksum for PRELOAD Values
Area: 0x18 - 0x1E

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 14/51
REGISTER MAP: On-Chip RAM (Banks 0x00 - 0x0F, Address 0x00 - 0x3F)
OVERVIEW
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 0 (BSEL=0x00): General Conguration
I/O Interface Operating Modes
B0|0x00 DISI2C GPIOMODE(3:0) DIOMODE(2:0)
Absolute Data Format
B0|0x01 0 0 RCL_ADI(5:0)
B0|0x02 PCR_ADI(7:0)
B0|0x03 PCR_ADI(15:8)
B0|0x04 PCR_OUT SBL_ADI(2:0) DIR_ADI WRN_ADI ERR_ADI ERR_PDR
B0|0x05 ENSOL 0 OS_ADI(5:0)
ABZ Incremental Output
B0|0x06 AB_IPO(1:0) 0 0 MTD(1:0) ZGATE(1:0)
BiSS Slave Interface
B0|0x07 NTOA_BISS CRC16_BISS CRCS_BISS(5:0)
Supply Switch and Monitoring
B0|0x08 MON_FRQ(2:0) BAT_MON(1:0) BAT_THR(2:0)
Magnetic Signal Conditioning
B0|0x09 0 0 DCCOMP 0 POLEWID(3:0)
B0|0x0A NOMAG(1:0) MAGTHR(1:0) VON5 A_MAX(2:0)
B0|0x0B OSS(7:0)
B0|0x0C OSC(7:0)
B0|0x0D 0 0 ENOG OSD LOWPOW(1:0) GCOARSE(1:0)
Frequency and Bias Current Adjustment
B0|0x0E 0 0 0 IBIAS(4:0)
B0|0x0F 0 0 0 0 0 0 0 0
Analog Output
B0|0x10 GAINF(10:3)
B0|0x11 GAINX(2:0) VCMOUT(1:0) GAINF(2:0)
B0|0x12 0 GAINX(9:3)
B0|0x13 0 0 0 0 ENAC 0 0 0
Reserved
B0|0x14 0 0 0 0 0 0 0 0
B0|0x15 0 0 0 0 0 0 0 0
B0|0x16 INTERNAL USE : REGISTER PROTECTION LEVEL (read only)
CRC Conguration
B0|0x17 CRC_CFG(7:0)
Position Preload
B0|0x18 PCTR_PREL(7:0)
B0|0x19 PCTR_PREL(15:8)
B0|0x1A RCTR_PREL(7:0)
B0|0x1B RCTR_PREL(15:8)
B0|0x1C RCTR_PREL(23:16)
B0|0x1D RCTR_PREL(31:24)
B0|0x1E RCTR_PREL(39:32)
B0|0x1F CRC_PREL(7:0)

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 15/51
OVERVIEW
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank 1 (BSEL=0x01): BiSS ID Data
B1|0x01 EDS_BANK(7:0)
BiSS Prole
B1|0x02 BISS_PROFILE_ID_1(7:0)
B1|0x03 BISS_PROFILE_ID_0(7:0)
B1|0x04 SERIAL_3(7:0)
B1|0x05 SERIAL_2(7:0)
B1|0x06 SERIAL_1(7:0)
B1|0x07 SERIAL_0(7:0)
BiSS ID
B1|0x08 DEV_ID_5(7:0)
B1|0x09 DEV_ID_4(7:0)
B1|0x0A DEV_ID_3(7:0)
B1|0x0B DEV_ID_2(7:0)
B1|0x0C DEV_ID_1(7:0)
B1|0x0D DEV_ID_0(7:0)
B1|0x0E MFG_ID_1(7:0)
B1|0x0F MFG_ID_0(7:0)
Bank 7 (BSEL=0x07): Position Preload
Addresses Mirrored from B0|0x1A-0x1F. Usable for end user position preloading if BANK 0 is write protected
Position Preload
B7|0x18 PCTR_PREL(7:0)
B7|0x19 PCTR_PREL(7:0)
B7|0x1A RCTR_PREL(7:0)
B7|0x1B RCTR_PREL(15:8)
B7|0x1C RCTR_PREL(23:16)
B7|0x1D RCTR_PREL(31:24)
B7|0x1E RCTR_PREL(39:32)
B7|0x1F CRC_PREL(7:0)
Table 1: Register Map

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 16/51
DIRECT ACCESS REGISTER (All Banks, Address 0x40 - 0x7F)
OVERVIEW
Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank selection
0x40 BSEL(7:0)
EDS Bank Pointer (read only, mapped from bank 1 0x01)
0x41 EDS_BANK(7:0)
BiSS Prole (ready only, mapped from bank 1 0x02 - 0x07)
0x42 BISS_PROFILE_ID_1(7:0)
0x43 BISS_PROFILE_ID_0(7:0)
0x44 SERIAL_3(7:0)
0x45 SERIAL_2(7:0)
0x46 SERIAL_1(7:0)
0x47 SERIAL_0(7:0)
Revision & identication (read only)
0x4A ID(7:0)
0x4B ID(15:8)
0x4C CHIP_REV(7:0)
Absolute Data (read only)
0x50 0 0 IPO(5:0)
0x51 PC(7:0) - Period Counter
0x52 PC(15:8) - Period Counter
0x53 RC(7:0) - Revolution Counter
... RC(...) - Revolution Counter
0x57 RC(39:32) - Revolution Counter
Actual Gain Factor (read only)
0x5C AGAINS(10:3)
0x5D 0 0 0 0 0 AGAINS(2:0)
0x5E AGAINC(10:3)
0x5F 0 0 0 0 0 AGAINC(2:0)
Status Register
0x6C STATUS(7:0)
0x6C ANA_STUP NOMAG_L AMPL_ERR BAT_ERR POS_ERR CTR_ERR CFG_ERR STUP_ERR
0x6D STATUS(15:8)
0x6D MAG_ERR AC_MAX AC_MIN PRESET PDR REBOOT BAT_WRN
0x6E STATUS(23:16)
0x6E SLEEP_ST NOMAG_ST ACTIVE_ST RESET_ST
Command Register
0x76 CMD_STAT(7:0)
0x77 CMD(7:0)
BiSS ID (read only, mapped from bank 1: 0x08 - 0x0F)
0x78 DEV_ID_5(7:0)
... DEV_ID_...(7:0)
0x7D DEV_ID_0(7:0)
0x7E MFG_ID_1(7:0)
0x7F MFG_ID_0(7:0)
Table 2: Register Map for Direct Access Registers (All Banks, Addresses 0x40 - 0x7F)

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 17/51
BASIC OPERATION AND SIGNAL DEFINITIONS
The iC-PVS uses an array of hall sensors to detect the
local variation of the magnetic eld emerging from a
linear or rotary magnetic target. The target could for
example be a magnetic tape with periodic varying po-
larity and a period pitch (NS spacing) between 1 up
to 5 mm. Different supported magnetic disc scanning
arrangements are shown in Figures 6 to 8
Figure 6: Typical arrangement of iC-PVS scanning
a linear magnetic tape
Figure 7: Typical arrangement of iC-PVS scanning
a radial code disc
360°e
Figure 8: Typical arrangement of iC-PVS scanning
a 32 period axial code disc, 360 ° e marked
When used with a back-bias magnet iC-PVS can scan
ferrous gear wheels with a gear tooth module of 0.3 up
to 1.5. An example for gear wheel scanning is shown
in Figure 9.
From the periodic magnetic eld delivered by the tar-
get, the hall sensor array generates internal sensor
signals which are then further processed and passed
to the analog output, as shown in Figure 10. These
analogue sensor signals can then be used as an input
to a downstream interpolator device for high resolu-
tion sine-to-digital conversion and signal processing.
Additionally, a fast and highly efcient internal ADC con-
verts the analog signals and feeds them to the internal
absolute data engine for period counting.
The ux density shows a sinusoidal curve while target
is moved over one magnetic period. The maximum ux
density (B
max
- Elec. Char. 103) is the amplitude of this
sine curve (B
amp
- Elec. Char. 105) plus the presence of
a constant offset (B
dc
) which may be induced by a back-
-bias permanent magnet in gear wheel applications. For
magnetic code discs, the Bdc offset is zero.
Figure 9: Typical arrangement of iC-PVS scanning
a gear wheel with a back-bias magnet
S
B
moving magnetic target
x
SN N
1.0 to 5.0mm
360°e
V (j)
sin
V (j)
cos
Figure 10: Signal generation and analog data output

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 18/51
B[mT]
moving target
target displacement
1.0 to 5.0mm
= 360°e
Bamp
Bdc
Bmax
magnetic
flux density
X[mm]
magnetic period
Figure 11: Magnetic ux density at chip surface (B)
over target displacement (X)
When building magnetic rotary encoders with magnetic
code discs, a full mechanical rotation, referred to as
360 ° m, consists of multiple magnetic periods. On every
magnetic pole pair, one electrical sine period is gener-
ated on the analog output, referred to as 360 ° e. Figure
8 shows an example code disc with 32 magnetic pole
pairs. Here 360 ° e correspond to 11.25 ° m. The wheel
has to turn 11520 ° e for one full mechanical rotation of
360 ° m. The absolute FlexCount ® feature of iC-PVS
can be utilized to interpret the 32 magnetic periods as
one mechanical singleturn revolution. Excessive period
counts are processed and output as multiturn revolu-
tions. Every PCR (period count per revolution) from 1
to 65536 can be congured.

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 19/51
DEVICE OPERATING STATES
This chapter describes the rst steps for startup of
iC-PVS and the different operating states.
Initial Startup and Power-On-Reset
iC-PVS has two supply voltage inputs named VDD and
VBAT. Both refer to the same ground point at pin GND.
The system is powered via the VDD pin as long as the
applied voltage exceeds the V
on
threshold. The current
internal supply voltage can be measured at pin VDDS
which is used for further buffering with a bypass capaci-
tor. More information on the iC-PVS power scheme can
be found in chapter Supply Switch and Monitoring on
page 29.
In a common initial startup procedure the battery is con-
nected to the system via pin VBAT rst. A power-on-re-
set is performed when rising the voltage at VBAT above
the power-on-reset threshold (Elec. Char. 401). This
puts all circuitry to a dened init state.
Note:
The power-on-reset voltage threshold is no sufcient
working condition. The device will only be bootable
and utilizable if VDD is risen above V
on
(see Figure
12).
If battery backup is not used, it is necessary to tie pins
VBAT and VDD together. Pin VBAT must not be left
open. The permissible voltage range of VBAT is noted
in Elec. Char. 004.
As a second step the supply voltage is provided (VDD >
V
on
). This either happens shortly after battery insertion
or after a longer shelf life. iC-PVS will now progress
through the operating states described in Figure 12.
BOOT_ST
Read external
EEPROM
BATTERY_ST
Absolute engine
active only
NOMAG_ST
NOMAG_ = 1 (latched)
reduced absolute mode
ACTIVE_ST
Analog + Absolute
engine active
Sleep
RESET_ST
System halt
Power-On-Reset
Pin Preset
S EEP_ST
Analog + Absolute
engine disabled
Reboot CMD
VDD > Von
VDD < Voff
AMP _ERR = 1
OR
POS_ERR = 1
AMP _ERR = 1
OR
POS_ERR = 1
AMP _ERR = 0
AND
POS_ERR = 0
(VDD < Voff)
AMP _ERR = 0
AND
POS_ERR = 0
(VDD > Von)
Sleep CMD
Sleep CMD
Restart CMD
STUP_ERR = 0
CFG_ERR = 0
CTR_ERR = 0
VDD > Von
Figure 12: State diagram for device startup

preliminarypreliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 20/51
Device Operating States
On one of the following reset conditions, a system re-
set/restart is performed.
•Power-On-Reset (initial power up via pin VBAT)
•Pin PRE transition hi →low
•Command "REBOOT" (via serial interface)
Coming from a reset condition, iC-PVS always enters
the reset state. In this state pin NERR is low, indicating
that the system is not yet ready to operate. All system
functionality is halted and the current consumption is
reduced to a minimum. A fully assembled system may
be stored for future use in this condition, as the battery
current is very small (see Table 3). Communication via
any of the serial interfaces is not possible at this time.
The reset state is left only if VDD is provided (VDD >
Von).
After providing VDD, iC-PVS boots up its internal con-
guration and circuitry (boot state). Here, if present,
the external EEPROM is read-in. If the conguration
sequence from the EEPROM was successful, i.e. no
error is set by the internal diagnosis, the active state
is entered and the system is ready to operate. This is
indicated by a high level at pin NERR.
Two common failure modes can be distinguished, if the
conguration sequence from the EEPROM fails:
1. No EEPROM connected or communication with
the EEPROM fails. In that case iC-PVS will stay in
BOOT_ST, indicated by STUP_ERR = 1. iC-PVS
can be brought into ACTIVE_ST if STUP_ERR
is cleared by sending a SCLR command. In that
case iC-PVS loads a default conguration, which
means that that all conguration parameters are
set to their specied reset value.
2. The EEPROM does not contain a valid congura-
tion and the CRC check fails. In that case iC-PVS
will stay in BOOT_ST, indicated by STUP_ERR =
1. Depending on the invalid data area CFG_ERR
and/or CTR_ERR are set. BOOT_ST is only left
if the CRC matches the conguration data.
In normal operation, the iC-PVS switches between
active state (ACTIVE_ST) and battery state (BAT-
TERY_ST), depending on the voltage level at VDD.
In active state, the absolute data and analog singleturn
stages are active. Communication is possible via any
serial interface. In battery state, only the period counter
position is tracked for true absolute encoding. Serial
communication is inactive to safe power.
Additionally a NoMagnet state (NOMAG_ST) is avail-
able to handle a loss of magnet situation. This can
be an emergency state to handle a damaged encoder
system or a normal use-case for storage of the encoder
PCB without a magnetic target. Only the absolute
engine is active in a power reduced mode. Communi-
cation is possible via any serial interface in this state
as long as the device is VDD powered.
Comparable to the NoMagnet state, a sleep state can
be entered with the SLEEP command. Here, position
acquisition is completely disabled, but communication
via the serial interfaces is still possible as long as the
device is VDD powered. Command RESTART will put
iC-PVS back in active mode again.