Icom IC-2GA User manual

o
ICOM
SERVICE
MANUAL
VHF FM TRANSCEIVER
IC-2GA
1C-2GAT
IC-2GE
Downloaded by
RadioAmateur.EU
Icom Inc.

INTRODUCTION
This service manuaJ contains the latest service information for the
IC-2GA/GAT/GE VHP FM TRANSCEIVER at the time of going to press-
The following version lumbers ere often used in this maunaL
VERSION VERSION NUMBER
I02GA Australia 07
IC-2GA Southeast Asia 08
IC*2GA U.S.A. 08
IC-2GAT
1
Southeast Asia
j
09
IC-2GAT U.S.A. 05
IC-2GE Europe |02
IC-2GE Italy 04
^ORDERING PARTS
For the fastest service^ please supply all of the following information
when Ordering pans from your dealer or Icom Service Center:
Desired date of delivery
2,10-digit ordering number (for mechanical parts only)
3, Part number and name
4, Equipment model and unit name
5^ Quantity required
Example: 8310003850, No, 0*3 PH 60 1.4 x2,5 Ni, screw, IC-2GAT
DTMF unit, 3pcs-
^R^AIR NOTE
1, PO MOT open transceiver covers until the transceiver is discon-
nected from apower source,
2, DO MOT force any of the variable components. Turn them slowly
and smoothly.
3, DO NOT short any circuits or electronic parts.
4, An insulated tuning tool MUST BE used for all adjustments-
5- DO NOT keep power on for along time when the transceiver is
defective.
6. DO NOT transmit power into a signal generator or sweep gener-
ator.
7. Always connect a30dB or 40dB attenuator between the transceiv-
er and adeviation meter or spectrum analyzer when using such
test equipment.
3- Read the Instructions of test equipment thoroughly before con-
necting the equipment to the transceiver
^
III]
1
1
1
I
III!

TABLE OF CONTENTS
SECTION 1SPECIFICATIONS 1-1
SECTION 2OUTSIDE AND INSIDE VIEWS
2-1 FRONTAND SIDE PANELS 2-1
2-2 TOP PANEL 2-2
2-3 FUNCTION DISPLAY 2-2
2-4 MAIN UNIT 2-3
2-5 RFUNIT 2-4
2-6 SPEAKER AND DTMF UNITS 2-4
SECTION 3BLOCK DIAGRAM 3-1
SECTION 4CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS 4-1
4-2 TRANSMITTER CIRCUITS 4-2
4-3 PLL CIRCUIT 4-2
4-4 POWER SUPPLY CIRCUITS 4-3
4-5 OTHER CIRCUITS 4-4
4-6 CPU (IC501) PORT ALLOCATION 4-5
4-7 MATRICES 4-6
SECTION 5MECHANICAL PARTS AND DISASSEMBLY 5-1
SECTION 6ADJUSTMENT PROCEDURES
6-1 PLL ADJUSTMENT 6-1
6-2 RECEIVER ADJUSTMENT 6-2
6-
3TRANSMITTER ADJUSTMENT 6-3
SECTION 7BOARD LAYOUTS
7-
1INTERCONNECTION 7-1
7-2 LOGIC-A UNIT 7-2
7-3 LOGIC-B UNIT 7-3
7-4 RF UNIT 7-5
7-5 MAIN UNIT 7-7
7-6 OTHER UNITS 7-9
SECTION 8PARTS LIST 8-1
SECTION 9SCHEMATIC AND VOLTAGE DIAGRAM 9-1
SECTION 10 BC-35, BC-36 AC BATTERY CHARGERS
10-1 SPECIFICATIONS 10-1
10-2 PANEL DESCRIPTION 10-1
10-3 BLOCK DIAGRAM 10-2
10-4 CIRCUIT DESCRIPTION 10-3
10-5 MECHANICAL PARTS AND DISASSEMBLY 10-4
10-6 PARTS LIST 10-6
10-
7SCHEMATIC AND VOLTAGE DIAGRAM 10-7
SECTION 11 UT-40 TONE SQUELCH UNIT (sold separately)
11-
1CIRCUIT DESCRIPTION 11-1
11-2 BOARD LAYOUT 11-2
11-3 SCHEMATIC AND VOLTAGE DIAGRAM 11-3

SECTION 1SPECIFICATIONS
GENERAL
•Frequency coverage
•Mode
•Tuning step increment
•Memory channels
•Antenna impedance
•Power supply requirement
•Current drain
(at 13.2 VDC)
•Usable temperature range
•Dimensions
•Weight
MODEL VERSION OPERATIONAL RANGE (MHz)
RECEIVE TRANSMIT
IC-2GA #06(U.S.A.)
#07 (Australia)^
#08 (Southeast Asia) 138.00 ~174.00* 140.00 -150.00*
IC-2GAT #05 (U.S.A.)
#09 (Southeast Asia)
IC-2GE #02 (Europe) 144.00 ~146.00 144.00 ~146.00
#04 (Italy) 138.00 ~174.00* 138.00 ~174.00*
*Specifications guaranteed for 144.00 ~148.00 MHz.
^Operational range: 144.00 ~148.00 MHz.
FM (F3)
IC-2GA, IC-2GAT 5,10,15, 20 or 25 kHz
IC-2GE 12.5 or 25 kHz
IC-2GA, IC-2GAT 20 plus aCALL channel
IC-2GE 20
50 Ounbalanced
5.5 V~16.0 VDC (negative ground)
RECEIVE; power saver on, 10 mA (typical); max. aud. output, 250 mA
TRANSMIT: HIGH, 1.8 A; LOW, 900 mA
-10°C ~+60X (14T ~140°F)
All versions: 65(W)x35(D) mm; 2.6(W)x1.4(D) in
IC-2GAT(U.S.A.) with BP-70 :151(H) mm; 5.9(H) in
IC-2GA, IC-2GAT (Southeast Asia) with BP-4: 140(H) mm; 5.5(H) in
IC-2GA(U.S.A.), IC-2GE with BP-3 :130(H) mm; 5.1(H) in
IC-2GAT(U.S.A.) with BP-70: 500g(1.1lb)
IC-2GA, IC-2GAT (Southeast Asia) with BP-4: 450 g(1.0 lb)
IC-2GA (U.S.A.), IC-2GE with BP-3: 430 g(0.9 lb)
TRANSMITTER
•Output power (at 13.2 VDC)
•Modulation system
•Max. frequency deviation
•Spurious emissions
•Microphone impedance
HIGH, 7W; LOW, 1W
Variable reactance frequency modulation
±5 kHz
Less than -60 dB
2kO
RECEIVER
•Receiver system
•Intermediate frequencies
•Sensitivity
•Spurious rejection
•Audio output power
•Audio output impedance
Double-conversion superheterodyne
1st 16.9 MHz
2nd 455 kHz
Less than 0.25 pV for 12 dB SINAD
Less than -60 dB
More than 400 mW at 10% distortion with an 8Qload
80
All stated specifications are subject to change without notice or obligation.
1-1

SECTION 2OUTSIDE AND INSIDE VIEWS
2-1FRONT AND SIDE PANELS
SQUELCH CONTROL-
ANTENNA CONNECTOR
FUNCTION SWITCH
-
PTT SWITCH
LIGHT SWITCH-
BATTERY PACK
RELEASE BUTTON"
VOLUME CONTROL/
POWER SWITCH
-TRANSMIT INDICATOR
DTMF KEYBOARD
'0C-2GATonly)
SPEAKER-
CALL SWITCH KC-2GA/GAT)
TONE CALL SWITCH 0C-2GE)
RF OUTPUT POWER SWITCH -
MONITOR SWITCH
-
EXTERNAL MICROPHONE
‘AND SPEAKER JACKS
MICROPHONE
-BATTERY PACK
2-1

2-2 TOP PANEL
2-3FUNCTION DISPLAY
TONE AND SQUELCH
2-2

ICOM
circuit
2-3

2-5 RFUNIT
LPfViSnEanna
switching circuit
Pa msdule
0C4? SC-10SO>
Hefsrencs cryctaE
^X3; CH243]
Bandpass filtsr
2nd IF circuit
2ftd LO crystal [XI: CR177I
Isi IF cfrcuil
VCO UHIT
PLL ciicuit
?ll IC i\C2; PU2W1}
Z•6SPEAKER AND DTMF UNITS
MiCrnphanA
DTMF encoder crystal
rKSOIj 3.5S MHt)
DTMF UNJT
(IC-2GAT only}

IC1
MC3357P
riLIri
16.445MH2
le.SMHz
3-1
TONE
UNIT
MAIN
UNIT

SECTION 4CIRCUIT DESCRIPTION
4-1RECEIVER CIRCUITS
(1) ANTENNA SWITCHING CIRCUIT (RF UNIT)
RF signals enter the antenna connector and pass through a
series of Chebyshev low-pass filters (LI, L2, Cl, C2, C6, C7,
C8). The signals are then applied to the antenna switching
circuit, which employs atwo-stage diode switching system
(L3, L4, C4, C5, C11, D1),
(2) RF CIRCUIT {RF UNIT)
The signals from the antenna switching circuit are ampli-
fied at Q1. Amplified signals are applied to abandpass
filter (Cl 7, C22, C25, D3, D5, D6, L6'-L8) where out-of-band
signals are suppressed. D2, D3, D5, and D6 are varactor
diodes which track the bandpass filters with the PLL lock
voltage.
(3) 1st MIXER CIRCUIT {RF UNIT)
The signals are applied to the gate of the first mixer (Q2). A
frequency oscillated in the PLL passes through the LO
switching circuit (D16), and is applied to the source of Q2.
The received signals are mixed with the PLL output to
produce the first IF of 16.9 MHz, which is picked up at L9.
{4) 1st IF AMPLIFIER {RF UNIT)
The first IF signal is applied to aset of two monolithic filters
(FI1) which determine the bandwidth (15 kHz/”3 dB) and
suppress unwanted heterodyned signals. The first IF signal
is amplified at Q3, and then applied to IC1 (pin 16) via C34.
Using XI, IC1 oscillates a2nd LO frequency of 16.445 MHz.
The second IF of 455 kHz is output from pin 3. Applied to
IC1 (pin 5), the second IF is amplified at the IC's internal
limiter amplifier. The amplified signal is applied to the
quadrature detector (IC1, pins 7, 8; X2). An AF signal Is
output from the quadrature detector through pin 9.
After passing through the ceramic filter (F12), aportion of
the second IF is applied to the S-meter amplifier (Q4, Q5).
{6) AF CIRCUIT {MAIN UNIT)
The AF signal is applied to the de-emphasis circuit (C55,
R33), and then to the AF amplifier (Q219, Q220). The
de-emphasis circuit is an integrated circuit with frequency
characteristics of -“6 dB/octave (300 Hz'-'3 kHz). Passing
through the volume control (R502), the signals are ampli-
fied by 1C201, and sent to the speaker.
{7) SQUELCH CIRCUIT {RF AND MAIN UNITS)
Aportion of the AF signal from !C1 (pin 9) is applied to pin
10 (the active filter). The SQL pot (R501) adjusts the input
level at pin 1. The active filter in IC1 amplifies noise
components of frequencies of 20 kHz and above, and
outputs the resulting signals from pin 11. The signals pass
through D9 for noise detection. If the detected noise
voltage is high, Q18 Is turned on; Q202 is turned off,
cutting off voltage buffer (Q204, Q205) output voltage. In
this way, IC201 is deactivated when the squelch is closed.
When transmitting, adecrease In Q202 voltage cuts off
voltage buffer output voltage —turning off IC201,
{5) 2nd IF AND DEMODULATOR CIRCUITS
{RF UNIT)
IC1 contains the second local oscillator, the second mixer, a
limiter amplifier, and the quadrature detector.
(8) LOCAL OSCILLATOR CIRCUIT (RF UNIT)
Q12 buffer amplifies the VCO output, which then passes
through D16 and is applied to the source of Q2.
IF CIRCUIT
AF output
to Q219
4-1

4-2 TRANSMITTER CIRCUITS
(1) MICROPHONE AMPLIFIER (MAIN UNIT)
AF signals from the built-in condenser microphone or from
the external microphone jack are amplified at alimiter
amplifier (IC205), and are pre-emphasized to 6 dB/octave
(300 kHz). Pin 1outputs asquare wave which con-
tains many high harmonic components. The signals pass
through the splatter filter in IC205 where signals of 3kHz
and above are attenuated. The signals from pin 7are
applied to the VCO UNIT for frequency modulation (FM).
(2) DRIVE AMPLIFIER (RF UNIT)
The VCO output is buffer amplified at Q12. Passing
through D16, the signals are then amplified at the drive
amplifier (Q10).
(3) RF POWER AMPLIFIER (RF UNIT)
Q10 output Is amplified at IC3 to 7W(HIGH) or 1W(LOW).
When transmitting, the RF signals amplified at IC3 pass
through the antenna switching diode (D15) and the low
pass filter where harmonic signals are rejected. The signal
is then applied to the antenna connector.
(4)
APC CIRCUIT (Automatic Power Control)
(RF UNIT)
IC3 output passes through the APC detector circuit (D13,
D14, L15, etc.) where its RF output level is detected.
The detected output, compared at the differential amplifier
(Q13) to the reference voltage output of the power set
circuit, is applied to the base of 015.
When the antenna is matched at 50 O, the detected output
is at aminimum. When mismatched, the detected output
increases. The current at the collectors of Oil and Q15, as
well as the gain of the driver (Q10), decreases until the
detected output and the reference voltage become equal.
In this way, the power module (IC3) is protected from
damage.
017 acts as aswitch for the reference voltage used in the
APC circuit. In this way, HIGH/LOW transmit output power
switching is accomplished.
APC CIRCUIT RX 1st mixer current is controlled
4-3 PLL CIRCUITS
(1) GENERAL
The PLL circuit, using aone-chip PLL 1C (IC2), directly
generates the desired frequency. IC2 sets the dividing ratio
based on serial data from the CPU (IC501), and compares
the phases of the VCO signal and the reference oscillator
frequency. It detects the out-of-step phase and outputs it.
(2) REFERENCE OSCILLATOR CIRCUIT
(RF UNIT)
X3 oscillates a10 MHz signal. IC2 divides this signal with
N-data from the CPU. In this way, one of six tuning steps
(5, 10, 12.5, 15, 20, 25 kHz) can be selected.
(3)
CHARGE PUMP AND LOOP FILTER CIRCUITS
(RF UNIT)
Phase-detected signals from pins 5and 12 are converted to
DC voltage by the charge pump (Q6'^Q8) and the lag-lead
loop filter (R48-R50, C81, Cl 12 and Cl 13).
The frequency at which the VCO oscillates is controlled by
varactor diodes (D703, D704). DC voltage (PLL lock voltage)
is provided through the loop filter. The output of the loop
filter passes through Q9, and is used to control the
bandpass filter (D3, D5, D6) in the receiver RF circuit.
When the power save function is on, the charge pump
control circuit (020—022, D18) cuts off the charge pump
and the VCO.

(4) VCO CIRCUIT (RF UNIT)
D701 changes the inductive reactance of the oscillator
(Q702), shifting the receive and transmit frequencies.
Varactor diode D702 provides frequency control. Q703
buffer amplifies the VCO output signal; Q701 buffer ampli-
fies the PLL feedback signal.
(5) UNLOCK SENSOR CIRCUIT
When the PLL circuit is unlocked, pin 7of IC2 is "LOW" and
a"LOW" signal is applied to the unlock sensor (023). The
unlock sensor outputs acurrent amplified "LOW" signal to
the CPU, IC503 (pin 60).
DATA
CK
PLL STLB
4-4POWER SUPPLY CIRCUITS
(1)
VOLTAGE LINES
DESC8IFT10N
.. ..
Vcc
Battery pack output that passes through the
power switch. Vcc is applied to the power
module (iC3), the AF power amp regulator, and
the following 5Vlines.
+5
Common 5Vcurrent-amplified at (Q207, Q208)
using 1C output as a reference voltage. The
heat factor of the voltage at Q207 (Vbe) equals
that of the junction voltage at Q208. The
output is stable even with regard to tempera-
ture changes.
+5S Common 5Vcontrolled by the power save
function. Current-amplified at Q213, Q214.
R+5 5Vcontrolled by the power save function.
Current-amplified at Q211, Q212. Used by the
receiver circuits.
T+5 5Vcurrent-amplified at Q209, Q210. Used by
the transmitter circuits.
(2) VOLTAGE REGULATOR CIRCUIT
(MAIN UNIT)
When the battery voltage is 5.5—16 V, the regulator (IC204)
outputs areference voltage of 5V. The noise components
are removed by the noise filter (C220, R213). This output is
applied to the current amplifier (0207, 0208).
(3) CPU POWER SUPPLY CIRCUIT (LOGIC UNIT)
When the power is turned off, voltage from the lithium
battery is applied to the CPU, IC501 (pin 52) via D502.
4-3

4-5 OTHER CIRCUITS
(1)
S/RF METER CIRCUIT (LOGIC UNIT)
The voltages detected at the S-meter detector (Q4, Q5, D7)
or the APC detector (D13, D14) are applied to pin 2of IC502
(1/2). When the voltage level is detected, IC503 (pin 52)
outputs a"'HIGH" signal. Because the signal passes
through an integrator circuit (C507, R517), the voltage at
pin 3increases with time. When the voltage at pin 3is
greater than that at pin 2, pin 1outputs a"HIGH" signal to
IC503 (pin 51). When IC503 (pin 52) becomes "HIGH," the
S/RF level, calculated from the delay time, is displayed.
a/di a/do
(2) LAMP CIRCUIT (LOGIC UNIT)
When the LIGHT SWITCH Is pushed, the IC503 (pin 53)
LAMP signal becomes "HIGH." The current of this signal is
amplified at Q501 to light the two chip-type LED (DS502,
DS503).
(3) LOW VOLTAGE DETECTOR CIRCUIT
(LOGIC UNIT)
-I-5S is divided over R523 and R524. 1.16 Vare applied to
IC502B (pin 5). The Vcc voltage, divided over R525 and
R526, is applied to pin 6. When the Vcc voltage exceeds
5.7 V, the voltage at pin 6becomes greater than that at pin
5. Output pin 1becomes "LOW." When the Vcc voltage is
less than 5.7 V, the voltage at pin 5exceeds that at pin 6.
Pin 1outputs "HIGH." The TRANSMIT INDICATOR does not
light even when transmitting.
(4) BEEP CIRCUIT (MAIN UNIT)
When some switches are pushed, the CPU sends BEEP data
to IC102. Beep tones are output from IC202 (pin 5) in
square waves of about 1kHz and 500 Hz.
(5) POWER SAVER CIRCUIT (MAIN UNIT)
When the squelch Is closed, IC503 (pin 41) BUSY signal is
"LOW." If no operation is performed for more than 30
seconds, the power save function is automatically acti-
vated. After 30 seconds, the IC503 sends power save data
to IC202.
SQL LOW
Using this data, IC202 (pin 12) alternately outputs "HIGH"
(shut-down) for 500 msec, and "LOW" (standby) for 125
msec. This output, applied to IC203D (pins 5and 6) and
IC023C (pin 9), controls the bases of 021 1and 0213 —thus
controlling +5S and R+5.
If asignal is received, the BUSY signal becomes "HIGH,"
shutting off the power save function. If asignal is not
received, "HIGH" and "LOW" signals continue to alternate.
(6) SUBAUDIBLE TONE ENCODER
(IC-2GA, IC-2GAT)
When the tone encoder is turned on, the X601 reference
frequency (3.579545 MHz) is divided by IC60Vs dividing
ratio based on 6-bit data from IC503. Atone
(67.0 Hz~250.3 Hz) is output from pin 1. The tone output
passes through R601 for deviation adjustment and is
supplied to the MAIN UNIT.
(7) TONE CALL (IC-2GE)
Pushing the TONE CALL SWITCH (S206) turns on 0218. A
voltage is applied to IC206. IC206 divides 7.168 MHz by
4,096; and outputs a1750 Hz tone through pin 4. R242
provides deviation adjustment.
(8) DTMF ENCODER (IC-2GAT)
IC801 generates DTMF tone signals. When transmitting,
T-i-5 Vare applied to IC801 (pins 1and 2). If, at this time,
data are entered with the keypad, the frequency (3.58 MHz)
oscillated by X801 is divided by the appropriate dividing
ratio.
Pin 17 outputs audio frequencies coresponding to ROW
and COL input. R801 provides deviation adjustment. When
akey is pushed, a"HIGH" signal is output to pin 11. 0801
is turned on for about one second to maintain transmission
without pushing the PTT switch.
4-4

(9) T5/R5 SWITCHING CIRCUIT (MAIN UNIT)
When the PTT switch (S205) is pushed, Q216 Is turned on.
The collector of Q215 outputs a"LOW" signal to the CPU
(IC503, pin 44). Using the "LOW" signal, the CPU sends
TRANSMIT data to IC202. IC202 (pin 13) outputs a"HIGH"
signal to IC203C (pin 8) and IC203A (pins 12 and 13),
controlling IC203C (pin 10) —shutting off R+5.
Releasing the PTT switch turns off 0216. The collector of
0215 outputs a"HIGH" signal which causes the CPU to
send RECEIVE data to IC202. IC202 (pin 13) outputs a
"LOW" signal to IC203C (pin 8) and IC203A (pins 12 and
13), controlling IC203C (pin 10) —turning on R+5S.
IC203A (pin 11) outputs a"HIGH" signal to IC203B (pin 2)
controlling the base of 0209 —turning off T+5.
IC203A (pin 11) outputs a"LOW" signal to IC203B (pin 2),
controlling the base of 0209 —turning on T+5.
T5/R5 SWITCHING CIRCUIT
+5S R+5 '
H: ON
L: OFF
Q213, Q214
ABY
LH
LHL
HLL
H~T~
Vcc
T+5-
10
Q211, Q212
i\a\
a(/)
11 12 13 14
IC202 SHIFT REGISTER
5V>-^
H: ON
L: OFF
Q209, Q210
12
13
-I/O STL8
-DATA
-CK
4-6CPU (IC501) PORT ALLOCATION
PIN STANDBY OPEfU^TION ft- ....
NAME DESCRIPTION
iH/L
1~28 S13-S31 COM
29 P40 0L0LKSO Output for the SW matrix.
30 P41 0L0LKS1 Output for the SW matrix.
31 P42 0L0LKS2 Output for the SW matrix.
32 P43 0L0LKS10 Output for the SW matrix.
33 Vss Ground
34 P50 0L1LKRO Input for the matrix return.
35 P51 0L1LKR1 Input for the matrix return.
36 P52 0L1LKR2 Input for the matrix return.
37 P53 0L1LKR3 Input for the matrix return.
38 POO 1L11INT4 Standby detector input.
Goes to standby at the end of apulse.
39 P01 1L0JCK
Serial data output clock:
a) PLLN
b) CTCSSTONE
c) I/O EXPANSION
40 P02 1L0HDATA Serial data output synchronized with CK.
41 P03 1L1HBUSY BUSY input used when asignal is received.
42 P10 1L1LLAMPI Input used for lamp output HI/LOW control.
43 P11 1L1LMON1 .
Input used for ON/OFF control of SQL OFF and BEEP
output.
44 PI 2 1
1L1LPTT Tx/Rx switching input.
45 PI 31L1LFUNC Switches matrix input to FUNC functions.
46 P20 0L0LKSI1 Output for the initial matrix.
4-5

47 P21
48 P22
49 P23
50 P30
51 P31
52 P32
53 P33
54
55-59
60 P60
61 P61
62 P62
63 P63
64 P70
65 P71
66 P72
67 P73
68
69-80 S0-S12
Al/OSTB
APLSTB
ACTSTB
HDET
HSRFI
HSRFO
HLAMPO
5V VDD
XTAL
LUNLK
LHI/LOW
LENC/DEC
LENC
HDAO
H DAI
HDA2
HDA3
LRESET
Strobe signal output for I/O expansion serial data.
PLL serial data, strobe signal output.
CTCSS serial data, strobe signal output.
Data equalizer signal input from the CTCSS decoder.
S/RF meter comparison input.
S/RF meter comparison output.
LCD backlight LAMP output.
PLL unlock input.
Used for HLC output HI/LOW and KEYLOCK ON/OFF
switching.
Determines whether or not aCTCSS encoder/decoder
(MN6520) is online.
Determines whether or not aCTCSS encoder
(S7116A) is online.
Turns off standby.
When resetting, becomes "LOW" for Initialization.
LCD driver output
[100 kHz] DN
[10 kHz] DN

SECTION 5MECHANICAL PARTS AND DISASSEMBLY
DESCRIPTION ORDERING
NUMBER OTY mMBUl DESORPTION ORDERING
NUMBER QTY
©No. 0-3 PH BO 1.4 X2.5 Ni 8810003850 50Lens 8930011940 1
573 keyboard (#05, 09) 8010006870 10No. 0-1 PH M2 X2.5 8810004870 2
PH BO 2X31.5 ZK 8810004000 40Button K-106 8610004210 1
0Rear panel 8010006860 10Button K-107 8610004220 2
0No. 0-1 PH BO 2X48810004800 40No. 0-1 PH M2 X2.5 8810004870 3
Speaker plate 8930012100 10No. 0-3 PH BO 1.4 X4.5 Ni 8810004980 6
©Casing seal (side) 8930011990 10Spacer plate 8930012140 1
Microphone holder 8930011930 10Top panel switch seal 8930011960 1
0Casing seal (center) 8930011870 10Top panel* (#05, 06, 07, 08, 09) 8310011520 1
(§) No. 0-1 PH M2 X5ZK 8810000530 2Top pnet* (#02, 04) 8310011940 1
(0) PTT button 8930011910 10VR angle plate 8930012120
-—
—
—
—
1
PTT holder-1 8930011920 10LCD contact strip SRCN573 8930012090 2
PTT switch rubber 8930011950 10LCD reflector 8010006980 1
No. 0-3 PH BO 1.4 X2.5 NI 8810003850 20LCD LD-B9213J 5030000280 1
Front switch plate 8930012130 10LCD window plate 8310011530 1
Switch seal
(#05, 06, 07, 08, 09) 8310011820 10PH M2 X48810000010 4
0Jack cover flap 8930011980 1
Switch seal (B)
(#02, 04) 8310011920 10Antenna connector BNC-R111-E
(includes nut) 6510007130 1
Speaker seal 8930011580 1
573 standoff-
1
8930012081 4
0
Front panel (A)
(#06, 07, 08) 8210002950 10No. 0-1 PH M2 X8ZK 8810004840 2
T.T. front panel
(#05, 09) 8210002880 10Connection spring 8930005980 1
0BuH M2 X6Ni 8810002580 1
Front panel (B) (#02, 04) 8210002960 10Release button 8930008610 1
0Knobs
(PowerA/olume/Squelch) N-126 8610004230 20Sliding guide 8010006990 1
0PH M2 X6ZK 8810004860 20FH M2 X4Ni 8810002310 4
VR nut (E) 8830000550 20Screw lug M2 8860000010 2
Top panel* (#05, 06, 07, 08, 09) 8310011520 10Contact holder 8930011880 1
Top panel* (#02, 04) 8310011940 10BuH M2 X6Ni 8810002580 1
0Top panel seal 8930011970 10Latch plate (A)-1 8930008601 1
*The top panel is available completely assembled, i.e., with parts and @built-in.
#05, 06, 07, 08, 09: 8210002870
#02, 04 :8210003060
Screw type Screw: M2 x6, M2 x3, etc. Self-tapping screw: BO 2x4, BO 2x31.5, etc. Precision-type screw: No. 0-1
Head style of screws PH: Pan head BuH: Button head FH: Flat head
5-1

•LOGIC-A AND LOGIC-B UNITS •MAIN UNIT

SECTION 6ADJUSTMENT PROCEDURES
6-1 PLL ADJUSTMENT
TEST NSTtAJMEMTS REQUmO MEASUFtEMENT CONNECTION LOCATION
AC POWER SUPPLY
*Oulpuft VDllagq
«Ourrftnt ca(»acily
i2^ fftEQLPENCY COUNTER
*F/aquency fange
*Ffaquency accuracy
*Sanartiviiy
mOC VOLTMETEft
*InpuE impadanca
:13,2 VDC
:3Aqr mars
;±1 ppm pr batter
:100 mV ar bettsr
50 kftfDC or better
TEflMINAL
To separata th* FF UNU ffom tha MAIN UNIT, sas the diagram
drt p. 0-1 ^fa^d"0d1l.
ADJOSnMENT ADJUSTMENT CONOmONS MEASUREMENT VALUE ADdUSTWENT POIKT
UNIT LOCATION UNIT ADJUST
REFERENCE
FREQUENCY «Ccnn^ aBD n[fuinrKly loed.
mFnaquBHcy: 145.00 MHr
*Trarifimrt
Top
panel wupis the fr^usnoy
counter Eo ths dummy IcKsd.
14S.00MH1 Rf CM
LOCK VOLTAGE aFrequenov- 146.00 MKz
•Recaivs
Rf Connect th^ v>9ttm6fter rq CPI. 1.5 V1VCO
1
L702
RF AND VCO UNITS
C70
HEFEFENCE
FREOJENCY
ADJUSTMENT
Downloaded by
RadioAmateur.EU
LT02
{under aluminum tape]
LOCK VOLTAGE
ADJUSTMENT
CP1 {gold-plated
rectangle to the lalt
of CSii
AEFEFENCE FfteOUENCY
ADJUSTMENT
6-1