ICP DAS USA A-812PG Instructions for use

A-812PG
Hardware User’s Manual
Warranty
All products manufactured by ICP DAS are warranted against defective materials for a
period of one year from the date of delivery to the original purchaser.
Warning
ICP DAS assume no liability for damages consequent to the use of this product. ICP
DAS reserves the right to change this manual at any time without notice. The information
furnished by ICP DAS is believed to be accurate and reliable. However, no responsibility is
assumed by ICP DAS for its use, nor for any infringements of patents or other rights of third
parties resulting from its use.
Copyright
Copyright 1997 by ICP DAS. All rights are reserved.
Trademark
The names used for identification only may be registered trademarks of their respective
companies.
License
The user can use, modify and backup this software on a single machine.
The user may not reproduce, transfer or distribute this software, or any copy, in whole or in
part.
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 1

Tables of Contents
1. Introduction ___________________________________________________________4
1.1 General Description______________________________________________________ 4
1.2 Features _________________________________________________________________ 4
1.3 Specifications_____________________________________________________________ 5
1.3.1 Power Consumption : ___________________________________________________________5
1.3.2 Analog Inputs _________________________________________________________________5
1.3.3 A/D Converter_________________________________________________________________5
1.3.4 DA Converter _________________________________________________________________6
1.3.5 Digital I/O____________________________________________________________________6
1.3.6 Interrupt Channel ______________________________________________________________6
1.3.7 Programmable Timer/Counter_____________________________________________________7
1.3.8 Direct Memory Access Channel (DMA) ____________________________________________7
1.4 Applications______________________________________________________________ 8
1.5 Product Check List ________________________________________________________ 8
2 Hardware Configuration _________________________________________________9
2.1 Board Layout_____________________________________________________________ 9
2.2 I/O Base Address Setting __________________________________________________ 10
2.3 Jumper Setting __________________________________________________________ 11
2.3.1 JP3 : D/A Internal Reference Voltage Selection______________________________________11
2.3.2 JP1, JP2 : D/A Int/Ext Ref Voltage Selection ______________________________________12
2.3.3 JP8 : A/D Trigger Source Selection _______________________________________________12
2.3.4 JP5 : Interrupt Level Selection ___________________________________________________13
2.3.5 JP9 : User Timer/Counter Clock Input Selection _____________________________________14
2.3.6 JP6 : DMA DACK Selection, JP7 : DMA DRQ Selection _________________15
2.4 I/O Register Address______________________________________________________ 16
2.4.1 8254 Counter_________________________________________________________________17
2.4.2 A/D Input Buffer Register_______________________________________________________17
2.4.3 D/A Output Latch Register ______________________________________________________18
2.4.4 D/I Input Buffer Register _______________________________________________________19
2.4.5 Clear Interrupt Request_________________________________________________________19
2.4.6 A/D Gain Control Register ______________________________________________________20
2.4.7 A/D Multiplex Control Register __________________________________________________21
2.4.8 A/D Mode Control Register _____________________________________________________21
2.4.8 A/D Software Trigger Control Register ____________________________________________23
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 2

2.4.9 D/O Output Latch Register ______________________________________________________24
2.5 Digital I/O ______________________________________________________________ 25
2.6 8254 Timer/Counter ______________________________________________________ 26
2.7 A/D Conversion __________________________________________________________ 27
2.7.1 A/D conversion flow___________________________________________________________28
2.7.2 A/D Conversion Trigger Modes __________________________________________________29
2.7.3 A/D Transfer Modes ___________________________________________________________29
2.7.4 Using software trigger and polling transfer _________________________________________30
2.8 D/A Conversion __________________________________________________________ 31
2.9 Analog Input Signal Connection ____________________________________________ 32
2.10 Pin Assignment___________________________________________________________ 33
2.11 Daughter Board __________________________________________________________ 34
2.11.1 DN-20 for Analog input / output_________________________________________________34
2.11.2 DB-16P for Digital input_______________________________________________________34
2.11.3 DB-16R for Digital output _____________________________________________________34
3. Calibration___________________________________________________________35
3.1 Calibration VR Description ________________________________________________ 36
3.2 D/A Calibration Steps_____________________________________________________ 37
3.3 A/D Calibration Steps_____________________________________________________ 37
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 3

1. Introduction
1.1 General Description
The A-812PG is a high performance, multifunction analog, digital I/O board for the PC
AT compatible computer. The A-812PG provides low gain (1, 2, 4, 8, 16). The A-812PG
contains a 12-bit ADC with up to 16 single-ended analog inputs. The maximum sample rate
of A/D converter is about 62.5K sample/sec. There are two 12-bits DAC with voltage outputs,
16 channels of TTL-compatible digital input, 16 channels of TTL-compatible digital output
and one 16-bit counter/timer channel for timing input and output.
1.2 Features
 The maximum sample rate of A/D converter is about 62.5 K sample/sec
 Software selectable input ranges
 PC AT compatible ISA bus
 A/D trigger mode : software trigger , pacer trigger, external trigger
 16 single-ended input signals
 Programmable low gain : 1,2,4,8,16
 2 channel 12-bit D/A voltage output
 16 digital input /16 digital output (TTL compatible)
 Interrupt handling
 1 channel general purpose programmable 16 bits timer/counter
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 4

1.3 Specifications
1.3.1 Power Consumption :
 +5V @960 mA maximum, A-812PG
 Operating temperature : -20°C ~ 60°C
1.3.2 Analog Inputs
 Channels : 16 single-ended
 Input range : (software programmable)
A-812PG:bipolar : ±10V, ±5V, ±2.5V, ±1.25V, ±0.625V, ±0.3125V
(input range : ±10V or ±0.3125V by Jumper JP4 selected )
 Input current : 250 nA max (125 nA typical ) at 25 deg.
 On chip sample and hold
 Over voltage : continuous single channel to 70Vp-p
 Input impedance : 10 Ω// 6pF
10
1.3.3 A/D Converter
 Type : successive approximation , Burr Brown ADS 774
or SIPEX-SP774B ( equivalent)
 Conversion time : 8 microsec.
 Accuracy : +/- 1 bit
 Resolution : 12 bits
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 5

1.3.4 DA Converter
 Channels : 2 independent
 Type : 12 bit multiplying , Analog device AD-7541
 Linearity : +/- 1/2 bit
 Output range : 0~5V or 0~10V jumper selected , may be used with other AC or
DC reference input Maximum output limit +/- 10V
 Output drive : +/- 5mA
 Settling time : 0.6 microseconds to 0.01% for full scale step
1.3.5 Digital I/O
 Output port : 16 bits, TTL compatible
 Input port : 16 bits, TTL compatible
1.3.6 Interrupt Channel
 Level : 3,4,5,6,7,9,10,11,12,14,15, jumper selectable
 Enable : Via control register
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 6

1.3.7 Programmable Timer/Counter
 Type : 82C54 -8 programmable timer/counter
 Counters: The counter1 and counter2 are cascaded as a 32 bits pacer timer.
The counter0 is used as user timer/counter. The software driver use counter0
to implement a machine independent timer.
 Clock input frequency : DC to 10 MHz
 Pacer output : 0.00047Hz to 0.5MHz
 Input, gate : TTL compatible
 Internal Clock : 2M Hz
1.3.8 Direct Memory Access Channel (DMA)
 Level : CH1 or CH3, jumper selectable
 Enable : via DMA bit of control register
 Termination : by interrupt on T/C
 Transfer rate : 100K conversions/sec.(DOS Software manual, sec. 4.11)
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 7

1.4 Applications
 Signal analysis
 FFT & frequency analysis
 Transient analysis
 Production test
 Process control
 Vibration analysis
 Energy management
 Industrial and lab. measurement and control
1.5 Product Check List
In addition to this manual, the package includes the following items:
 A-812PG multifunction card
 A-812PG utility diskette
 A-812PG DOS software manual
Attention !
If any of these items is missing or damaged, contact the dealer who
provides you this product. Save the shipping materials and carton in
case you want to ship or store the product in the future.
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 8

2. Hardware Configuration
2.1 Board Layout
A-812PG
ISA BUS
ISA BUS
CN5 CN4
JP5 SW1
CN2
JP4
JP
8
JP7JP6
JP1
JP3
CN3
CN1
BB ADS-774
JP2
JP
9
VR 1 2 3 4 5
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 9

2.2 I/O Base Address Setting
The A-812PG occupies 16 consecutive locations in I/O address space. The
base address is set by DIP switch SW1. The default address is 0x220.
ON
1 2 3 4 5 6
A9 A8 A7 A6 A5 A4`
SW1 : BASE ADDRESS
BASE
ADDR
A9 A8 A7 A6 A5 A4
200-20F OFF ON ON ON ON ON
210-21F OFF ON ON ON ON OFF
220-22F() OFF ON ON ON OFF ON
230-23F OFF ON ON ON OFF OFF
: : : : : : :
300-30F OFF OFF ON ON ON ON
: : : : : : :
3F0-3FF OFF OFF OFF OFF OFF
() : default base address is 0x220
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 10

The PC I/O port mapping is given below.
ADDRESS Device ADDRESS DEVICE
000-1FF PC reserved 320-32F XT Hard Disk
200-20F Game/control 378-37F Parallel Printer
210-21F XT Expansion Unit 380-38F SDLC
238-23F Bus Mouse/Alt. Bus Mouse 3A0-3AF SDLC
278-27F Parallel Printer 3B0-3BF MDA/Parallel Printer
2B0-2DF EGA 3C0-3CF EGA
2E0-2E7 AT GPIB 3D0-3DF CGA
2E8-2EF Serial Port 3E8-3EF Serial Port
2F8-2FF Serial Port 3F0-3F7 Floppy Disk
300-31F Prototype Card 3F8-3FF Serial Port
2.3 Jumper Setting
2.3.1 JP3 : D/A Internal Reference Voltage
Selection
JP3
(5V)
(
10V
)
Reference
Voltage
5V
(default)
JP3
(5V)
(
10V
)
Reference
Voltage
10V
Select ( 5V) : D/A voltage output = 0 to 5V (both channel)
Select ( 10V) : D/A voltage output = 0 to 10V (both channel)
JP3 is validate only if JP1/JP2 select D/A internal reference voltage
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 11

2.3.2 JP1, JP2 : D/A Int/Ext Ref Voltage Selection
If JP1/2 select internal reference, then JP3 select 5V/ 10V internal reference voltage.
If JP1/2 select external reference, then ExtRef1, CN2 pin 17, is the external reference
voltage for DA channel 1. and ExtRef2, CN2 pin 19, is the external reference voltage for
DA Channel 2. If user provides AC +/- 10V external reference voltage, the D/A output
voltage may be AC -/+ 10V
2.3.3 JP8 : A/D Trigger Source Selection
Ch 1 = INT
Ch 2 = INT
(default)
JP1
/
2
(
vref
)
Ch 1 =EXT
(ExtRef1)
Ch 2 =EXT
(ExtRef2)
Ch 1 = INT
Ch 2 =EXT
(ExtRef2)
JP1
/
2
(
vref
)
Ch 1 =EXT
(ExtRef1)
Ch 2 = INT
JP1
/
2
(
vref
)
JP1
/
2
(
vref
)
EXTTRG
INTTRG
Internal
Trigger
(default)
EXTTRG
INTTRG
External
Trigger
The A-812PG supports two trigger type, internal trigger and external
trigger. The external trigger comes from ExtTrg, CN3 pin 1. There are two
types of internal trigger, software trigger and pacer trigger.
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 12

2.3.4 JP4 : A/D Input Range Selection
JP4
( 5V)
(
10V
)
A/D input
range
0 ~ 5V
(default)
JP4
( 5V)
(
10V
)
A/D input
range
0 ~ 10V
Select ( 5V) : A/D voltage input = 0 to 5V (total channel)
Select ( 10V) : A/D voltage input = 0 to 10V (total channel)
2.3.5 JP5 : Interrupt Level Selection
The interrupt channel can not be shared. The A-812PG software driver can support 8
different boards in one system but only 2 of these cards can use interrupt transfer function.
N
O Interrupt
IRQ 3 4 5 6 7 9 10 11 12 14 15 NC
Interrupt 15
(default)
IRQ 3 4 5 6 7 9 10 11 12 14 15 NC
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 13

2.3.6 JP9 : User Timer/Counter Clock Input
Selection
The A-812PG has 3 independent 16 bits timer/counter. The cascaded
counter1 and counter2 are used as pacer timer. The counter0 can be used as a
user programmable timer/counter. The user programmable timer/counter can
select 2M internal clock or external clock ExtCLK, CN3 pin 8. The block
diagram is given in section 2.6. The clock source must be very stable. Itis
recommended to use internal 2M clock.
The A-812PG software driver uses the counter0 as a machine
independent timer. If user program call A-812PG_Delay() subroutine, the
counter0 will be programmed as a machine independent timer. The detail
information is given in section 2.6.
Internal 2M
Clock
(default)
INTCL
K
EXTCLK
External
Clock
INTCL
K
EXTCLK
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 14

2.3.7 JP6 : DMA DACK Selection,
JP7 : DMA DRQ Selection
The DMA channel cannot be shared. The A-812PG software driver can support 8
different boards in one PC based system, but only two of these boards can use DMA
transfer function.
N
O DMA
1
5
2
6
DR
Q
JP7
1
5
2
6
DAC
K
JP8
JP8
JP7
1
5
2
6
DR
Q
1
5
2
6
DAC
K
DMA 1
(default)
1
5
2
6
DR
Q
JP7
1
5
2
6
JP8
DAC
K
DMA 3
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 15

2.4 I/O Register Address
The A-812PG occupies 16 consecutive PC I/O addresses. The following table
lists the registers and their locations.
Address Read Write
Base+0 8254 Counter 0 8254 Counter 0
Base+1 8254 Counter 1 8254 Counter 1
Base+2 8254 Counter 2 8254 Counter 2
Base+3 Reserved 8254 Counter Control
Base+4 A/D Low Byte D/A Channel 0 Low Byte
Base+5 A/D High Byte D/A Channel 0 High Byte
Base+6 DI Low Byte D/A Channel 1 Low Byte
Base+7 DI High Byte D/A Channel 1 High Byte
Base+8 Reserved A/D Clear Interrupt Request
Base+9 Reserved A/D Gain Control
Base+A Reserved A/D Multiplexer Control
Base+B Reserved A/D Mode Control
Base+C Reserved A/D Software Trigger Control
Base+D Reserved DO Low Byte
Base+E Reserved DO High Byte
Base+F Reserved Reserved
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 16

2.4.1 8254 Counter
The 8254 Programmable timer/counter has 4 registers from Base+0 through
Base+3. For detailed programming information about 8254, please refer to
Intel‘s “Microsystem Components Handbook”.
Address Read Write
Base+0 8254 Counter 0 8254 Counter 0
Base+1 8254 Counter 1 8254 Counter 1
Base+2 8254 Counter 2 8254 Counter 2
Base+3 Reserved 8254 Counter Control
2.4.2 A/D Input Buffer Register
(READ) Base+4 : A/D Low Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
(READ) Base+5 : A/D High Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 READY D11 D10 D9 D8
A/D 12 bits data : D11…..D0, D11=MSB, D0=LSB
READY =1 : A/D 12 bits data is not ready
=0 : A/D 12 bits data is ready
The low 8 bits A/D data are stored in address BASE+4 and the high 4 bits data are stored in
address BASE+5. The READY bit is used as an indicator for A/D conversion. When a A/D
conversion is completed, the READY bit will be clear to zero.
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 17

2.4.3 D/A Output Latch Register
(WRITE) Base+4 : Channel 1 D/A Low Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
(WRITE) Base+5 : Channel 1 D/A High Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X X X D11 D10 D9 D8
(WRITE) Base+6 : Channel 2 D/A Low Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
(WRITE) Base+7 : Channel 2 D/A High Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X X X D11 D10 D9 D8
D/A 12 bits output data : D11..D0, D11=MSB, D0=LSB, X=don‘t care
The D/A converter will convert the 12 bits digital data to analog output. The low 8 bits of
D/A channel 1 are stored in address BASE+4 and high 4 bits are stored in address BASE+5.
The address BASE+6 and BASE+7 store the 12 bits data for D/A channel 2. The D/A output
latch registers are designed as a “double buffered” structure, so the analog output latch
registers will be updated until the high 4 bits digital data are written. If the user sends the
high 4 bits data first, the DA 12 bits output latch registers will update at once. So the low 8
bits will be the previous data latched in register. This action will cause an error on DA
output voltage. So the user must send low 8 bits first and then send high 4 bits to
update the 12 bits AD output latch register.
NOTE : Send low 8 bits first, then send high 4 bits.
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 18

2.4.4 D/I Input Buffer Register
(READ) Base+6 : D/I Input Buffer Low Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
(READ) Base+7 : D/I Input Buffer High Byte Data Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
D15 D14 D13 D12 D11 D10 D9 D8
D/I 16 bits input data : D15..D0, D15=MSB, D0=LSB
The A-812PG provides 16 TTL compatible digital inputs. The low 8 bits are stored in
address BASE+6. The high 8 bits are stored in address BASE+7.
2.4.5 Clear Interrupt Request
(WRITE) Base+8 : Clear Interrupt Request Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X X X X X X X
X=don‘t care, XXXXXXXX=any 8 bits data is validate
If A-812PG is working in the interrupt transfer mode, an on-board hardware status bit will be
set after each A/D conversion. This bit must be clear by software before the next hardware
interrupt. Writing any value to address BASE+8 will clear this hardware bit and the
hardware will generate another interrupt when next A/D conversion is completed.
A-812PG Hardware Manual (Ver.1.2, Sep/2005, IPH-004-12) ----- 19