Ingenic XBurst 2 CPU Core Owner's manual

XBurst®2 CPU Core
Programming Manual
Release Date: June 2, 2017

XBurst®2 CPU Core
Programming Manual
Copyright © 2005-2017 Ingenic Semiconductor Co., Ltd. All rights reserved.
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is
granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to the
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Ingenic products are not designed for and should not be used in any medical or life sustaining or
supporting equipment.
All information in this document should be treated as preliminary. Ingenic may make changes to this
document without notice. Anyone relying on this documentation should contact Ingenic for the current
documentation and errata.
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CONTENTS
CONTENTS
1Overview............................................................................................ 5
1.1 Features of XBurst®2 CPU for X2000.................................................................................... 5
2Operating Modes............................................................................... 6
3CP0.................................................................................................... 8
3.1 CP0 Register Summary.......................................................................................................... 8
3.1.1 CP0 Registers Grouped by Function .............................................................................. 8
3.1.2 CP0 Registers Grouped by Number ............................................................................. 10
3.2CP0 register Formats............................................................................................................ 12
3.2.1 CP0 Register Field Types.............................................................................................. 12
3.3 CP0 Register Descriptions.................................................................................................... 13
3.3.1CPU Configuration and Status Registers...................................................................... 13
3.3.2 TLB Management Registers ......................................................................................... 29
3.3.3 Exception Control Registers.......................................................................................... 38
3.3.4 Timer Registers............................................................................................................. 43
3.3.5 Cache Management Registers...................................................................................... 44
3.3.6 Thread Context and Shadow Control Registers ........................................................... 45
3.3.7 CPU Performance Monitor Registers............................................................................ 46
3.3.8 Debug Registers............................................................................................................ 48
3.3.9 User Mode Support Registers....................................................................................... 54
3.3.10 Kernel Mode Scratch Registers .................................................................................... 56
4Exceptions and Interrupts................................................................ 58
4.1 Exception Priority.................................................................................................................. 58
4.2 Exception Vector Locations................................................................................................... 59
4.3 Exception Handling Process................................................................................................. 60
4.3.1 Enter Exception Handler Routine.................................................................................. 60
4.3.2 Return from Exception Handler Routine....................................................................... 60
4.4 Exception Categories............................................................................................................ 61
5Memory Management Unit .............................................................. 63
5.1 Overview............................................................................................................................... 63
5.2 Virtual Memory Space........................................................................................................... 64
5.2.1 User Mode..................................................................................................................... 64
5.2.2 Kernel Mode.................................................................................................................. 65
5.3 TLB........................................................................................................................................ 67
5.3.1 Instruction Micro TLB .................................................................................................... 67
5.3.2 Data Micro TLB ............................................................................................................. 67
5.3.3 Variable Page Size TLB (VTLB).................................................................................... 67
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CONTENTS
5.3.4 Fixed Page Size TLB (FTLB).........................................................................................70
5.3.5 Filling JTLB Entry...........................................................................................................71
5.4 Virtual to Physical Address Translation.................................................................................72
6Caches.............................................................................................73
6.1 L1-cache................................................................................................................................73
6.1.1 Cache Coherency Attribute............................................................................................73
6.1.2 Cache Relative CP0 Registers......................................................................................74
6.1.3 Cache Operation Relative Instructions..........................................................................74
6.1.4 PREF/PREFX instruction...............................................................................................77
6.1.5 SYNC instruction ...........................................................................................................78
6.2 L2-cache................................................................................................................................79
7Initialize Core State..........................................................................80
7.1 Initialized Core State by Hardware........................................................................................80
7.1.1 Coprocessor 0 State......................................................................................................80
7.1.2 TLB Initialization.............................................................................................................80
7.1.3 Cache Initialization.........................................................................................................80
7.2 Initialized Core State by Software.........................................................................................80
7.2.1 General Purpose Registers Initialization .......................................................................80
8CCU..................................................................................................81
8.1 Overview................................................................................................................................81
8.2 Register Description..............................................................................................................82
8.2.1 Cores SLeep Control Register.......................................................................................83
8.2.2 Core Sleep Status Register...........................................................................................84
8.2.3 Core Software Reset Register.......................................................................................85
8.2.4 Memory Subsystem Control Register............................................................................86
8.2.5 Memory Subsystem Implementation Register...............................................................87
8.2.6 CPU Configuration Register ..........................................................................................88
8.2.7 Peripheral IRQ Pending Register ..................................................................................89
8.2.8 Peripheral IRQ Mask Register.......................................................................................89
8.2.9 Mailbox IRQ Pending Register ......................................................................................90
8.2.10 Mailbox IRQ Mask Register...........................................................................................90
8.2.11 OST IRQ Pending Register ...........................................................................................91
8.2.12 OST IRQ Mask Register................................................................................................91
8.2.13 Debug Interrupt Pending Register.................................................................................92
8.2.14 Debug Interrupt Mask Register......................................................................................92
8.2.15 Reset Entry Register......................................................................................................93
8.2.16 Mailbox Register<N>.....................................................................................................93
8.2.17 CCU Spin Lock Register................................................................................................94
8.2.18 CCU Spin Atomic Register.............................................................................................94
8.2.19 Global Interrupt Mask Register......................................................................................95
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CONTENTS
8.2.20 CPU Feature Configuration Register ............................................................................ 96
8.2.21 Bus Exception Control Register.................................................................................... 97
8.3 Usage.................................................................................................................................... 98
8.3.1 The Configuration of CCU............................................................................................. 98
9EJTAG Debug Support.................................................................... 99
9.1 Overview............................................................................................................................... 99
9.2 Detecting Debug Mode....................................................................................................... 100
9.3 Ways of Entering Debug Mode........................................................................................... 100
9.4 Exiting Debug Mode............................................................................................................ 100
9.5 Hardware Breakpoints ........................................................................................................ 100
9.5.1 Instruction Breakpoints................................................................................................ 101
9.5.2 Data Breakpoints......................................................................................................... 101
9.5.3 Overview of Instruction Breakpoint Registers............................................................. 101
9.5.4 Overview of Data Breakpoint Registers...................................................................... 101
9.6 Conditions for Matching Breakpoints.................................................................................. 102
9.6.1 Conditions for Matching Instruction Breakpoints......................................................... 102
9.6.2 Conditions for Matching Data Breakpoints.................................................................. 102
9.6.3 SIMD Load/Store Handling.......................................................................................... 103
9.7 Debug Exceptions from Breakpoints .................................................................................. 103
9.7.1 Debug Exception by Instruction Breakpoint................................................................ 104
9.7.2 Debug Exception by Data Breakpoint......................................................................... 104
9.7.3 Breakpoint Used as Triggerpoint................................................................................. 104
9.8 Test Access Port (TAP) ....................................................................................................... 104
9.8.1 EJTAG Internal and External Interfaces...................................................................... 105
9.8.2 Test Access Port Operation......................................................................................... 105
9.8.3 Test Access Port (TAP) Instructions............................................................................ 109
9.8.4 TAP Processor Accesses .............................................................................................111
9.9 EJTAG Registers .................................................................................................................113
9.9.1 General Purpose Control and Status...........................................................................113
9.9.2 Instruction Breakpoint Registers..................................................................................114
9.9.3 Data Breakpoint Registers ...........................................................................................117
9.9.4 EJTAG TAP Registers................................................................................................. 122
9.10 Debug Exception................................................................................................................. 130
9.10.1 Debug Exception Priorities.......................................................................................... 130
9.10.2 Debug Exception Vector Location............................................................................... 131
9.10.3 General Debug Exception Processing........................................................................ 131
9.10.4 Debug Single Step Exception ..................................................................................... 132
9.10.5 Debug Interrupt Exception........................................................................................... 133
9.10.6 Debug Instruction Break Exception............................................................................. 133
9.10.7 Debug Breakpoint Exception....................................................................................... 133
9.10.8 Debug Data Break on Load/Store Exception.............................................................. 134
9.11 Debug Mode Exceptions..................................................................................................... 134
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CONTENTS
9.11.1 Exceptions Taken in Debug Mode...............................................................................134
9.11.2 Debug Mode Exception Processing ............................................................................135
9.12 MIPS EJTAG Compliant Mode............................................................................................136
9.13 Accelerated EJTAG Mode...................................................................................................136
9.13.1 ACC Mode Flag ...........................................................................................................136
9.13.2 EJTAG Control Register in ACC mode (ECR_A).........................................................136
9.13.3 Processor Access Address Register in ACC mode (ADDRESS_A)............................138
9.13.4 Processor Access Data Register in ACC mode (DATA_A)..........................................138
9.13.5 Debug ModeAddress Space in Compliant Mode (AM = 0).........................................139
9.13.6 Debug ModeAddress Space in ACC Mode (AM = 1)..................................................139
9.13.7 Supported JTAG Instructions in ACC Mode ................................................................140
Revision History...................................................................................141
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Operating Modes
1 Overview
XBurst®2 CPU is a high performance and low power implementation of MIPS32 ISAr5 + Configurable
SIMD ISA (MIPS MSA128 + XBurst® MXA128 for X2000) instruction set architecture.
1.1 Features of XBurst®2 CPU for X2000
32-bit MIPS32 ISA R5 plus MIPS SIMD instruction set architecture:MSA128
Ingenic SIMD instruction set architecture: MXA128
dual-issue, superscalar, super pipeline with Simultaneous Multi-Threading (SMT)
Two hardware threads per physical core
Quad instructions fetch per cycle
Dual-issue instructions per hardware thread per cycle
Smart branch prediction scheme with Instruction trace buffer (ITB), Branch Target Buffer
(BTB), Pattern History Table (PHT), Return Address Stack (RAS) and Jump Target Buffer
(RTB)
L1 cache size up to 32KB for Instruction cache and Data cache, respectively, 8-way set
associative
high-performance dual-issue floating-point (single and double) and 128-bit SIMD Unit
32 x 128-bit registers, 128-bit loads/stores to/from SIMD unit
data types: 8/16/32 bits integer, Q15/Q31 fixed point and 32/64 bits floating point
IEEE-754 2008 compliance
Programmable Memory Management Unit (MMU)
1st level mini-TLB (MTLB): 8-entry instruction MTLB, 16-entry data MTLB
2nd level joint TLBs: 32-entry VTLB, 256-entry 4-way set associative FTLB
Integrated Cache Crossbar (CCX) and L2 cache
Configurable size up to 1MB
Support multi-core configurations up to 4 physical cores (4 cores with total 8 threads)
Hardware prefetcher for streaming performance
Advanced power management
Hardware automatic clock gating for idle subsystems
XBurst2 CPU implements SMT technology - a physical core contains 2 simultaneous threads. For
convenience of description, a thread can be regarded as a logic core. Therefore, except explicitly
claim, a core means a logic core in later chapters.
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Overview
2 Operating Modes
XBurst®2 CPU core supports three operating modes:
Debug Mode
Kernel Mode
User Mode
Table 2-1 the conditions of operating mode
Debug.DM Status.UM Status.EXL Status.ERL Operating Mode
1 X X X Debug Mode
0 0 X X Kernel Mode
0 X 1 X
0 X X 1
0 1 0 0 User Mode
X denotes don't care.
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CP0
3 CP0
The XBurst2 System Control Coprocessor (CP0) provides the register interface to the XBurst2 core
and supports memory management, address translation, exception handling, and other privileged
operations. Each CP0 register has a unique number that identifies it, referred to as its register number.
A separate select number is used to differentiate additional registers within the register number. For
example, as shown in the table below, there are eight configuration registers with register number 16.
If the select number is omitted, it is zero.
This chapter contains the following sections:
• Section 3.1 “CP0 Register Summary”
• Section 3.2 “CP0 Register Formats”
• Section 3.3 “CP0 Register Descriptions”
3.1 CP0 Register Summary
The following two subsections show the CP0 register set, Table 3-1 CP0 Register Grouped by
Function and Table 3-2 CP0 Registers Grouped by Number.
3.1.1 CP0 Registers Grouped by Function
The CP0 registers set are divided into several register groups listed below.
Table 3-1 CP0 Register Grouped by Function
Category Register
Name Register Number Register Select
CPU Configuration
and Status Config 16 0 section 3.3.1.1
Config1 16 1 section 3.3.1.2
Config2 16 2 section 3.3.1.3
Config3 16 3 section 3.3.1.4
Config4 16 4 section 3.3.1.5
Config5 16 5 section 3.3.1.6
PRId 15 0 section 3.3.1.7
EBase 15 1 section 3.3.1.8
Status 12 0 section 3.3.1.9
IntCtl 12 1 section 3.3.1.10
TLB Management Index 0 0 section 3.3.2.1
Random 1 0 section 3.3.2.2
EntryLo0 2 0 section 3.3.2.3
EntryLo1 3 0 section 3.3.2.3
EntryHi 10 0 section 3.3.2.4
Context 4 0 section 3.3.2.5
PageMask 5 0 section 3.3.2.6
PageGrain 5 1 section 3.3.2.7
Wired 6 0 section 3.3.2.8
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CP0
BadVAddr 8 0 section 3.3.2.9
Exception Control Cause 13 0 section 3.3.3.1
EPC 14 0 section 3.3.3.2
ErrorEPC 30 0 section 3.3.3.3
Timer Registers Count 9 0 section 3.3.4.1
Compare 11 0 section 3.3.4.2
Cache Management TagLo 28 0 section 3.3.5.1
DataLo 28 1 section 3.3.5.2
Shadow Registers SRStl 12 2 section 3.3.6.1
SRSMap 12 3 section 3.3.6.2
Performance Monitoring PerfCntCtl0 25 0 section 3.3.7.1
PerfCntCnt0 25 1 section 3.3.7.2
PerfCntCtl1 25 2 section 3.3.7.1
PerfCntCnt1 25 3 section 3.3.7.2
Debug Debug 23 0 section 3.3.8.1
Debug2 23 6 section 3.3.8.2
DEPC 24 0 section 3.3.8.3
DESAVE 31 0 section 3.3.8.4
WatchLo 18 0 section 3.3.8.5
WatchHi 19 0 section 3.3.8.6
User Mode Support HWREna 7 0 section 3.3.9.1
UserLocal 4 2 section 3.3.9.2
LLAddr 17 0 section 3.3.9.3
Kernel Mode Support KScratch1 31 2 section 3.3.10.1
KScratch2 31 3 section 3.3.10.2
KScratch3 31 4 section 3.3.10.3
KScratch4 31 5 section 3.3.10.4
KScratch5 31 6 section 3.3.10.5
KScratch6 31 7 section 3.3.10.6
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CP0
3.1.2 CP0 Registers Grouped by Number
The following table provides a numerical list of the processor CP0 register.
Table 3-2 CP0 Registers Grouped by Number
Register
Function Location
Num
Sel
Name
0 0 Index Index into the TLB array section 3.3.2.1
1 0 Random Randomly generated index into the TLB array section 3.3.2.2
2 0 EntryLo0 Low-order portion of the TLB entry for even-
numbered virtual pages. section 3.3.2.3
3 0 EntryLo1 Low-
order portion of the TLB entry for
odd-numbered virtual pages. section 3.3.2.3
4 0 Context Pointer to page table entry in memory. section 3.3.2.5
4 2 UserLocal It is written and interpreted by software section 3.3.9.2
5 0 PageMask PageMask controls the variable page sizes in
TLB entries. section 3.3.2.6
5 1 PageGrain PageGrain controls the granularity of the page
sizes in TLB entries. section 3.3.2.7
6 0 Wired Controls the number of fixed ("wired") TLB
entries. section 3.3.2.8
7 0 HWREna Enable access to selected hardware registers in
non-privileged mode via the RDHWR instruction. section 3.3.9.1
8 0 BadVaddr The virtual address triggering the most recent
address-related exception. section 3.3.2.9
9 0 Count Interval counter. section 3.3.4.1
9 6 SpinLock Spinlock register.
10 0 EntryHi High-order portion of the TLB entry. section 3.3.2.4
11 0 Compare Compare value for interval count. section 3.3.4.2
12 0 Status Processor status and control. section 3.3.1.9
12 1 IntCtl Setup for interrupt vector and interrupt priority
features. section 3.3.1.10
12 2 SRSCtl Shadow register set control section 3.3.6.1
12 3 SRSMap Shadow register map section 3.3.6.2
13 0 Cause Cause of last exception section 3.3.3.1
14 0 EPC Program counter of resuming after servicing the
most recent normal exception. section 3.3.3.2
15 0 RPID Processor identification and revision section 3.3.1.7
15 1 EBase Exception handler’s base address. section 3.3.1.8
16 0 Config Configuration register. section 3.3.1.1
16 1 Config1 Configuration for MMU, catches etc. section 3.3.1.2
16 2 Config2 Configuration for MMU ,caches etc. section 3.3.1.3
16 3 Config3 Interrupt and ASE capabilities. section 3.3.1.4
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CP0
16 4 Config4 Indicates presence of Config5 register section 3.3.1.5
16 5 Config5 Provides information on EVA and cache error
exception vector section 3.3.1.6
17 0 LLAddr The physical address of the load operation for the
most recent Load Linked (LL) instruction. section 3.3.9.3
18 0 WatchLo Watchpoint address. (low order) section 3.3.8.5
19 0 WatchHi Watchpoint address (high order) and mask. section 3.3.8.6
23 0 Debug EJTAG Debug register. section 3.3.8.1
23 6 Debug2 EJTAG Debug 2 register. section 3.3.8.2
24 0 DEPC Program counter of resuming after servicing the
most recent debug/debug-mode exception. section 3.3.8.3
25 0 PerfCntCtl0 Performance counter 0 control section 3.3.7.1
25 1 PerfCntCnt0 Performance counter 0 count section 3.3.7.2
25 2 PerfCntCtl1 Performance counter 1 control section 3.3.7.1
25 3 PerfCntCnt1 Performance counter 1 count section 3.3.7.2
28 0 TagLo Cache tag read/write interface for I-Cache and
D-Cache. section 3.3.5.1
28 1 DataLo Low-order data read/write interface for I-Cache
and D-Cache section 3.3.5.2
30 0 ErrorEPC Program counter of resuming after servicing the
most recent Error exception (like reset). section 3.3.3.3
31 0 DESAVE Debug handler scratchpad register. section 3.3.8.4
31 2 KScratch1 Kernel scratch pad register 1. section 3.3.10.1
31 3 KScratch2 Kernel scratch pad register 2. section 3.3.10.2
31 4 KScratch3 Kernel scratch pad register 3. section 3.3.10.3
31 5 KScratch4 Kernel scratch pad register 4. section 3.3.10.4
31 6 KScratch5 Kernel scratch pad register 5. section 3.3.10.5
31 7 KScrathc6 Kernel scratch pad register 5. section 3.3.10.6
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CP0
3.2 CP0 register Formats
This section contains descriptions of each CP0 register. The registers are listed in numerical order,
first by register number, then by select field number.
3.2.1 CP0 Register Field Types
For each register described below, field descriptions include the read/write properties of the field, and
the reset state of the field. The read/write properties are described in Table 3-3.
Table 3-3 CP0 Register Field R/W Access Types
Notation Hardware Interpretation Software Interpretation
R/W A field in which all bits are readable and writeable by software and potentially by hardware.
Hardware updates of this field are visible by software reads. Software updates of this field
are visible by hardware reads.
If the reset state of this field is “Undefined”, either software or hardware must initialize the
value before the first read will return a predictable value. This should not be confused with
the formal definition of UNDEFINED behavior.
R
A field that is either static or is
updated only by hardware.
If the reset state of this field is either
"0" or
"1", hardware initializes this
field.
A field to which the value written by software is
ignored. Software may write any value to this field
without affecting hardware behavior. Software
reading the field will return the last value updated
by hardware.
If the reset st
ate of this field is “Undefined,”
software reading of this field results
in an
UNPREDICTABLE value except after a hardware
update done under the conditions specified in the
description of the field.
W A field that can be written by software but cannot be read by software.
Software reading of this field will return an UNDEFINED value.
W0 Hardware can write "0" or "1" to this
field Software writes always causes the field
to be
cleared to zero.
W1C Hardware can write "0" or "1" to this
field. Software should write "1" to this field to clear it.
Reserved
A field that hardware does not
update, and assumes a zero value. A field to which the write operation by software is
always ingored. And software reading of this field
will return zero.
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CP0
3.3 CP0 Register Descriptions
The following subsections describe the CP0 registers listed in above.
3.3.1 CPU Configuration and Status Registers
This section contains the following CPU Configuration and Status registers.
Device Configuration - Config(CP0 Register16, Select 0)
Device Configuration 1-Config 1(CP0 Register16, Select1)
Device Configuration 2-Config 2(CP0 Register16, Select2)
Device Configuration 3-Config 3(CP0 Register16, Select3)
Device Configuration 4-Config 4(CP0 Register16, Select4)
Device Configuration 5-Config 5(CP0 Register16, Select5)
Processor ID-PRId(CP0 Register 15, Select 0)
Exception Base Address-EBase(CP0 Register 15, Select 1)
Status (CP0 Register 12, Select 0)
Interrupt Control - IntCtl (CP0 Register 12, Select 1)
3.3.1.1 Device Configuration - Config(CP0 Register16, Select 0)
The Config register specifies various configuration and capabilities information. Most of the fields in
the Config register are initialized by hardware reset, or are constant value.
Config Register
31 30 28 27 25 24 16 15 14 13 12 10 9 7 6 4 3 2 0
M K23 KU 0 BE AT AR MT 0VI K0
Name Bits Description R/W Reset
M 31 This bit is hardwired to "1" to indicate the presence of the
Config1 register. R 1
K23 30:28 These fields are unused because XBurst CPU does not
support fixed mapping MMU. R 0
KU 27:25 R 0
0 24:16 returns zero on read and must be written as zero R 0
BE 15 Indicates the endian mode. XBurst CPU supports little
endian only.
0: littel endian;
1: big endian;
R 0
AT 14:13 Architecture type implemented by the processor.
Hardwired to 2’b00 which indicates that the architecture type
is MIPS32.
This field only denotes address and register width. The
exact implemented instruction sets are denoted by the ISA
R 0
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CP0
register field of Config3.
AR 12:10 Architecture revision level.
This bit always reads 1 to reflect Release 5 of MIPS32
architecture.
R 1
MT 9:7 MMU type. This field is hardwired to 3’b100 to indicate a
VTLB+FTLB MMU. R 4
0 6:4 Must be written as zero; returns zero on read R 0
VI 3 Virtual instruction cache. This field is hardwired to 1'b0 to
indicate the instruction cache of XBurst2 CPU is not virtual. R 0
K0 2:0 Kseg0 cache attributes.
SeeTable 6-2 Cache Coherency Attributes for detail R/W 2
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CP0
3.3.1.2 Device Configuration 1-Config 1(CP0 Register16, Select1)
The Config1 register is an adjunct to the Config register and encodes additional capabilities
information. All fields in the Config1 register are read-only.
The Icache and Dcache configuration parameters include encoding for the number of sets per way,
the line size, and the associativity. The total cache size for a cache is therefore:
Cache Size = Associativity * Line Size * Set Per Way
Config1 Register
31 30 25 24 22 21 19 18 16 15 13 12 10 9 7 6 5 4 3 2 1 0
M MMU size IS IL IA DS DL DA C2 MD PC
WR
CA EP FP
Name Bits Description R/W Reset
M 31 This bit is hardwired to ‘1’ to indicate the presence of the
Config2 register . R 1
MMU size 30:25 The size of the VTLB array (the array has MMUSize + 1 entries). Refer to the Config4 register for more information.
0x1F indicates 32 VTLB entries for this implementation. R 0x1F
IS 24:22
L1 instruction cache number of sets per way. This field is
encoded as follows:
0 : Reserved
1 : 128 sets per way
2~7 : Reseveed.
R 1
IL 21:19
L1 instruction cache line size. This field is encoded as
follows:
0~3 : Reserved
4 : 32-byte line size
5~7 : Reserved.
R 4
IA 18:16
L1 Instruction cache associativity. This field is encodes as
follows:
0~6 : Reserved
7 : 8-way
R 7
DS 15:13
L1 Data cache number of sets per way. This field is encodes
as follow:
0 : Reserved
1 : 128 set per way
2~7 : Reseveed.
R 1
DL 12:10
L1 data cache line size. This field is encoded as follows:
0~3 : Reserved
4 : 32-byte line size
5~7 : Reserved.
R 4
DA 9:7 L1 data cache associativity.This field is encoded as follows: 0~6 : Reserved
7 : 8-way R 7
C2 6 Coprocessor 2 implemented: R 1
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CP0
0: Coprocessor 2 not implemented.
1: Coprocessor 2 implemented.
MD 5 MDMX Application Specific Extension (ASE).
0x0: indicates that the MDMXASE is not implemented R 0
PC 4
Performance Counter implemented.
Performance counter always is implemented. Hence this bit
is always logic '1'. Refer to the PerfCtl0-1 and PerfCnt0-1
registers for more information.
R 1
WR 3 Watch registers implemented.
Refer to WathcLo/WatchHi registers for more information. R 1
CA 2 MIPS16e present. This bit always reads as 0 to indicate no
support of MIPS16e ISA R 0
EP 1 EJTAG implemented. This bit always reads as 1 to indicate
the EJTAG unit is implemented. R 1
FP 0
FPU implemented.
If an FPU is implemented, further
capabilities of the FPU
can be read from the capability bits in the FIR register
belonging to CP1 registers.
R 1
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CP0
3.3.1.3 Device Configuration 2-Config 2(CP0 Register16, Select2)
The Config2 register encodes level 2 cache configurations.(level 3 cache is not implemented).
Config2 Register
31 30 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
M TU TS TL TA SU SS SL SA
Name Bits Description R/W Reset
M 31 This bit is hardwired to '1' to indicate the presence of the
Config3 register. R 1
TU 30:28 L3 cache is not implemented for XBurst2 CPU, hence the bit
fields of TU, TS,TL,TA are not used and are all tied to 0. R 0
TS 27:24 R 0
TL 23:20 R 0
TA 19:16 R 0
SU 15:13 Version of L2.
0 : V0.0
1 : V1.0
2 : V2.0
3-8 : reserved
R
2
SS 11:8 L2 cache sets per way.This field is encoded as follows:
0, 1, 6, 7 : Reserved
2 : 256 set per way
3 : 512 set per way
4 : 1024 set per way
5 : 2048 set per way
R 4
SL 7:4 L2 cache line size. This field is encoded as follows:
0~4, 6, 7 : Reserved
5 : 64-byte line size
R 5
SA 3:0 L2 cache associativity.This field is encoded as follows:
0~6 : Reserved
7 : 8-way
8~14 : Reserved
15 : 16-way
R 15
XBurst®2 CPU Core Programming Manual
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CP0
3.3.1.4 Device Configuration 3-Config 3(CP0 Register16, Select3)
Config 3 provides information about the presence of optional extensions to the base MIPS32
architecture in addition to those specified in Config 2.All fields in the Config3 register are read-only.
Config3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
0
CMGCR
MSAP
BP
BI
SC
PW
VZ
IPLW
MMAR
MCU
ISAOnExc
ISA
ULRI
RXI
DSP2P
DSPP
CTXTC
ITL
LPA
VEIC
VInt
SP
CDMM
MT
SM
TL
Name Bits Description R/W Reset
M 31 Denotes the presence of Config4 register. R 1
0 30 Must be written as zero; returns zero on read R 0
CMGCR 29 Coherency Manager memory-mapped Global Configuration
Register Space. 0 denotes it is not implemented. R 0
MSAP 28 MSA Present.
0: MSA is not implemented;
1: MSA is implemented;
R 1
BP 27 BadInstrP register implemented.
Always read as zero, indicating that it is not implemented. R 0
BI 26 BadInstr register implemented.
Always read as zero, indicating that it is not implemented. R 0
SC 25 Segment Control implemented.
The bit indicates whether SegCtl0~SegCtl1 are present. R 0
PW 24 Hardware Page Table Walk implemented.
Read as zero , indicating that it is not implemented. R 0
VZ 23 Virtualization implemented;
Read as zero, indicating that it is not implemented. R 0
IPLW 22:21 Config3MCU is zero, indicating that MCU ASE is not
implemented so this field is not used. R 0
MMAR 20:18 Config3ISA is zero, indicating that microMIPS32 is not
implemented so this field is not used. R 0
MCU 17 MCU ASE implemented.
Always read as zero, indicating that it is not implemented. R 0
ISAOn-
Exc 16 Reflects the ISAto be used after vectoring to an exception. 0: MIPS32 is used on entrance to an exception vector;
1: microMIPS is used on entrance to an exception vector;
Always read as zero as microMIPS is never implemented.
R 0
ISA 15:14 Indicates Instruction Set Availability.
Always read as zero, indicating that MIPS32 is implemented R 0
ULRI 13 UserLocal register implemented.
0: UserLocal register is not implemented; R 1
XBurst®2 CPU Core Programming Manual
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18