Ingenic JZ4775 Guide

Ingenic®JZ4775
Board Design Guide
Revision: 1.1
Date: Sept. 2013

Ingenic JZ4775
Board Design Guide
Copyright © Ingenic Semiconductor Co. Ltd 2013. All rights reserved.
Release history
Date
Revision
Change
Mar 2013
1.0
First release
Sep.2013
1.1
Change the company address and etc
Disclaimer
This documentation is provided for use with Ingenic products. No license to Ingenic property rights is
granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to
the usage, or intellectual property right infringement except as provided for by Ingenic Terms and
Conditions of Sale.
Ingenic products are not designed for and should not be used in any medical or life sustaining or
supporting equipment.
All information in this document should be treated as preliminary. Ingenic may make changes to this
document without notice. Anyone relying on this documentation should contact Ingenic for the
current documentation and errata.
Ingenic Semiconductor Co., Ltd.
Junzheng Bld, Zhongguancun Software Park 2 Dongbeiwang West Road, Haidian
District Beijing,China,100193
Tel: [phone]
Fax: [phone]
Http: //www.ingenic.cn

Content
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
i
Content
1Overview............................................................................................. 1
1.1 Introduction.........................................................................................................................1
1.2 Reference Platform.............................................................................................................2
2Platform Stack-Up and Placement...................................................... 3
2.1 General Design Considerations...........................................................................................3
2.2 Nominal 6-Layer Board Stack-Up........................................................................................3
2.3 PCB Technology Considerations.........................................................................................4
2.4 4-Layer Board Stack-Up......................................................................................................5
2.5 8-Layer HDI Board Stack-Up...............................................................................................6
3Static Memory Interface Design Guidelines ....................................... 7
3.1 Overview ............................................................................................................................7
3.2 Boot Memory......................................................................................................................7
3.3NAND Flash Connection.....................................................................................................8
4DDR3 SDRAM.................................................................................... 9
4.1 Overview ............................................................................................................................9
4.2 Connection to two 2Gb x 16 DDR3 SDRAM device.............................................................9
4.3 Connection to four 1Gb x 8 DDR3 SDRAM device.............................................................10
4.4 Layout Guideline...............................................................................................................10
5Audio Codec Design Guidelines....................................................... 14
5.1 Overview ..........................................................................................................................14
5.2 Audio Power .....................................................................................................................14
5.3 Headphone Out ................................................................................................................14
5.4 Mic In................................................................................................................................15
5.5 Speaker............................................................................................................................16
5.6 Receiver...........................................................................................................................16
5.7 Line In...............................................................................................................................16
5.8 Layout Guideline...............................................................................................................17
6USB and OTG Design Guidelines .................................................... 19
6.1 USB Overview ..................................................................................................................19
6.1.1 USB Power................................................................................................................19
6.2 OTG Overview..................................................................................................................19
6.2.1 OTG Power ...............................................................................................................19
6.3 Guidelines for the USB and OTG interface........................................................................20
7LCD................................................................................................... 23

Content
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
ii
8EPD ...................................................................................................26
8.1 Overview..........................................................................................................................26
9Camera..............................................................................................27
9.1 Overview..........................................................................................................................27
10 SAR A/D Controller............................................................................28
10.1 Overview..........................................................................................................................28
10.2 Touch Screen...................................................................................................................28
10.3 Battery Voltage Measurement...........................................................................................29
11 OTP EFUSE ......................................................................................30
11.1 Overview..........................................................................................................................30
12 Ethernet Design Guidelines...............................................................31
12.1 Overview..........................................................................................................................31
12.2 JZ4775 Ethernet Controller Connection............................................................................ 31
13 RTC ...................................................................................................32
13.1 Overview..........................................................................................................................32
13.2 RTC Clock........................................................................................................................ 32
13.3 Power Control ..................................................................................................................32
14 Miscellaneous Peripheral Design Guidelines....................................34
14.1 SSI Design Guideline .......................................................................................................34
14.2 UART...............................................................................................................................35
14.2.1 UART Implementation...............................................................................................35
14.3 SMB BUS.........................................................................................................................36
14.4 PWM................................................................................................................................36
14.5 GPIO................................................................................................................................36
14.6 JTAG/Debug Port ............................................................................................................. 36
15 Platform Clock Guidelines.................................................................38
16 Platform Power Guidelines................................................................39
16.1 Overview..........................................................................................................................39
16.2 Power Delivery and Decoupling........................................................................................39

Overview
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
1
1 Overview
JZ4775 is a mobile application processor targeting for multimedia rich and mobile devices like tablet
computer, EBook, mobile digital TV. This SOC introduces a kind of innovative architecture to fulfill
both high performance mobile computing and high quality video decoding requirements addressed
by mobile multimedia devices. JZ4775 provides high-speed CPU computing power and fluent 720p
video replay.
The CPU (Central Processing Unit) core, equipped with 16kB instruction and 16kB data level 1
cache, and 256kB level 2 cache, operating at 1GHz, and full feature MMU function performs OS
related tasks.
At the heart of the CPU core is XBurst® processor engine. XBurst® is an industry leading
microprocessor core which delivers superior high performance and best-in-class low power
consumption. A hardware floating-point unit which compatible with IEEE754 is also included.
The VPU (Video Processing Unit) core is powered with another XBurst® processor engine. The
SIMD instruction set implemented by XBurst® engine, in together with the on chip video
accelerating engine and post processing unit, delivers high video performance. The maximum
resolution of 720p in the formats of H.264, VC-1, MPEG-1/2, MPEG-4, RealVideo and VP8 are
supported in decoding.
The memory interface supports a variety of memory types that allow flexible design requirements,
including glueless connection to SLC NAND flash memory or up to 64-bit ECC MLC/TLC NAND
flash memory and toggle NAND flash for cost sensitive applications. It provides the interface to
DDR2, DDR3 and LPDDR memory chips with lower power consumption.
On-chip modules such as audio CODEC, multi-channel SAR-ADC, AC97/I2S controller and camera
interface offer designers a rich suite of peripherals for multimedia application. The LCD controller
support regular RGB, 1024x768 output, WLAN, Bluetooth and expansion options are supported
through high-speed SPI and MMC/SD/SDIO host controllers. Other peripherals such as USB OTG
and USB 1.1 host, UART and SPI as well as general system resources provide enough computing
and connectivity capability for many applications.
1.1 Introduction
This design guide provides recommendations for system designs based on the JZ4775 processor.
Design issues (e.g., thermal considerations) should be addressed using specific design guides or
application notes for the processor.
The design guidelines in this document are used to ensure maximum flexibility for board designers
while reducing the risk of board related issues. The design information provided in this document
falls into two categories:
• Design Recommendations: It is based on INGENIC‟s simulations and lab experience to date
are strongly recommended, if not necessary, to meet the timing and signal quality
specifications.
• Design Considerations: Suggestions for platform design provide one way to meet the design
recommendations. Design considerations are based on the reference platforms designed by

Overview
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
2
INGENIC. They should be used as an example, but may not be applicable to particular
designs.
Note: In this manual, processor means the JZ4775 processor if not specified.
The guidelines recommended in this manual are based on experience and simulation work
completed by INGENIC while developing systems with JZ4775. This work is ongoing, and the
recommendations and considerations are subject to change.
Platform schematics can be obtained and are intended as a reference for board designers.
While the schematics may cover a specific design, the core schematics remain the same for
most platforms. The schematic set provides a reference schematic for each platform
component, and common system board options. Additional flexibility is possible through other
permutations of these options and components.
The document can help customer span doorstep, design product using existent software and
hardware resources. Your advice is the best encourage for us.
1.2 Reference Platform
Figure 1-1 shows the JZ4775 Development Board Architecture.
LCD I2C1 LCD/EPD
BOARD
HEADER
EPD
TOUCH SCREEN
32.768K I2C1
LINE OUT
HP OUT
Reset
MIC811
DRAMS(DDR3)
MSC1(Boot)
26M
USB
HOST
3223
CRY
CAMERA
HEADER
RTC
USB
OTG
CRY
MIC1/MIC2
AUDIO
JACK
PMU
CIM1
Reset
RS232 DB9,UART2
Line IN
AUDIO
Jack
AMPRECEIVER
UART2
JZ4775
PCM
DRAMBUS
UART2
SD&TF SOCKET
Line IN(differ)
USB2.0 USB1.1
NAND\MCP\INAND\Toggle NAND
I2C2
STATIC MEMBUS
JTAG
HEADER
WIFI
BT
FM
I2C1
UART0
MSC1
10M/100M/1000M
ETHERNET
Figure 1-1 JZ4775 Development Board Architecture

Platform Stack-Up and Placement
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
3
2 Platform Stack-Up and Placement
In this section, an example of a JZ4775 platform component placement and stack-up is presented
for a PMP product.
2.1 General Design Considerations
This section describes motherboard layout and routing guidelines for JZ4775 platforms. This section
does not describe the function of any bus, or the layout guidelines for an add-in device. If the
guidelines listed in this manual are not followed, it is very important that thorough signal integrity and
timing simulations are completed for each design. Even when the guidelines are followed, critical
signals are recommended to be simulated to ensure proper signal integrity and flight time. Any
deviation from the guidelines should be simulated.
The trace impedance typically noted (i.e., 50Ω ± 10%) is the nominal trace impedance for a 4-mil
wide trace. That is, the impedance of the trace when not subjected to the fields created by changing
current in neighboring traces. When calculating flight times, it is important to consider the minimum
and maximum impedance of a trace based on the switching of neighboring traces. Using wider
spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces
reduce settling time. Coupling between two traces is a function of the coupled length, the distance
separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance.
To minimize the effects of trace-to-trace coupling, the routing guidelines documented in this section
should be followed. Additionally, these routing guidelines are created using a PCB stack-up similar
to that illustrated in Figure 2-1.
2.2 Nominal 6-Layer Board Stack-Up
The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%.
Recommendations in this design guide are based on the following a 6-layer board stack-up:
Core Layer 8
Ground Layer 9
Prepreg Layer 10
Signal Layer 11
Figure 2-1 6-layer PCB Stack-Up
Prepreg Layer 6
Ground Layer 3
Signal Layer 1
Prepreg Layer 2
Core Layer 4
Power Layer 7
-----------------------------------------------------
Total Thickness 62 mils.
Signal Layer 5

Platform Stack-Up and Placement
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
4
Table 2-1 PCB Parameter
Description
Nominal Value
Tolerance
Comments
Board Impedance Z0
50Ω
±10%
With nominal 4 mil trace width
Dielectric Thickness
4.3 mils
±0.5 mils
1 x 2116 Pre-Preg
Micro-stripline Er
4.1
±0.4
@ 100 MHz
Trace Width
4.0 mils
±0.5 mils
Standard trace
Trace Thickness
2.1 mils
±0.5 mils
0.5 oz foil + 1.0 oz plate
Solder mask Er
4.0
±0.5
@ 100 MHz
Solder mask Thickness
1.0 mils
±0.5 mils
From top of trace
2.3 PCB Technology Considerations
The following recommendation aids in the design of a JZ4775 based platform. Simulations and
reference platform are based on the following technology, and we recommend that designers
adhere to these guidelines.
Figure 2-2 PCB Technologies –Stack-Up
L1 Signal
L6 Signal
L2 Ground
Copper
L4 Power
Copper
L3 Signal
L5 Ground
Copper

Platform Stack-Up and Placement
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
5
Table 2-2 PCB Parameter for Vias
Number of Layers
Stack Up
6 Layer
Cu Thickness1
0.5 oz Outer (before plating); 1 oz inner
Final Board Thickness
62 mils (- 5mils / +8mils)
Material
Fiberglass made of FR4
Signal and Power Via Stack
Via Pad
16 mils
Via Anti-Pad
20 mils
Via Finished Hole
8 mils
1. The Cu Thickness is just a reference value. It is calculated by the PCB board producers for
impedance matching.
2.4 4-Layer Board Stack-Up
The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. If
a 4-layer board is used, the stack-up should be:
Figure 2-3 4-layer PCB Stack-Up
Table 2-3 PCB Parameters
Description
Nominal Value
Tolerance
Comments
Board Impedance Z0
50Ω
±10%
With nominal 4 mil trace width
Micro-stripline Er
4.1
±0.4
@ 100 MHz
Trace Width
4.0 mils
±0.5 mils
Standard trace
Trace Thickness
2.1 mils
±0.5 mils
0.5 oz foil + 1.0 oz plate
Solder mask Er
4.0
±0.5
@ 100 MHz
Solder mask Thickness
1.0 mils
±0.5 mils
From top of trace
Signal Layer 1
-----------------------------------------------------
Total Thickness 40 mils.
Ground Layer 3
Core Layer 4
Prepreg Layer 2
Power Layer 5
Signal Layer 7
Prepreg Layer 6

Platform Stack-Up and Placement
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
6
2.5 8-Layer HDI Board Stack-Up
The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. If
a 8-layer HDI board is used, the stack-up should be:
Figure 2-4 8-layer PCB Stack-Up
Table 2-4 PCB Parameters
Description
Nominal Value
Tolerance
Comments
Board Impedance Z0
50Ω
±10%
With nominal 4 mil trace width
Micro-stripline Er
4.1
±0.4
@ 100 MHz
Trace Width
4.0 mils
±0.5 mils
Standard trace
Trace Thickness
2.1 mils
±0.5 mils
0.5 oz foil + 1.0 oz plate
Solder mask Er
4.0
±0.5
@ 100 MHz
Solder mask Thickness
1.0 mils
±0.5 mils
From top of trace
Placement Layer 1
Prepreg Layer 2
Power Layer 11
-----------------------------------------------------
Total Thickness 40 mils.
Ground Layer 5
Prepreg Layer 14
Prepreg Layer 12
Core Layer 10
Core Layer 6
Prepreg Layer 8
Signal Layer 3
Signal Layer 7
Signal Layer 13
Ground Layer 9
Ground Layer 15
Prepreg Layer 4

Static Memory Interface Design Guidelines
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
7
3 Static Memory Interface Design
Guidelines
3.1 Overview
The External NAND Memory Controller (NEMC) divides the off-chip memory space and outputs
control signals complying with specifications of various types of static memory and bus interfaces.
It enables the connection of static memory such as conventional NAND flashmemory (8bit and 16bit
bus width), Toggle NAND flash memory (ONLY 8bit bus width), etc. to this processor or the external
memory interface.
Static memory interface
–Support 3 external chip selection CS3~1#. Each bank can be configured separately
–The size and base address of static memory banks are programmable
–Direct interface to 8/16-bit bus width external memory interface devices or external static
memory to each bank. Read/Write strobe setup time and hold time periods can be
programmed and inserted in an access cycle to enable connection to low-speed memory
–Wait insertion by WAIT pin
–Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory
accesses to different banks, or a read access followed by a write access to the same bank
NAND flash interface
–Support on CS3~CS1, sharing with static memory bank3~bank1
–Support both of conventional NAND flash memory and Toggle NAND flash memory
–Support most types of NAND flashes, 8/ 16-bit data access, 512B/2KB/4KB/8KB/16KB page
size. For 512B page size, 3 and 4 address cycles are supported. For 2KB/4KB/8KB/16KB
page size, 4 and 5 address cycles are supported
–Support read/erase/program NAND flash memory
–Support boot from NAND flash
3.2 Boot Memory
BOOT_SEL [2:0] pins define the boot time configurations as listed in the following table.
Table 3-1 Boot Configuration
BOOT_SEL2
BOOT_SEL1
BOOT_SEL0
Boot From
1
1
1
USB boot (USB 2.0 device, EXTCLK=24MHz)
1
0
0
SD boot @ MSC1 (MMC/SD use GPIO Port E)
1
0
1
SD boot@ MSC0 ( MMC/SD use GPIO Port A)
0
1
1
eMMC boot @ MSC0 (use GPIO PortA)
1
1
0
NAND boot @ CS1
0
0
0
SPI boot @ SPI0/CE0
0
0
1
USB boot (USB 2.0 device, EXTCLK=26MHz)
0
1
0
NOR boot @ CS4 (just for FPGAtesting)

Static Memory Interface Design Guidelines
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
8
The boot procedure is showed in the following flow chart:
In case of NAND/SDcard/iNAND/SPI boot, if it fails, enter MSC1 and USB boot.
In case of USB boot, if it cannot connect to USB host within 10 seconds, restart the boot
procedure.
In case of NOR boot, if it fails, restart the boot procedure.
If the boot procedure has been repeated more than 3 times, enter hibernating mode.
3.3 NAND Flash Connection
It supports on CS [3:1], sharing with static memory bank3~bank1.
The following Figure 3-1 is an example of 16-bit NAND Flash Interconnection; Figure3-2 is an
example of 8-bit Toggle NAND Flash Interconnection.
Figure 3-1 16-bit NAND Flash Interconnection Example
Figure 3-2 8-bit Toggle NAND Flash Interconnection Example
CS[n] #
SA0
SA1
SD [15:0]
JZ4775
FRE#
FWE#
FRB#
CE#
CLE
ALE
I/O [15:0]
NAND Flash
RE#
R/B#
WE#
CS[n]#
SA0
SA1
SD [8:0]
JZ4775
FRE#
FWE#
FRB#
CE#
CLE
ALE
I/O [8:0]
NAND Flash
RE#
R/B#
WE#
DQS
NDQS

DDR3 SDRAM
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
9
4 DDR3 SDRAM
4.1 Overview
DDRC (DDR Controller) is a general IP which provides an interface to DDR2, DDR3, mobile
DDR (LPDDR) memory. The DDRC IP is designed for SOC usage and is configurable, scalable to
meet the requirement of various SOC.
4.2 Connection to two 2 Gb x 16 DDR3 SDRAM device
Figure 4-1 Two 16-bit DDR3 Interconnection Example
CKE
CS#
BA [2:0]
A [13:0]
ODT
RAS#
CAS#
WE#
CK, CK#
RESET#
DQ [15:0]
LDQS, LDQS#
UDQS, UDQS#
LDM
UDM
JZ4775
2 Gb x 16
DDR3 SDRAM
CKE
CS0_N
BA [2:0]
DA [13:0]
ODT0
RAS_N
CAS_N
WE_N
CK, CK_N
RST_N
DQ [15:0]
DQS0, DQS0_N
DQS1, DQS1_N
DM0
DM1
DQ [31:16]
DQS2, DQS2_N
DQS3, DQS3_N
DM2
DM3
CKE
CS#
BA [2:0]
A [13:0]
ODT
RAS#
CAS#
WE#
CK, CK#
RESET#
DQ [15:0]
LDQS, LDQS#
UDQS, UDQS#
LDM
UDM

DDR3 SDRAM
Board Design Guide for JZ4775, Revision 1.1
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
10
4.3 Connection to four 1 Gb x 8 DDR3 SDRAM device
Figure 4-2 Four 8-bit DDR3 Interconnection Example
4.4 Layout Guideline
In the classical high-speed flow, to ensure the maximum performance of the DDR3, we should
observe the following guidelines. The questions we should be noticed are: Flight time delay and
skew, Signal integrity and impedance matching, Crosstalk, Power supply bypassing.
The basic recommendations are as follows:
The minimum Stack-up required four layer stack. There must have a ground layer to
separated two signal layers. Just as describes in Figure 2-3.
Signals should be routed based on the relative tightness of the skew budgets. In order of
priority:
1) The double data rate signals, DQ, DM, and DQS/DQS# should be routed first since
these have the strictest budgets, ¼of a clock period available for set up or hold relative
to the differential strobe.
2) Differential clock, CK/CK# and single data rate signals, Address/Command/Control.
These have looser budgets with ½of a clock period for set up and hold.
3) If read and write leveling techniques are not used, make sure that the rising edges of all
differential DQS/DQS# signals are within ¼of a clock period of the rising edge of the
differential clock, CK/CK#.
4) Route all Vref and support signals (JTAG etc. if implemented)
1Gb x 8
DDR3 SDRAM
CKE
CS#
BA [2:0]
A [13:0]
ODT
RAS#
CAS#
WE#
CK, CK#
RESET#
DQ [8:0]
LDQS, LDQS#
DM
CKE
CS#
BA [2:0]
A [13:0]
ODT
RAS#
CAS#
WE#
CK, CK#
RESET#
DQ [8:0]
LDQS, LDQS#
DM
CKE
CS#
BA [2:0]
A [13:0]
ODT
RAS#
CAS#
WE#
CK, CK#
RESET#
DQ [8:0]
DQS, DQS#
DM
CKE
CS#
BA [2:0]
A [13:0]
ODT
RAS#
CAS#
WE#
CK, CK#
RESET#
DQ [8:0]
DQS, DQS#
DM
JZ4775
CKE
CS0_N
BA [2:0]
DA [13:0]
ODT0
RAS_N
CAS_N
WE_N
CK, CK_N
RST_N
DQ [8:0]
DQS0, DQS0_N
DM0
DQ [15:9]
DQS1, DQS1_N
DM1
DQ [23:16]
DQS2, DQS2_N
DM2
DQ [31:24]
DQS3, DQS3_N
DM3
1 Gb x 8
DDR3 SDRAM

DDR3 SDRAM
Board Design Guide for JZ4775, Revision 1.1
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11
The fundamental high-speed PCB issues are flight time delay and skew. Controlling the
maximum placement of components. All of the shorter nets in a clock domain must be
match the longest one. Therefore, flight time delay and skew are controlled by the matching
of the trace.
Assumptions are 151 ps. /inch for top layer microstrip (air in cross section) and 179 ps./inch
for stripline or embedded microstrip (no air in cross section). The below table is the
recommended budgets.
Table 4-1 The Recommended Budgets
Signal integrity refers to controlling overshoot, ring back, and transition edges. These issues
are caused by the mismatch of impedance. Trace impedance is governed by the trace width
as well as the thickness and dielectric constant of the PCB insulating materials (usually
FR-4). So you should keep the impedance average in a trace, be sure the bending and via
as little as possible.
When the signal has a via in its trace, there must be a GND via beside the signal via.
Crosstalk is fundamentally controlled by the PCB stack-up and minimum trace spacing. The
best approach to avoiding a crosstalk problem is to ensure all the signals have high-quality
signal return paths and to spread the signal out.
oEach signal layer should have a nearby full ground plane to provide the shortest
return current path. In order to maintain consistent characteristic impedance, it is
important that the traces be routed over solid ground planes (Figure 4-3) not
separate (Figure 4-4). A high speed signal trace should never be routed across a
plane split. This will interrupt the return currents that flow beneath the conductor
and can lead to crosstalk with neighboring traces. This will also increase emissions
from the board.
Figure 4-3 GND Joined Together

DDR3 SDRAM
Board Design Guide for JZ4775, Revision 1.1
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12
Figure 4-4 GND is separate
oEach bus (D0~D8, DQS0/DQS0_N and DQM0 compose one bus, and etc.) should
not cross other buses. If routing is carried out on two layers, byte lanes should be
alternated between layers in order to reduce congestion, and crosstalk at the
DRAMs; e.g. Byte lanes 0 and 2 should be routed on one layer, and 1 and 3 on the
other.
oThe crosstalk and characteristic impedance of an array of traces are interrelated. In
order to minimize crosstalk, the characteristic impedance of a trace should be
determined predominantly by the distance to the reference plane and not the
distance to the neighboring traces. To achieve this, the space between traces
should be twice the height of the trace above the ground plane. Figure4-5 shows
the recommended spacing (“H”means the height from reference plane.).
Figure 4-5 Spacing between Different Signal Groups
Precise power supply bypassing is important for high-speed PCB. Control the power supply
high-frequency impedance means controlling power supply inductance. Power supply
high-frequency impedance is beaten down by many small capacitors connected between
the power and ground plane. Using many capacitors, rather than a large one, will reduce
the inductance. The inductance of a capacitor is dependent on its size. The capacitor
DDR3

DDR3 SDRAM
Board Design Guide for JZ4775, Revision 1.1
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13
need to be placed very close to the device they are bypassing.
VREF is used as a reference by the input buffers of the DDR3 memories. It is recommended
to be 1/2 of the DDR3 power supply voltage and should be created using a resistive divider
as shown in the schematic. Other methods are not recommended. Figure 4-5 shows the
layout guidelines for VREF.
Figure 4-6 VREF Routing and Topology
The region of the PCB used for DDR3 circuitry must be isolated from other signals. Region
should be encompassing all DDR3 circuitry and varies signals depending on placement.
Non-DDR3 signals should not be routed on the DDR3 signal layer within the DDR3 keep out
region. No breaks should be allowed in the reference ground layers in the region. In addition,
the +1.5V power plane should cover the entire keep out region.
Bypassing capacitors should be close to the devices, or positioned for the shortest
connections to pins, with wide traces to reduce impedance.
DDR3
JZ4775
DDR3
VREF nominal
minimum trace
width is 20 mils
VREF bypass
capacitor

Audio Design Guidelines
14
Board Design Guide for JZ4775, Revision 1.0
Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
5 Audio Codec Design Guidelines
5.1 Overview
This chapter describes the embedded audio CODEC in the processor. This embedded CODEC is
an I2S audio CODEC. AIC (AC'97 and I2S Controller) module is an interface to this CODEC for
audio data replaying and recording.
5.2 Audio Power
AVDCDC25 andAVDHP25should are connected to a cleaned +2.5V power.
For correct working, it is required to connect decoupling capacitors (22μF and 100nF ceramic)
between the pins AVDCDC25, AVDHP25 andAVSCDC, AVSHP.
A 10μF ceramic or tantalum capacitor in parallel with a 0.1μF ceramic capacitor should be attached
from VCAP toAVSCDC to eliminate the effects of high frequency noise.
5.3 Headphone Out
The capacitor-less circuit for headphone out is recommended，because this circuit is no POP noise
which is caused by the coupled capacitor.
The AOHPL and AOHPR pins are applied directly to the loads. The ground of the headphone is
connected to AOHPM. The DC value of the signal AOHPL\ AOHPR\ AOHPM equals to VREF/2.
The measurement ground reference corresponds to the physical interconnection of AOHPM and
AOHPMS. AOHPM and AOHPMS have to be connected together as close as possible of the
headphone connector. The measurement is done between AOHPL/R and the measurement ground
reference.
The C52, C54, R56, R57 combine into two RC circuits to improve the headphone out performance.
The ESD1 and ESD3 is an ESD transient voltage suppression component which provides a very
high level of protection for sensitive electronic components that may be subjected to electrostatic