Inova ICP-PIII User manual

CompactPCI
®
ICP-PIII
High-Performance
CPU Boards
USER’S MANUAL
Publication Number: PD00581013.004 AB
MAN-ICP-PIII

This user’s manual describes a product that, due to its nature, cannot describe a particular applica-
tion. The content of this user’s manual is furnished for informational use only, is subject to change
without notice, and should not be constructed as a commitment by Inova Computers GmbH.
Inova Computers GmbH assumes no responsibility or liability for any errors or inaccuracies that
may appear in this user’s manual.
Except as otherwise agreed, no part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means, electronic, mechanical, recording, or other-
wise, without the prior written consent of Inova Computers GmbH.
Products or brand names are trademarks or registered trademarks of their respective companies or
organisations.
Inova Computers GmbH Inova Computers Inc,
Innovapark 20 270 Communication Way, Bldg. #6
D-87600 Kaufbeuren Hyannis, MA 02601
Germany USA
Tel.: ++49 (0) 8341 62 65 Tel.: ++1-508-771-4415
Fax: ++49 (0) 8341 62 69 Fax: ++1-508-771-4346
email: [email protected] email: [email protected]
http://www.inova-computers.com

©2002 Inova Computers GmbH Page 0-1Doc. PD00581013.004
ICP-PIII Preface
CompactPCI
®
Preface
Contents
Unpacking and Special Handling Instruc-
tions ............................................... 6
Revision History ............................... 7
Three Year Limited Warranty.............. 8
1.0 ICP-PIII CPU ........................... 1-2
1.01 Interfacing ............................................................................................... 1-3
1.02 Peripherals ............................................................................................... 1-3
1.03 Software .................................................................................................. 1-3
1.04 Graphics .................................................................................................. 1-3
1.1 Specifications ......................... 1-4
1.2 Configuration .......................... 1-6
Table 1.20 ‘Processor Overview .................................................................................................. 1-6
Figure 1.20 ICP-PIII Overview..................................................................................................... 1-7
1.3 Software ................................ 1-8
1.31 Linux........................................................................................................ 1-8
1.32 VentureCom............................................................................................. 1-8
1.33 Windows 2000 ......................................................................................... 1-8
1.34 Windows CE ............................................................................................. 1-9
1.35 VxWorks ................................................................................................... 1-9
1.36 OS-9 x86 ................................................................................................. 1-9
1.37 QNX ........................................................................................................ 1-9
1.38 Jbed ......................................................................................................... 1-9

©2002 Inova Computers GmbHPage 0-2 Doc. PD00581013.004
Preface ICP-PIII
1.4 Hardware ............................. 1-10
1.41 Block Diagram........................................................................................ 1-10
Figure 1.41 Block Diagram....................................................................................................... 1-10
1.42 Connector Location ............................................................................... 1-11
Figure 1.42 Connector Locations .............................................................................................. 1-11
1.43 Connector Description ........................................................................... 1-11
Table 1.43 Connector Description ............................................................................................ 1-11
Table 1.43 Continued .............................................................................................................. 1-12
1.44 Front-Panel Features............................................................................... 1-12
Table 1.44 Front Panels ........................................................................................................... 1-12
Figure 1.44 Front-Panel Options .............................................................................................. 1-13
1.45 Interface Positions .................................................................................. 1-14
Figure 1.45 Interfaces .............................................................................................................. 1-14
2.0 Memory Map........................... 2-2
Figure 2.00 System Architecture ................................................................................................. 2-2
Table 2.00 UMB Reservations for ISA ......................................................................................... 2-3
Table 2.01 Port Addressing ........................................................................................................ 2-3
2.1 I/O Mapped Peripherals............. 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4
2.2 Memory Mapped Peripherals ..... 2-5
2.3 Interrupt Routing .................... 2-5
Table 2.30 PC-AT Interrupt Definitions ....................................................................................... 2-6
2.4 Inova PIII Device List ................ 2-7
Table 2.40 Legacy I/O Map (ISA Compatible) ............................................................................ 2-7
2.5 Interrupt Configuration ............ 2-8
Table 2.50 CompactPCI Bus Interrupts ....................................................................................... 2-8
2.6 Timer / Counter ....................... 2-9
2.7 Watchdog ............................... 2-9
3.0 CompactPCI J1/J2 Connector ... 3-3
3.01 CompactPCI Connector ........................................................................... 3-3
Figure 3.01 The 32-Bit CompactPCI Bus Interface Connector ...................................................... 3-3
3.02 ICP-PIII Connector J1 and J2 ..................................................................... 3-3
Table 3.02 Inova’s ICP-PIII 32-Bit CompactPCI J1 Pin Assignment ............................................... 3-4
Table 3.03 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment (Standard) ............................ 3-5
Table 3.04 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (A) ..................... 3-6
Table 3.05 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (B)...................... 3-7
Table 3.06 Inova’s ICP-PIII 32-Bit CompactPCI J2 Pin Assignment for Rear I/O (C) ..................... 3-8
Table 3.07 Inova’s ICP-PIII Rear I/O J2 (CPU) Integration .......................................................... 3-9

©2002 Inova Computers GmbH Page 0-3Doc. PD00581013.004
ICP-PIII Preface
CompactPCI
®
3.1 CompactPCI Backplane .......... 3-10
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot ................................ 3-11
3.2 Interfaces ............................. 3-12
3.21 J7 & J12 Fast Ethernet ............................................................................ 3-12
Figure 3.21 RJ45 Pinout ........................................................................................................... 3-12
Table 3.21 Ethernet Connector Signals ..................................................................................... 3-12
3.22 J17 VGA Interface ................................................................................... 3-13
Figure 3.22 High-Density D-Sub VGA Interface Pinout .............................................................. 3-13
Table 3.22 Video Output Connector Signals ............................................................................. 3-13
Table 3.22b Video Resolutions ................................................................................................. 3-14
3.23 J16 PanelLink Interface ........................................................................... 3-15
Figure 3.23 PanelLink Interface Connector ............................................................................... 3-15
Table 2.12 PanelLink Interface ................................................................................................. 3-15
2.24 J16 GigaSTAR Interface ........................................................................... 3-16
Figure 2.24 GigaSTAR D-Sub Interface Pinout........................................................................... 3-16
Table 2.11 GigaSTAR Interface ................................................................................................ 3-16
3.25 J19 USB Interface ................................................................................... 3-17
Figure 3.25 USB Interface Pinout .............................................................................................. 3-17
Table 3.25 USB Connector Signals ........................................................................................... 3-17
3.26 J15 FireWire Interface ............................................................................. 3-18
Figure 3.26 FireWire Interface Pinout ........................................................................................ 3-18
Table 3.26 FireWire Connector Signals ..................................................................................... 3-18
3.27 J20 Infrared (iRdA) Interface ................................................................... 3-19
3.28 J20 Reset Button..................................................................................... 3-19
3.29 J14 FLASH Interface ................................................................................ 3-19
3.30 J18 Floppy Disk Interface ........................................................................ 3-19
3.31 Connecting the PIII to the Inova IPB-FPE8 .............................................. 3-20
Figure 3.31 CPU to IPB-FPE8 Connection .................................................................................. 3-20
3.32 Connecting the PIII to the Inova ICP-HD-1 ............................................. 3-21
Figure 3.32 CPU to ICP-HD-1 Connection................................................................................. 3-21
3.33 Connecting the PIII to the Inova IPB-FPE12 ............................................ 3-22
Figure 3.33 CPU to IPB-FPE12 Connection ................................................................................ 3-22
3.34 Connecting the PIII to the Inova IPB-FPE12 ............................................ 3-23
Figure 3.34 CPU to IPB-FPE12 Connection ................................................................................ 3-23
3.35 Connecting the PIII to the ICP-FD-1 ....................................................... 3-24
Figure 3.35 CPU to Slim-Line Floppy Disk Connection ............................................................... 3-24

©2002 Inova Computers GmbHPage 0-4 Doc. PD00581013.004
Preface ICP-PIII
A1 IPB-FPE8 CPU Extension ......... A-2
A1.1 J11 Interface for COM1, Mouse & Keyboard ............................................ A-2
A1.2 IPB-FPE8 & Front-panel (4HP or 8HP)....................................................... A-2
Figure A1.2 IPB-FPE8 Stand-Alone or Integrated with CPU .......................................................... A-2
A1.3 Stand-Alone IPB-FPE8 ............................................................................... A-3
Figure A1.3 Stand-Alone Piggyback Interface IPB-FPE8 ............................................................... A-3
A1.4 IPB-FPE8MS (Theme Variation) ................................................................. A-4
Figure A1.4 Piggyback Interface IPB-FPE8MS .............................................................................. A-4
Table A1.4 IPB-FPE8MS Connector Description ........................................................................... A-4
A1.5 IPB-FPE8MS Description ........................................................................... A-5
Figure A1.5 Top & Bottom Views of the IPB-FPE8MS ................................................................... A-5
Table A1.5 Standard Hard-Disk & Floppy Disk Connectors .......................................................... A-5
A1.6 Keyboard Interface ................................................................................... A-6
Figure A1.6 Keyboard Interface Pinout ...................................................................................... A-6
Table A1.6 Keyboard Connector Signals ..................................................................................... A-6
A1.7 Mouse Interface ....................................................................................... A-6
Figure A1.7 Mouse Interface Pinout ............................................................................................ A-6
Table A1.7 Mouse Connector Signals ......................................................................................... A-6
A1.8 COM1 Interface ....................................................................................... A-7
Figure A1.8 COM1 Interface Pinout ............................................................................................ A-7
Table A1.8 COM1 Connector Signals ......................................................................................... A-7
B1 ICP-HD CPU Extension ............. B-2
B1.1 J11, J13 Interfaces .................................................................................... B-2
B1.2 ICP-HD-1 & Front-panel (4HP or 8HP)...................................................... B-2
Figure B1.2 ICP-HDE8 Stand-Alone or Integrated with CPU......................................................... B-2
B1.3 IDE Carrier Board ICP-HD-1 ...................................................................... B-3
Figure B1.3 IDE Carrier Board ICP-HD1 ...................................................................................... B-3
Table B1.3 ICP-HD-1 Connector Description ............................................................................... B-4
B1.4 ICP-HDE8MS (Theme Variation) ............................................................... B-4
Figure B1.4 IDE Carrier ICP-HDE8MS.......................................................................................... B-4
Table B1.4 IPB-HDE8MS Connector Description .......................................................................... B-5
B1.5 ICP-HDE8MS Description ......................................................................... B-6
Figure B1.5 Top & Bottom Views of the ICP-HDE8MS .................................................................. B-6
B1.6 Keyboard Interface ................................................................................... B-7
Figure B1.6 Keyboard Interface Pinout ....................................................................................... B-7
Table B1.6 Keyboard Connector Signals ..................................................................................... B-7
B1.7 Mouse Interface ....................................................................................... B-7
Figure B1.7 Mouse Interface Pinout ............................................................................................ B-7
Table B1.7 Mouse Connector Signals.......................................................................................... B-7
B1.8 COM1 & COM 2 Interfaces...................................................................... B-8
Figure B1.8 COM1 & COM2 Interface Pinout ............................................................................. B-8
Table B1.8 COM1 & COM2 Connector Signals ........................................................................... B-8

©2002 Inova Computers GmbH Page 0-5Doc. PD00581013.004
ICP-PIII Preface
CompactPCI
®
B1 IPM-ATA CPU Extension ........... B-2
B1.1 J1 Interfaces ............................................................................................. B-2
Figure B1.1a Dedicated IPM-ATA Backplane................................................................................ B-2
B1.1 J1 Interfaces (Contd.) ............................................................................... B-3
Figure B1.1b The Complete Connection Picture........................................................................... B-3
B1.2 IPM-ATA-HD ............................................................................................. B-4
Figure B1.2 IPM-ATA-HD Board Layout ....................................................................................... B-4
Table B1.2 IPM-ATA-HD Jumper Description ............................................................................... B-4
B1.3 IPM-ATA-CF .............................................................................................. B-5
Figure B1.3 IPM-ATA-CF Board Layout ........................................................................................ B-5
Table B1.3 IPM-ATA-CF Jumper Description................................................................................. B-5
B1.4 IPM-ATA-PCMCIA ..................................................................................... B-6
Figure B1.4 IPM-ATA-PCMCIA Board Layout ............................................................................... B-6
Table B1.4 IPM-ATA-PCMCIA Jumper Description ........................................................................ B-6
B1.5 Device Compatibility ................................................................................ B-7
Table B1.5 Compatibility List ...................................................................................................... B-7
C1 IPB-FPE12 CPU Extension ........ C-2
C1.1 J13 Interface for LPT1 & COM2 ............................................................... C-2
C1.2 IPB-FPE12 & Front-panel (4HP or 12HP) .................................................. C-2
Figure C1.2 IPB-FPE12 Stand-Alone or Integrated with CPU ........................................................ C-2
C1.3 LPT1 & COM2 Piggyback ........................................................................ C-3
Figure C1.3 LPT1 & COM2 Piggyback Board IPB-FPE12 .............................................................. C-3
Table C1.3 IPB-FPE12 Connector Description .............................................................................. C-4
C1.4 LPT1 Interface.......................................................................................... C-5
Figure C1.6 LPT1 Interface Pinout .............................................................................................. C-5
Table C1.6 LPT1 Connector Signals ............................................................................................ C-5
C1.5 COM2 Interface ....................................................................................... C-6
Figure C1.5 COM2 Interface Pinout ........................................................................................... C-6
Table C1.5 COM2 Connector Signals ......................................................................................... C-6
D1 IPB-RIO CPU Extension............ D-2
D1.1 IPB-RIO-HD-FD ....................................................................................... D-2
Figure D1.1 IPB-RIO-HD-FD ....................................................................................................... D-2
D1.2 IPB-RIO-HD-LPT-(FLEX) ........................................................................... D-3
Figure D1.2 IPB-RIO-HD-LPT-(FLEX)............................................................................................ D-3
D1.3 IPB-RIO-C-SHORT ................................................................................... D-4
Figure D1.3 IPB-RIO-C-SHORT ................................................................................................... D-4
Table D1.3 Rear I/O Type ‘C’ ..................................................................................................... D-4
D1.4 IPB-RIO-C-80MM.................................................................................... D-5
Figure D1.4 IPB-RIO-C-80MM .................................................................................................... D-5

©2002 Inova Computers GmbHPage 0-6 Doc. PD00581013.004
Preface ICP-PIII
Unpacking and Special Handling
Instructions
This product has been designed for a long and fault-free life; nonetheless, its life expectancy can
be severely reduced by improper treatment during unpacking and installation.
Observe standard antistatic precautions when changing piggybacks, ROM devices, jumper set-
tings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not
placed on conductive surfaces as these can cause short circuits, damage the batteries or disrupt
the conductive tracks on the board.
Do not exceed the specified operational temperature ranges of the board version ordered. If
batteries are present, their temperature restrictions must be taken into account.
Keep all the original packaging material for future storage or warranty shipments. If it is necessary
to store or ship the board, re-pack it as it was originally packed.
Before returning this product for repair, please ask for an RMA (Returned Material Authorization)
number and supply the following information:
LCompany name, contact person, shipping address and invoice address
LProduct name and serial number
LFailure or fault description
LClearly write the RMA number on the outside of the transportation carton.

©2002 Inova Computers GmbH Page 0-7Doc. PD00581013.004
ICP-PIII Preface
CompactPCI
®
Revision History
Manual MAN-ICP-PIII
Publication Number PD00581013.XXX
Issue Author
Date of Issue
PD00581013.001 AB 31/11/2000
PD00581013.002 AB 15/08/2001
PD00581013.003 AB 21/09/2001
PD00581013.004 AB 15/02/2002Specs. Updated & Rear I/O Table Corrected
Final Version - Included Appendix A-D I/O Modules
Revision History
Preliminary, First Release; All pages revised
Brief Description of Changes
Updated to include Radeon VE and Rear I/O options

©2002 Inova Computers GmbHPage 0-8 Doc. PD00581013.004
Preface ICP-PIII
Three Year Limited Warranty
Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware
warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are
valid unless the consumer has the expressed written consent of Inova.
Inova warrants their own products (excluding software) to be free from defects in workmanship
and materials for a period of 36 consecutive months from the date of purchase. This warranty is
not transferable nor extendible to cover any other consumers or long term storage of the product.
This warranty does not cover products which have been modified, altered, or repaired by any
other party than Inova or their authorized agents. Furthermore, any product which has been, or
is suspected of being damaged as a result of negligence, misuse, incorrect handling, servicing or
maintenance; or has been damaged as a result of excessive current/voltage or temperature; or has
had its serial number(s), any other markings, or parts thereof altered, defaced, or removed will
also be excluded from this warranty.
A customer who has not excluded his eligibility for this warranty may, in the event of any claim,
return the product at the earliest possible convenience, together with a copy of the original proof
of purchase, a full description of the application it is used on, and a description of the defect; to
the original place of purchase.
Pack the product in such a way as to ensure safe transportation (we recommend the original
packing materials), whereby Inova undertakes to repair or replace any part, assembly or sub-
assembly at our discretion; or, to refund the original cost of purchase, if appropriate.
In the event of repair, refund, or replacement of any part, the ownership of the removed or
replaced parts reverts to Inova, and the remaining part of the original guarantee, or any new
guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired
items. Any extensions to the original guarantee are considered gestures of goodwill, and will be
defined in the “Repair Report” returned from Inova with the repaired or replaced item.
Other than the repair, replacement, or refund specified above, Inova will not accept any liability
for any further claims which result directly or indirectly from any warranty claim. We specifically
exclude any claim for damage to any system or process in which the product was employed, or
any loss incurred as a result of the product not functioning at any given time. The extent of
Inova’s liability to the customer shall not be greater than the original purchase price of the item
for which any claim exists.
Inova makes no warranty or representation, either expressed or implied, with respect to its prod-
ucts, reliability, fitness, quality, marketability or ability to fulfil any particular application or pur-
pose. As a result, the products are sold “as is,” and the responsibility to ensure their suitability for
any given task remains the purchaser’s. In no event will Inova be liable for direct, indirect, or
consequential damages resulting from the use of our hardware or software products, or docu-
mentation; even if we were advised of the possibility of such claims prior to the purchase of, or
during any period since the purchase of the product. Please remember that no Inova employee,
dealer, or agent are authorized to make any modification or addition to the above terms, either
verbally or in any other form written or electronically transmitted, without consent.

©2002 Inova Computers GmbH Page1-1Doc. PD00581013.004
ICP-PIII Product Overview
CompactPCI
®
1
Product Overview
Overview Contents
1.0 ICP-PIII CPU ........................... 1-2
1.01 Interfacing ............................................................................................... 1-3
1.02 Peripherals ............................................................................................... 1-3
1.03 Software .................................................................................................. 1-3
1.04 Graphics .................................................................................................. 1-3
1.1 Specifications ......................... 1-4
1.2 Configuration .......................... 1-6
Table 1.20 ‘Processor Overview .................................................................................................. 1-6
Figure 1.20 ICP-PIII Overview..................................................................................................... 1-7
1.3 Software ................................ 1-8
1.31 Linux........................................................................................................ 1-8
1.32 VentureCom............................................................................................. 1-8
1.33 Windows 2000 ......................................................................................... 1-8
1.34 Windows CE ............................................................................................. 1-9
1.35 VxWorks ................................................................................................... 1-9
1.36 OS-9 x86 ................................................................................................. 1-9
1.37 QNX ........................................................................................................ 1-9
1.38 Jbed ......................................................................................................... 1-9
1.4 Hardware ............................. 1-10
1.41 Block Diagram........................................................................................ 1-10
Figure 1.41 Block Diagram....................................................................................................... 1-10
1.42 Connector Location ............................................................................... 1-11
Figure 1.42 Connector Locations .............................................................................................. 1-11
1.43 Connector Description ........................................................................... 1-11
Table 1.43 Connector Description ............................................................................................ 1-11
Table 1.43 Continued .............................................................................................................. 1-12
1.44 Front-Panel Features............................................................................... 1-12
Table 1.44 Front Panels ........................................................................................................... 1-12
Figure 1.44 Front-Panel Options .............................................................................................. 1-13
1.45 Interface Positions .................................................................................. 1-14
Figure 1.45 Interfaces .............................................................................................................. 1-14

©2002 Inova Computers GmbHPage1-2 Doc. PD00581013.004
Product Overview ICP-PIII
1.0 ICP-PIII CPU
The ICP-PIII is a high-performance 3U CompactPCI single-board Socket 370 based universal CPU
that satisfies the needs of a wide range of industrial automation, military, medical, aerospace,
imaging, telecommunications, process control and embedded/OEM applications. The powerhouse
in any application, Inova’s Socket 370 based high-performance 3U CompactPCI CPU is packed
with a feature set unheard of on such a small scale. With 128MByte on-board SDRAM with BIOS
controlled ECC, the ICP-PIII suits the demands placed by modern operating systems. In addition,
performance scalability is assured through the broad selection of Intel Pentium III and Celeron
BGA2 (mobile) and FC-PGA devices.
Conforming to the latest PICMG CompactPCI specification the ICP-PIII has a colourful feature set
of rear I/O options and supports basic hot-swap. Being of a universal design, both 5.0 and 3.3V
I/O signalling voltages are possible without modification.
Although the CPU measures just 160mm by 100mm it is fabricated using the latest 12-layer PCB
technology and with over 4800 PCB links and 6550 solder points the ICP-PIII is truly a miracle of
engineering achievement.
Inova’s high-performance, high-density 3U PIII board provides support on all three major serial
networking levels that include Fast Ethernet, FireWire and USB. To enable so much functionality to
exist in such a small footprint, the ICP-PIII is able to host the I/O on either the front-panel or in the
form of rear I/O or even both. Implementing the latest Intel chipsets and processors available for
the embedded market the ICP-PIII is adequately equipped to provide support for all major operat-
ing systems and off-the-shelf application software.
The built-in graphic solution not only saves space within a rack that would otherwise be taken-up
by an additional graphics board, but due to its extremely efficient use of hardware real-estate,
costs can be cut too. Modularity is further assured through the use of dedicated plug-in SDRAM
modules.
On-board peripheral connectors allow the CPU to be enhanced to include mouse, keyboard,
COM and LPT functions. Slim-line 1.44MByte floppy disk and EIDE interfaces provide the mass-
storage possibilities and due to the rear I/O possibilities, one of the EIDE channels (2 devices) can
be used for remote connection of hard disks or CD-ROM drive etc.

©2002 Inova Computers GmbH Page1-3Doc. PD00581013.004
ICP-PIII Product Overview
CompactPCI
®
1
1.01 Interfacing
For maximum communication flexibility, multiple interfaces satisfying different industrial stand-
ards are implemented. LAN applications can take advantage of Inova’s 10BaseT/100BaseTx (dual)
Ethernet implementation or, if high-speed system-level serial interfacing is required, the built-in
400/100 Mbit/s FireWire port is available. Peripherals may be connected to the standard USB or,
as an option, the on-board PCI bus allows support of custom I/O piggybacks conforming to
Inova’s open specification.
The Intel 21554 non-transparent PCI/PCI bridge is utilised for multiprocessing applications equipped
with a Master and Slave CPU in the same system.
1.02 Peripherals
The ICP-PIII supports standard PC peripherals like floppy disk, hard disk and CD ROM. Notebook
style hard disks may be connected directly to the base-board (2-slot) and possess their own front-
panel offering COM ports and PS-2 style connectors for mouse and keyboard.
1.03 Software
The following operating systems have been verified with Inova’s PIII, 3U CompactPCI CPU:
NLinux
NWindows®NT®& VenturCom RTX® (Real-Time Extension)
NWindows®2000
NWindows ®CE
NW indows ®9x
NWindriver VxWorks®
NQNX®
NEsmeralda Technology Jbed® (under development)
NSolaris x86
All readily available application software designed for operation on the standard x86 architecture
will execute without modification.
1.04 Graphics
The Lynx3DM graphic controller is a highly integrated 128-bit GUI (Graphical User Interface)
engine supporting dual independent graphic displays. Screen resolutions up to 1600 x 1200
pixels with 24-bit (True Colour) are supported.
The introduction of the ATI Radeon VE, with its 16MByte video RAM and superior 3D acceleration
& hardware MPEG-2 support, enables screen resolutions up to 2048 x 1536 pixels to be driven.
Dual video and TFT dual-scan/single-scan colour panels are supported with configurable colour
depths. In addition, Inova’s ICP-PIII caters for the needs of the GigaST)R, PanelLink™ and LVDS
user.

©2002 Inova Computers GmbHPage1-4 Doc. PD00581013.004
Product Overview ICP-PIII
1.1 Specifications
Processor Socket 370 BGA (mobile) or FC-PGA based Intel Pentium III or Celeron
Pentium III Up to 1000MHz
(100MHz PSB, 256kByte L2 cache)
Mobile PIII Up to 700MHz BGA2 package with interposer
(100MHz PSB, 256kByte L2 cache)
Mobile Celeron BGA2 package with interposer
(100Mz PSB, 128kByte L2 cache)
L2 Cache 128/256kByte L2 cache depending on processor
Memory 128MByte soldered synchronous DRAM with optional BIOS activated
ECC feature. Additional Piggyback provides additional 128MByte,
or 384MByte
FLASH-Disk Available as an option (Disk-on-Chip™) providing up to 500MByte FLASH
Battery Lithium cell for RTC (NV-RAM) with a lifetime > 8 years
North Bridge 440BX North Bridge 82443BX supporting:
A100MHz system bus DRAM controller with 64bit, 100MHz
SDRAM interface
AECC support
AAGP 2X interface (66/133MHz)
APower management
South Bridge M1543C:
APCI/ISA Bridge
ASuper I/O: 1 Floppy Disk Controller, 1 Parallel Port, 2 Serial Ports
AFast IR
AIDE Controller (4 devices)
AUltra 66 DMA support
A12Mbit/s USB controller
AInterrupt controller
APower Management Unit
AFull support for ACPI and OS directed power management
AMouse & keyboard controller
Graphics Lynx3DM or Radeon VE graphic accelerator
A8/16Mbyte SGRAM/SDRAM
A3D graphics, DVD & MPEG-2 support
AMulti-Display
ADual View support under Microsoft Windows®9x, Windows®NT®
& Windows®2000
ACRT / TFT resolutions up to 2048x1536
AGigaST)R / PanelLink™ or TFT Piggyback
Dual display option or TFT will require dedicated front-panel.
Recovery BIOS FLASH Recovery BIOS
Watchdog Programmable up to 10 minutes; issues NMI or Reset

©2002 Inova Computers GmbH Page1-5Doc. PD00581013.004
ICP-PIII Product Overview
CompactPCI
®
1
PCI/PCI Intel 21150 transparent bridge (Master) or Intel 21554 non-transpar-
ent PCI/PCI bridge for multiprocessing (Slave) operation with Basic
Hot-Swap support (PICMG 2.1 R1.0), Serialized interrupts and univer-
sal (3.3/5.0V) V I/O support
On-Board I/O A10/100 MBit/s Ethernet (Intel 82559)
Aoptional 2nd independent Fast Ethernet
AUp to 2x 12Mbit/s USB
AUp to 2x 400Mbit/s FireWire interfaces
Rear I/O Standard to all CPU variants is option ‘C’ which provides 2nd FireWire
channel, 2nd USB channel, LPT1 (Floppy), EIDE and loudspeaker.
Other I/O configurations including customized are possible.
Mass Storage 1.44MByte 3.5” floppy drive and EIDE (flex cable/rear I/O) support-
ing 2 pairs (Master/Slave) hard-disks or CD ROMs
Front-Panels Optional 4TE front-panel extension provides:
COM1, COM2, keyboard, PS-2 mouse
Extended front-panel (4TE) provides:
COM2, LPT1
Connectors USB (USB), RJ45 (Ethernet), 6-pin FireWire (FireWire), 15-pin D-Sub
(PanelLink), 15-pin high-density D-Sub (VGA), 9-pin D-Sub
(GigaST)R)
CompactPCI PICMG 2.0 R3.0, 32-bit, 33MHz system slot interface with 7 Master
(DMA) support. Dual-slot operation
Mechanics 3U (100 x 160 x 21mm) 4 TE
3U (100 x 160 x 42mm) 8 TE
3U (100 x 160 x 63mm) 12 TE
Power Cons. 25W typ. PIII @ 850MHz (Lynx)
21W typ. PIII @ 700MHz (Lynx)
12W typ. Mobile PIII @ 500MHz (Lynx)
Software Windows® NT®, Windows® 2000, Windows® 9x, Linux,
Support VxWorks®, QNX®
Mass 220g (4TE)
Oper. Temp. 0°C to +60°C (Ambient)*
Storage Temp. -40°C to +85°C (400MHz Mobile [Lynx] only)
Extended Temp. -40 to +85°C (Seleted CPUs only)
Humidity 5% to 95% (non-condensing)
Warranty Three-year limited warranty
Conformance PICMG 2.0 R3.0
CE
*Note: Any CPU fitted with HD, FD or CD-ROM etc. has a max. operational temperature of 50 °C
CPUs without HD or PC inter faces ar e single-slot (4TE) for ‘pr ocessor speeds ≤700MHz.
Mobile processors are passively cooled - installation MUSThave >0.3m/s air flow!

©2002 Inova Computers GmbHPage1-6 Doc. PD00581013.004
Product Overview ICP-PIII
1.2 Configuration
Inova’s high-performance, high-density 3U PIII board supports functionality and connectivity on
all three major serial networking levels like Fast Ethernet, FireWire and USB as well as most state-of-
the-art fieldbus standards such as PROFIBUS, CAN, Interbus, and LON.
Three CPU groups exist to cater for the needs of all aspects of CompactPCI integration: The high-
end typically supports 128MBytes on-board soldered SDRAM, Lynx3DM graphic controller with
8MByte SGRAM and all I/O. For standard applications, the same base layout is utilized however,
the soldered SDRAM, graphic controller and many of the peripheral connections are absent for
use in typical embedded applications. Finally, for multiprocessing applications, the PCI/PCI trans-
parent bridge is replaced by the 21554 non-transparent version.
All CPU family members can possess up to 512MByte SDRAM with BIOS controlled ECC through
a combination of soldered memory units and plug-in modules. FLASH up to 512MByte may be
realised in a similar manner. All CPUs are equipped with a shielded front-panel with typically VGA,
USB, FireWire and Fast Ethernet interfaces installed. Other front-panels are available with mouse,
keyboard, COM, LPT, TFT, PanelLink or dual Ethernet interfaces. The choice of Lynx 3DM or ATI
Radeon VE graphic controller complete with 8/16MByte video RAM is available as an option as is
multiprocessing.
Table 1.20 ‘Processor Overview
CPU Family Processor CPU Speed(s) Multi-Processing Package
ICP-PIII-fegsm Intel PIII 400 to 850MHz No FC-PGA
ICP-SPIII-fegsm Intel PIII 400 to 850MHz Yes FC-PGA
ICP-xxPIII-fegsm Mobile PIII/Celeron 400 to 700MHz Yes / No BGA2 (Interposer)

©2002 Inova Computers GmbH Page1-7Doc. PD00581013.004
ICP-PIII Product Overview
CompactPCI
®
1
100/10Mbit
Ethernet
FLASH Extension:
Up to 512MByte
TFT,
GigaST)R,
PanelLink or LVDS
North-Bridge
Optional
Multiprocessing
Socket 370 or
BGA2 based
Intel Pentium III
or Celeron
Inova’s CPUs have been prepared for rear I/O operation. Currently (RIO-C), EIDE, FireWire2, USB2,
LPT1 and the loudspeaker signals are present on the backplane (if requested at time of order.)
Other options may also be available (including customer specific) but are not referred to in this
user’s handbook. In order to take full advantage of the rear I/O features, the CompactPCI back-
plane needs to support them. Inova provides two standard versions; one has the J2 connector at
the CPU location extended to the rear of the backplane while the other version has all slots fitted
with the J2 connector on both the front and rear.
Figure 1.20 ICP-PIII Overview
VGA,
GigaST)R
PanelLink
LVDS,
FireWire
USB
Optional Lynx3DM or
Radeon VE Graphic
Controller (Under-
side)
128MB or 384MB
SDRAM Extension
512MByte in Development
PCI Interface for
Piggyback Extensions

©2002 Inova Computers GmbHPage1-8 Doc. PD00581013.004
Product Overview ICP-PIII
1.3 Software
1.31 Linux
Being a modern operating system, Linux executes a 32-bit architecture, uses pre-emptive multi-
tasking, has protected memory, supports multiple users, and has rich support for networking,
including TCP/IP. Linux was originally written for Intel’s 386 architecture, but now runs on a wide
variety of hardware platforms including the full x86 family of processors as well as Alpha, SPARC,
and PowerPC.
Linux’s architecture also creates a more reliable and inherently stable system through the use of
protected memory and pre-emptive multitasking. Protected memory prevents an error in one
application from bringing down the entire system, and genuine multitasking means that a bottle-
neck in one application does not hold up the entire system. Linux also maintains a very clean
separation between user processes and kernel processes. While other server class operating sys-
tems use protected memory this feature is prone to failure if faulty applications are allowed to
invade kernel space with their processes.
1.32 VentureCom
Hard, real-time scalability and embedded operation extensions are required for Windows NT by
HAL modification for deterministic interrupt handling at multiple priority levels. This approach
achieves response times in the µs range and reduces hardware resource requirements while main-
taining full compatibility with the enormous range of standard software and device drivers written
for the Windows NT operating system.
1.33 Windows 2000
Windows 2000 is highly reliable and available 32-bit OS.
Support for USB devices allows connection of peripherals without the need to reboot the system
and unlike Windows NT 4.0 support is also provided for the IEE1394a (FireWire) devices. Finally,
secure, wireless communication between two Windows 2000-based computers is possible using
the popular IrDA infrared protocol.
Removable storage devices such as DVD and Device Bay are supported as are new display devices
such as Accelerated Graphics Port (AGP), multiple video cards and monitors, OpenGL 1.2, DirectX®
7.0 API, and Video Port Extensions.
With Plug and Play automatic installation of new hardware is possible with only minimal configu-
ration. More than 12,000 devices now support this functionality.

©2002 Inova Computers GmbH Page1-9Doc. PD00581013.004
ICP-PIII Product Overview
CompactPCI
®
1
1.34 Windows CE
Microsoft® Windows CE is an operating system designed for a wide variety of embedded systems
and products, from hand-held PCs and consumer electronic devices to specialized industrial con-
trollers and embedded communications devices. The Windows CE operating system has proved
itself capable of handling the most demanding 32-bit embedded applications by bringing the full
power of the Microsoft's 32-bit programming and operating systems technology to the embed-
ded systems designer. Windows CE is actually a collection of operating system modules and com-
ponents that can be selected and configured to meet the needs of a specific embedded applica-
tion or product.
1.35 VxWorks
WindRiver’s run-time system solution is a high-performance RTOS with a scalable microkernel and
sophisticated networking facilities - like TCP/IP networking across various media.
The open architecture provides efficient support of PC-based architectures. Flexible, intertask com-
munication, µs interrupt handling, POSIX 1003.1b real-time extensions, fast and flexible I/O sys-
tem etc. are some of the many key features.
1.36 OS-9 x86
Microware’s real-time operating system has a track record that has been proved in the industrial/
embedded market and has continued to provide reliable intelligence to sophisticated applica-
tions. OS-9 x86’s flexibility, modularity and reliability in conjunction with a rich driver structure
allow its use in I/O intensive applications.
1.37 QNX
This solution ports the Win32 API to a QNX kernel. The Win32 API aims to define a standard for
developing open systems applications that are optimized to run on ‘Wintel’ platforms. This oper-
ating system evolves around a small microkernel RTOS that produces a protected-mode, POSIX-
certified API. Being fully modular and scalable, this technology creates the smallest footprint that
is beneficial to high-end server applications.
1.38 Jbed
Esmertec’s Jbed is a new generation of real-time operating system. Java-based innovation provides
unprecedented safety and ease of use without compromising resource efficiency (native processor
speed) or hard real-time performance. In addition, advanced features are implemented such as
modularity, hot updates, deadline-driven scheduling admission testing as well as a fast and pro-
ductive cross-development.

©2002 Inova Computers GmbHPage1-10 Doc. PD00581013.004
Product Overview ICP-PIII
1.4 Hardware
1.41 Block Diagram
Figure 1.41 Block Diagram
This block diagram is applicable to all Inova’s PIII-based CPUs. Components and/or functionality
may change without notice. An extra PCI load can be attached to the on-board 80-pin header. An
open specification is available allowing developers to manufacture their own PCI device.
USB
PS/2
COM 1/2
LPT 1 PCI2ISA Power
EIDE
FDC
IRQ
8/16 MByte
SGRAM
North Bridge
Intel 82443BX
RTC
128/384 MByte
Piggyback
Extension
SDRAM (ECC)
128 MByte
On-Board
ISA Bus
Floppy
Hard-Disk
(2 Channels. 4 Devices)
South
Bridge
ALi 1543C
10/100 Mbit/s
Ethernet
400 Mbit/s
FireWire
VGA
GigaST
)
R
PanelLink
TFT
2x USB
Mouse/Key.
COM1/2
LPT1
FLASH (BIOS)
PC100
AGP
PCI/PCI Bridge
System Slot
or
Peripheral Device
PCI Bus
TSB 12LV23
Intel 82559 Ethernet
Intel 82559 Ethernet
PL
Silicon Motion
Lynx3DM
or
ATI Radeon VE
Graphics
10/100 Mbit/s
Ethernet
Piggyback
Up to 512 MByte
M-Systems
Disk-On-Chip™
x86 ‘processor
Pentium III,
Celeron
Socket
FC-PGA 370
or
BGA2 (Mobile)