Intel PENTIUM P6000 SPECIFICATION 20 User manual

Document Number: 323873-002
Intel® Pentium® P6000 and U5000
Mobile Processor Series
Datasheet
This is volume 1 of 2. Refer to Document 322813 for Volume 2
June 2010

2Datasheet
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Datasheet 3
Contents
1 Features Summary ....................................................................................................8
1.1 Introduction .......................................................................................................8
1.2 Processor Feature Details ................................................................................... 10
1.2.1 Supported Technologies .......................................................................... 10
1.3 Interfaces......................................................................................................... 10
1.3.1 System Memory Support ......................................................................... 10
1.3.2 PCI Express* ......................................................................................... 11
1.3.3 Direct Media Interface (DMI).................................................................... 12
1.3.4 Platform Environment Control Interface (PECI) ........................................... 13
1.3.5 Intel® HD Graphics Controller.................................................................. 13
1.3.6 Embedded DisplayPort* (eDP*) ................................................................ 14
1.3.7 Intel® Flexible Display Interface (Intel® FDI) ............................................ 14
1.4 Power Management Support ............................................................................... 14
1.4.1 Processor Core....................................................................................... 14
1.4.2 System ................................................................................................. 14
1.4.3 Memory Controller.................................................................................. 15
1.4.4 PCI Express* ......................................................................................... 15
1.4.5 DMI ...................................................................................................... 15
1.4.6 Integrated Graphics Controller ................................................................. 15
1.5 Thermal Management Support ............................................................................ 15
1.6 Package ........................................................................................................... 15
1.7 Terminology ..................................................................................................... 16
1.8 Related Documents............................................................................................ 18
2Interfaces................................................................................................................ 19
2.1 System Memory Interface................................................................................... 19
2.1.1 System Memory Technology Supported ..................................................... 19
2.1.2 System Memory Timing Support............................................................... 20
2.1.3 System Memory Organization Modes ......................................................... 20
2.1.4 Rules for Populating Memory Slots ............................................................ 22
2.1.5 Technology Enhancements of Intel®Fast Memory Access (Intel®FMA).......... 23
2.1.6 DRAM Clock Generation........................................................................... 23
2.1.7 System Memory Pre-Charge Power Down Support Details ............................ 23
2.2 PCI Express Interface......................................................................................... 24
2.2.1 PCI Express Architecture ......................................................................... 24
2.2.2 PCI Express Configuration Mechanism ....................................................... 26
2.2.3 PCI Express Ports and Bifurcation ............................................................. 26
2.3 DMI................................................................................................................. 27
2.3.1 DMI Error Flow....................................................................................... 27
2.3.2 Processor/PCH Compatibility Assumptions.................................................. 27
2.3.3 DMI Link Down ...................................................................................... 27
2.4 Intel® HD Graphics Controller............................................................................. 28
2.4.1 3D and Video Engines for Graphics Processing ............................................ 28
2.4.2 Integrated Graphics Display Pipes............................................................. 31
2.4.3 Intel Flexible Display Interface ................................................................. 33
2.5 Platform Environment Control Interface (PECI) ...................................................... 33
2.6 Interface Clocking ............................................................................................. 34
2.6.1 Internal Clocking Requirements ................................................................ 34

4Datasheet
3 Technologies............................................................................................................35
3.1 Intel Graphics Dynamic Frequency .......................................................................35
4 Power Management .................................................................................................36
4.1 ACPI States Supported .......................................................................................36
4.1.1 System States........................................................................................36
4.1.2 Processor Core/Package Idle States...........................................................36
4.1.3 Integrated Memory Controller States .........................................................37
4.1.4 PCIe Link States .....................................................................................37
4.1.5 DMI States ............................................................................................37
4.1.6 Integrated Graphics Controller States ........................................................37
4.1.7 Interface State Combinations ...................................................................38
4.2 Processor Core Power Management ......................................................................38
4.2.1 Enhanced Intel SpeedStep® Technology....................................................39
4.2.2 Low-Power Idle States.............................................................................39
4.2.3 Requesting Low-Power Idle States ............................................................41
4.2.4 Core C-states .........................................................................................42
4.2.5 Package C-States ...................................................................................43
4.3 IMC Power Management .....................................................................................46
4.3.1 Disabling Unused System Memory Outputs.................................................47
4.3.2 DRAM Power Management and Initialization ...............................................47
4.4 PCIe Power Management ....................................................................................48
4.5 DMI Power Management .....................................................................................49
4.6 Integrated Graphics Power Management ...............................................................49
4.6.1 Intel®Display Power Saving Technology 5.0 (Intel®DPST 5.0).....................49
4.6.2 Graphics Render C-State .........................................................................49
4.6.3 Graphics Performance Modulation Technology.............................................49
4.6.4 Intel®Smart 2D Display Technology (Intel®S2DDT)...................................49
4.7 Thermal Power Management ...............................................................................50
5 Thermal Management ..............................................................................................51
5.1 Thermal Design Power and Junction Temperature...................................................51
5.1.1 Intel Graphics Dynamic Frequency ............................................................51
5.1.2 Intel Graphics Dynamic Frequency Thermal Design Considerations and
Specifications .........................................................................................52
5.1.3 Idle Power Specifications .........................................................................54
5.1.4 Intelligent Power Sharing Control Overview ................................................54
5.1.5 Component Power Measurement/Estimation Error .......................................55
5.2 Thermal Management Features............................................................................56
5.2.1 Processor Core Thermal Features ..............................................................56
5.2.2 Integrated Graphics and Memory Controller Thermal Features ......................62
5.2.3 Platform Environment Control Interface (PECI) ...........................................66
6 Signal Description....................................................................................................68
6.1 System Memory Interface ...................................................................................69
6.2 Memory Reference and Compensation ..................................................................71
6.3 Reset and Miscellaneous Signals ..........................................................................72
6.4 PCI Express Graphics Interface Signals .................................................................73
6.5 Embedded DisplayPort (eDP)...............................................................................74
6.6 Intel Flexible Display Interface Signals..................................................................74
6.7 DMI .................................................................................................................75
6.8 PLL Signals .......................................................................................................75
6.9 TAP Signals.......................................................................................................76

Datasheet 5
6.10 Error and Thermal Protection .............................................................................. 77
6.11 Power Sequencing ............................................................................................. 78
6.12 Processor Power Signals ..................................................................................... 79
6.13 Ground and NCTF .............................................................................................. 81
6.14 Processor Internal Pull Up/Pull Down.................................................................... 81
7 Electrical Specifications........................................................................................... 83
7.1 Power and Ground Pins ...................................................................................... 83
7.2 Decoupling Guidelines ........................................................................................ 83
7.2.1 Voltage Rail Decoupling........................................................................... 83
7.3 Processor Clocking (BCLK, BCLK#) ...................................................................... 83
7.3.1 PLL Power Supply ................................................................................... 84
7.4 Voltage Identification (VID) ................................................................................ 84
7.5 Reserved or Unused Signals................................................................................ 88
7.6 Signal Groups ................................................................................................... 88
7.7 Test Access Port (TAP) Connection....................................................................... 91
7.8 Absolute Maximum and Minimum Ratings ............................................................. 92
7.9 Storage Conditions Specifications ........................................................................ 92
7.10 DC Specifications............................................................................................... 93
7.10.1 Voltage and Current Specifications............................................................ 94
7.11 Platform Environmental Control Interface (PECI) DC Specifications......................... 101
7.11.1 DC Characteristics ................................................................................ 101
7.11.2 Input Device Hysteresis......................................................................... 102
8 Processor Pin and Signal Information.................................................................... 103
8.1 Processor Pin Assignments................................................................................ 103
8.2 Package Mechanical Information........................................................................ 177
Figures
Figure 1-1 Intel® Pentium® P6000 and U5000 Mobile Processor Series on the Calpella
Platform..................................................................................................9
Figure 2-2 Intel Flex Memory Technology Operation ................................................... 21
Figure 2-3 Dual-Channel Symmetric (Interleaved) and Dual-Channel
Asymmetric Modes ................................................................................. 22
Figure 2-4 PCI Express Layering Diagram ................................................................. 24
Figure 2-5 Packet Flow through the Layers ................................................................ 25
Figure 2-6 PCI Express Related Register Structures in the Processor ............................. 26
Figure 2-7 Integrated Graphics Controller Unit Block Diagram...................................... 28
Figure 2-8 Processor Display Block Diagram .............................................................. 31
Figure 4-9 Idle Power Management Breakdown of the Processor Cores.......................... 40
Figure 4-10 Thread and Core C-State Entry and Exit .................................................... 40
Figure 4-11 Package C-State Entry and Exit ................................................................ 45
Figure 5-12 Frequency and Voltage Ordering............................................................... 57
Figure 7-13 Active VCC and ICC Loadline (PSI# Asserted) .............................................. 95
Figure 7-14 Active VCC and ICC Loadline (PSI# Not Asserted) ........................................ 95
Figure 7-15 VAXG/IAXG Static and Ripple Voltage Regulation ........................................ 97
Figure 7-16 Input Device Hysteresis......................................................................... 102
Figure 8-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant).................. 104
Figure 8-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)................ 105
Figure 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant).................. 106
Figure 8-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)................ 107

6Datasheet
Figure 8-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant) .................................. 136
Figure 8-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant) ................................137
Figure 8-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant) ..................................138
Figure 8-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant) ................................ 139
Figure 8-25 rPGA Mechanical Package (Sheet 1 of 2) ................................................. 177
Figure 8-26 rPGA Mechanical Package (Sheet 2 of 2) .................................................. 178
Figure 8-27 BGA Mechanical Package (Sheet 1 of 2) ................................................... 179
Figure 8-28 BGA Mechanical Package (Sheet 2 of 2) ................................................... 180
Tables
Table 2-1 Supported SO-DIMM Module Configurations1..............................................19
Table 2-2 DDR3 System Memory Timing Support ......................................................20
Table 2-3 eDP/PEG Ball Mapping .............................................................................32
Table 2-4 Processor Reference Clocks ......................................................................34
Table 4-5 System States........................................................................................36
Table 4-6 Processor Core/Package State Support ......................................................36
Table 4-7 Integrated Memory Controller States .........................................................37
Table 4-8 PCIe Link States .....................................................................................37
Table 4-9 DMI States ............................................................................................37
Table 4-10 Integrated Graphics Controller States ........................................................37
Table 4-11 G, S and C State Combinations.................................................................38
Table 4-12 D, S, and C State Combination .................................................................38
Table 4-13 Coordination of Thread Power States at the Core Level ................................41
Table 4-14 P_LVLx to MWAIT Conversion ...................................................................41
Table 4-15 Coordination of Core Power States at the Package Level...............................44
Table 4-16 Targeted Memory State Conditions............................................................48
Table 5-17 Intel Pentium U5000 mobile processor series Dual-Core ULV Thermal Power
Specifications .........................................................................................53
Table 5-18 Intel Pentium P6000 mobile processor series Dual-Core SV Thermal Power
Specifications .........................................................................................54
Table 5-19 18 W Ultra Low Voltage (ULV) Processor Idle Power ....................................54
Table 5-20 35 W Standard Voltage (SV) Processor Idle Power.......................................54
Table 6-21 Signal Description Buffer Types ................................................................68
Table 6-22 Memory Channel A..................................................................................69
Table 6-23 Memory Channel B..................................................................................70
Table 6-24 Memory Reference and Compensation .......................................................71
Table 6-25 Reset and Miscellaneous Signals ...............................................................72
Table 6-26 PCI Express Graphics Interface Signals ......................................................73
Table 6-27 Intel® Flexible Display Interface...............................................................74
Table 6-28 DMI - Processor to PCH Serial Interface .....................................................75
Table 6-29 PLL Signals ............................................................................................75
Table 6-30 TAP Signals............................................................................................76
Table 6-31 Error and Thermal Protection....................................................................77
Table 6-32 Power Sequencing ..................................................................................78
Table 6-33 Processor Power Signals ..........................................................................79
Table 6-34 Ground and NCTF ...................................................................................81
Table 6-35 Processor Internal Pull Up/Pull Down .........................................................81
Table 7-36 Voltage Identification Definition ................................................................84
Table 7-37 Market Segment Selection Truth Table for MSID[2:0] ..................................87
Table 7-38 Signal Groups1.......................................................................................88
Table 7-39 Processor Absolute Minimum and Maximum Ratings ....................................92

Datasheet 7
Table 7-40 Storage Condition Ratings ....................................................................... 93
Table 7-41 Processor Core (VCC) Active and Idle Mode DC Voltage and Current
Specifications......................................................................................... 94
Table 7-42 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications..... 96
Table 7-43 Processor Graphics VID based (VAXG) Supply DC Voltage and Current
Specifications......................................................................................... 97
Table 7-44 DDR3 Signal Group DC Specifications ........................................................ 98
Table 7-45 Control Sideband and TAP Signal Group DC Specifications............................ 99
Table 7-46 PCI Express DC Specifications ................................................................ 100
Table 7-47 eDP DC Specifications ........................................................................... 101
Table 7-48 PECI DC Electrical Limits ....................................................................... 102
Table 8-49 rPGA988A Processor Pin List by Pin Number ............................................. 108
Table 8-50 rPGA988A Processor Pin List by Pin Name ................................................ 122
Table 8-51 BGA1288 Processor Ball List by Ball Name ............................................... 140
Table 8-52 BGA1288 Processor Ball List by Ball Number ............................................ 158

8Datasheet
Revision History
§
Revision
Number Description Revision
Date
001 • Initial release May 2010
002 • Added Pentium P6000 sku information June 2010

Datasheet 9
Features Summary
1 Features Summary
1.1 Introduction
Intel® Pentium® P6000 and U5000 Mobile Processor Series is the next generation of
64-bit, multi-core mobile processor built on 32-nanometer process technology. Based
on the low-power/high-performance Nehalem micro-architecture, the processor is
designed for a two-chip platform as opposed to the traditional three-chip platforms
(processor, GMCH, and ICH). The two-chip platform consists of a processor and the
Platform Controller Hub (PCH) and enables higher performance, lower cost, easier
validation, and improved x-y footprint. The PCH may also be referred to as Mobile
Intel® 5 Series Chipset (formerly Ibex Peak-M). Intel® Pentium® P6000 and U5000
Mobile Processor Series is designed for the Calpella platform and is offered in rPGA988A
and BGA1288 package respectively.
Included in this family of processors is Intel® HD graphics and memory controller die
on the same package as the processor core die. This two-chip solution of a processor
core die with an integrated graphics and memory controller die is known as a multi-chip
package (MCP) processor.
Note:
1. Throughout this document, Intel® Pentium® P6000 and U5000 Mobile Processor
Series is referred to as processor.
2. Throughout this document, Intel® HD graphics is referred as integrated graphics.
3. Integrated graphics and memory controller die is built on 45-nanometer process
technology
4. Intel® Pentium® P6000 and U5000 Mobile Processor Series is not Intel® vPro™
eligible

Features Summary
10 Datasheet
Figure 1-1. Intel® Pentium® P6000 and U5000 Mobile Processor Series on the Calpella
Platform
Processor
Discrete Graphics
(PEG)
Analog CRT
Gigabit
Network Connection
USB 2.0
Intel®HD Audio
FWH
Super I/O
PCI
Serial ATA
Mobile Intel® 5 Series Chipset
PCH
DDR3 SO-DIMMs
PCI Express* x16
8 PCI Express* x1
Ports
(2.5 GT/s)
14 Ports
PCI
6 Ports
3 Gb/s
SPI
Digital Display x 3
Intel® Flexible
Display Interface
PCI Express*
WiMax
SPI Flash
LPC
SMBUS 2.0
PECI
GPIO
OR
GPU, Memory
Controller
Dual Core
Processor
800/1066 MT/s
2 Channels
1 SO-DIMM / Channel
DMI2
(x4)
Dual Channel NAND
Interface
LVDS Flat Panel
Intel®
Management
Engine
WiFi
Controller Link 1
Embedded
DisplayPort* (eDP)
PCI Express x 1

Datasheet 11
Features Summary
1.2 Processor Feature Details
•Two execution cores
•A 32-KB instruction and 32-KB data first-level cache (L1) for each core
•A 512-KB shared instruction/data second-level cache (L2), 256-KB for each core
•Up to 3-MB shared instruction/data third-level cache (L3), shared among all cores
1.2.1 Supported Technologies
•Intel® 64 architecture
•Execute Disable Bit
•Processor Context Identifier (PCID) (U5400 processor only)
Note: Please refer to the Intel® Pentium® P6000 and U5000 Mobile Processor Series
Specification Update for feature support details
1.3 Interfaces
1.3.1 System Memory Support
•One or two channels of DDR3 memory with a maximum of one SO-DIMM per
channel
•Single- and dual-channel memory organization modes
•Data burst length of eight for all memory organization modes
•Memory DDR3 data transfer rates of 800 MT/s (SV/ULV) and 1066 MT/s (SV)
•64-bit wide channels
•DDR3 I/O Voltage of 1.5 V
•Non-ECC, unbuffered DDR3 SO-DIMMs only
•Theoretical maximum memory bandwidth of:
— 12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s
•1-Gb, and 2-Gb DDR3 DRAM technologies are supported for x8 and x16 devices.
•Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,
assuming dual-channel mode with two x8, double-sided, un-buffered, non-ECC,
SO-DIMM memory configuration.
•Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
•Memory organizations:
— Single-channel modes
— Dual-channel modes - Intel® Flex Memory Technology:

Features Summary
12 Datasheet
Dual-channel symmetric (Interleaved)
Dual-channel asymmetric
•Command launch modes of 1n/2n
•Partial Writes to memory using Data Mask (DM) signals
•On-Die Termination (ODT)
•Intel® Fast Memory Access (Intel® FMA):
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
1.3.2 PCI Express*
•The Processor PCI Express ports are fully compliant to the PCI Express Base
Specification Revision 2.0.
— One 16-lane PCI Express* port intended for graphics attach.
•Gen1 (2.5 GT/s) PCI Express* frequency is supported.
•Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
•Maximum theoretical bandwidth on interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
•Hierarchical PCI-compliant configuration mechanism for downstream devices.
•Traditional PCI style traffic (asynchronous snooped, PCI ordering).
•PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as “extended configuration space”.
•PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
•Automatic discovery, negotiation, and training of link out of reset.
•Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
•Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— DMI -> PCI Express Port 0
•64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
•64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are

Datasheet 13
Features Summary
non-zero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
•Re-issues configuration cycles that have been previously completed with the
Configuration Retry status.
•PCI Express reference clock is 100-MHz differential clock buffered out of system
clock generator.
•Power Management Event (PME) functions.
•Static lane numbering reversal
— Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification.
— PCI Express 1x16 configuration
Normal (1x16): PEG_RX[15:0]; PEG_TX[15:0]
Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15]
•Supports Half Swing “low-power/low-voltage” mode.
•Message Signaled Interrupt (MSI and MSI-X) messages
•PEG Lanes shared with Embedded DisplayPort* (see eDP, Section 1.3.6).
•Polarity inversion
1.3.3 Direct Media Interface (DMI)
•Compliant to Direct Media Interface second generation (DMI2).
•Four lanes in each direction.
•2.5 GT/s point-to-point DMI interface to PCH is supported.
•Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of
250 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
•Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
•Shares 100-MHz PCI Express reference clock.
•64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
•64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
•Supports the following traffic types to or from the PCH:
— DMI -> PCI Express Port 0 write traffic
—DMI->DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)

Features Summary
14 Datasheet
— Processor core -> DMI
•APIC and MSI interrupt messaging support:
— Message Signaled Interrupt (MSI and MSI-X) messages
•Downstream SMI, SCI and SERR error indication.
•Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
•DC coupling – no capacitors between the processor and the PCH.
•Polarity inversion.
•PCH end-to-end lane reversal across the link.
•Supports Half Swing “low-power/low-voltage.”
1.3.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH).
1.3.5 Intel® HD Graphics Controller
•The integrated graphics controller contains a refresh of the fifth generation graphics
core
•Intel® Dynamic Video Memory Technology (Intel® DVMT) support
•Intel® Graphics Performance Modulation Technology (Intel® GPMT)
•Intel® Smart 2D Display Technology (Intel® S2DDT)
•Intel® Clear Video Technology
— MPEG2 Hardware Acceleration
— WMV9/VC1 Hardware Acceleration
— AVC Hardware Acceleration
—ProcAmp
— Advanced Pixel Adaptive De-interlacing
— Sharpness Enhancement
— De-noise Filter
— High Quality Scaling
— Film Mode Detection (3:2 pull-down) and Correction
—Intel®TVWizard
•12 EUs
•Dedicated analog and digital display ports are supported through the Intel 5 Series
Chipset PCH

Datasheet 15
Features Summary
1.3.6 Embedded DisplayPort* (eDP*)
•Shared with PCI Express Graphics port
•Shared on upper four logical lanes, after any lane reversal
•eDP[3:0] map to PEG[12:15] (non-reversed)
•eDP[3:0] map to PEG[3:0] (reversed)
•Concurrent eDP and PEG x1 supported
1.3.7 Intel® Flexible Display Interface (Intel® FDI)
•Carries display traffic from the integrated graphics controller in the processor to the
legacy display connectors in the PCH.
•Based on DisplayPort standard.
•Two independent links - one for each display pipe.
•Four unidirectional downstream differential transmitter pairs:
— Scalable down to 3X, 2X, or 1X based on actual display bandwidth requirements
— Fixed frequency 2.7 GT/s data rate
•Two sideband signals for Display synchronization:
— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
•One Interrupt signal used for various interrupts from the PCH:
— FDI_INT signal shared by both Intel FDI Links
•PCH supports end-to-end lane reversal across both links.
1.4 Power Management Support
1.4.1 Processor Core
•Full support of ACPI C-states as implemented by the following processor C-states:
— Ultra low voltage supports C0, C1, C1E, C3, Deep Power Down Technology (code
named C6)
— Standard voltage supports C0, C1, C1E, C3
•Enhanced Intel SpeedStep® Technology
1.4.2 System
•S0, S3, S4, S5

Features Summary
16 Datasheet
1.4.3 Memory Controller
•Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))
•Dynamic power-down
1.4.4 PCI Express*
•L0s and L1 ASPM power management capability
1.4.5 DMI
•L0s and L1 ASPM power management capability
1.4.6 Integrated Graphics Controller
•Intel Smart 2D Display Technology (Intel S2DDT)
•Intel® Display Power Saving Technology (Intel® DPST)
•Graphics Render C-State (RC6)
1.5 Thermal Management Support
•Digital Thermal Sensor
•Adaptive Thermal Monitor
•THERMTRIP# and PROCHOT# support
•On-Demand Mode
•Open and Closed Loop Throttling
•Memory Thermal Throttling
•External Thermal Sensor (TS-on-DIMM and TS-on-Board)
•Render Thermal Throttling
•Fan speed control with DTS
1.6 Package
•The Intel® Pentium® P6000 and U5000 Mobile Processor Series is available is
available on:
— A 37.5 x 37.5 mm rPGA package (rPGA988A) (Standard Voltage only)
— A 34 x 28 mm BGA package (BGA1288) (Ultra Low voltage only)

Datasheet 17
Features Summary
1.7 Terminology
Term Description
BLT Block Level Transfer
CRT Cathode Ray Tube
DDR3 Third-generation Double Data Rate SDRAM memory technology
DP DisplayPort*
DMA Direct Memory Access
DMI Direct Media Interface
DTS Digital Thermal Sensor
ECC Error Correction Code
eDP* Embedded DisplayPort*
Intel® DPST Intel®Display Power Saving Technology
Enhanced Intel
SpeedStep®
Tec hn olo gy
Technology that provides power management capabilities to laptops.
Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or
non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some
classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the
Intel® 64 and IA-32 Architectures Software Developer's Manuals for
more detailed information.
(G)MCH Legacy component - Graphics Memory Controller Hub
GPU Graphics Processing Unit
ICH The legacy I/O Controller Hub component that contains the main PCI
interface, LPC interface, USB2, Serial ATA, and other I/O functions. It
communicates with the legacy (G)MCH over a proprietary interconnect
called DMI.
IMC Integrated Memory Controller
Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture
ITPM Integrated Trusted Platform Module
IOV I/O Virtualization
LCD Liquid Crystal Display
LVDS Low Voltage Differential Signaling. A high speed, low power data
transmission standard used for display connections to LCD panels.
MCP Multi-Chip Package.
NCTF Non-Critical to Function. NCTF locations are typically redundant
ground or non-critical reserved, so the loss of the solder joint
continuity at end of life conditions will not affect the overall product
functionality.
Nehalem Intel’s 45-nm processor design, follow-on to the 45-nm Penryn design.

Features Summary
18 Datasheet
PCH Platform Controller Hub. The new, 2009 chipset with centralized
platform capabilities including the main I/O interfaces along with
display connectivity, audio features, power management,
manageability, security and storage features. The PCH may also be
referred to using the name (Mobile) Intel® 5 Series Chipset
PECI Platform Environment Control Interface.
PEG PCI Express* Graphics. External Graphics using PCI Express
Architecture. A high-speed serial interface whose configuration is
software compatible with the existing PCI specifications.
Processor The 64-bit, single-core or multi-core component (package).
Processor Core The term “processor core” refers to Si die itself which can contain
multiple execution cores. Each execution core has an instruction
cache, data cache, and 256-KB L2 cache. All execution cores share the
L3 cache.
Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring
ECC. These devices are usually, but not always, mounted on a single
side of a SO-DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
Storage Conditions A non-operational state. The processor may be installed in a platform,
in a tray, or loose. Processors may be sealed in packaging or exposed
to free air. Under these conditions, processor landings should not be
connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a
device removed from packaging material) the processor must be
handled in accordance with moisture sensitivity labeling (MSL) as
indicated on the packaging material.
TAC Thermal Averaging Constant.
TDP Thermal Design Power.
VCC Processor core power supply.
VSS Processor ground.
VAXG Graphics core power supply.
VTT L3 shared cache, memory controller, and processor I/O power rail.
VDDQ DDR3 power rail.
VLD Variable Length Decoding.
x1 Refers to a Link or Port with one Physical Lane.
x4 Refers to a Link or Port with four Physical Lanes.
x8 Refers to a Link or Port with eight Physical Lanes.
x16 Refers to a Link or Port with sixteen Physical Lanes.
Term Description

Datasheet 19
Features Summary
1.8 Related Documents
§
Document Document Number/
Location
Public Specifications
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/
specifications
PCI Express Base Specification 2.0 http://www.pcisig.com
DDR3 SDRAM Specification http://www.jedec.org
DisplayPort Specification http://www.vesa.org
Intel® 64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/
products/processor/
manuals/index.htm
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669

Interfaces
20 Datasheet
2 Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two,
independent, 64-bit wide channels each accessing one SO-DIMM. It supports a
maximum of one, unbuffered non-ECC DDR3 SO-DIMM per-channel thus allowing up to
two device ranks per-channel.
DDR3 Data Transfer Rates:
— 800 MT/s (PC3-6400) and 1066 MT/s (PC3-8500)
•DDR3 SO-DIMM Modules:
— Raw Card A – double-sided x16 unbuffered non-ECC
— Raw Card B – single-sided x8 unbuffered non-ECC
— Raw Card C – single-sided x16 unbuffered non-ECC
— Raw Card D – double-sided x8 (stacked) unbuffered non-ECC
— Raw Card F – double-sided x8 (planar) unbuffered non-ECC
•DDR3 DRAM Device Technology:
— Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16
and x8 devices. There is no support for memory modules with different
technologies or capacities on opposite sides of the same memory module. If one
side of a memory module is populated, the other side is either identical or
empty.
Table 2-1. Supported SO-DIMM Module Configurations1
Raw
Card
Version
DIMM
Capacity
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of Row/
Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
A 1 GB 1 Gb 64 M x 16 8 2 13/10 8 8K
A 2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K
B 1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K
B 2 GB 2 Gb 256 M x 8 8 1 15/10 8 8K
C 512 MB 1 Gb 64 M x 16 4 1 13/10 8 8K
C 1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K