Intel 80219 Technical manual

Intel®80219 General Purpose PCI
Processor
Specification Update
July 2004
Notice: The Intel®80219 General Purpose PCI Processor (80219) may contain design defects or
errors known as errata that may cause the product to deviate from published specifications.
Current characterized errata are documented in this specification update.
Document Number: 274020-002

2Specification Update
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®80219 General Purpose PCI Processor may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Specification Update 3
Intel®80219 General Purpose PCI Processor
Contents
Revision History......................................................................................... 5
Preface....................................................................................................... 6
Summary Table of Changes....................................................................... 7
Identification Information...........................................................................11
Core Errata .............................................................................................. 13
Non-Core Errata....................................................................................... 20
Specification Changes ............................................................................. 24
Specification Clarifications....................................................................... 26
Documentation Changes ......................................................................... 29

4Specification Update
Intel®80219 General Purpose PCI Processor
This Page Left Intentionally Blank

Specification Update 5
Intel®80219 General Purpose PCI Processor
Revision History
Revision History
Date Version Description
July 2004 002 Added Specification Clarification 7.
November 2003 001 Initial Release.

6Specification Update
Intel®80219 General Purpose PCI Processor
Preface
Preface
This document is an update to the specifications contained in the Affected Documents/Related
Documents table below. This document is a compilation of device and documentation errata,
specification clarifications and changes.It is intended for hardware system manufacturers and
software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification update and are
no longer published in other documents.
This document may also contain information that was not previously published.
Affected Documents/Related Documents
Nomenclature
Errata are design defects or errors. These may cause the Intel®80219 General Purpose PCI
Processor1behavior to deviate from published specifications. Hardware and software designed to
be used with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications. These changes
will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These will be incorporated in any new release of the specification.
Note: Errata remain in the specification update throughout the product life cycle, or until a particular
stepping is no longer commercially available. Under these circumstances, errata removed from the
specification update are archived and available upon request. Specification changes, specification
clarifications and documentation changes are removed from the specification update when the
appropriate changes are made to the appropriate product specification or user documentation
(datasheets, manuals, etc.).
Title Order
Intel®80219 General Purpose PCI Processor Developer’s Manual 274017
Intel®80219 General Purpose PCI Processor Advance Information Datasheet 274018
Intel®80219 General Purpose PCI Processor Design Guide 274019
1. ARM* architecture compliant.

Specification Update 7
Intel®80219 General Purpose PCI Processor
Summary Table of Changes
Summary Table of Changes
The following table indicates the errata, specification changes, specification clarifications, or
documentation changes which apply to the Intel®80219 General Purpose PCI Processor product.
Intel may fix some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted.This table uses the
following notations:
Codes Used in Summary Table
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change does not
apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or
modified from the previous version of the document.

8Specification Update
Intel®80219 General Purpose PCI Processor
Summary Table of Changes
Core Errata
No. Steppings Page Status Errata
A-0
1X13 NoFix Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification
2X13 NoFix Drain Is Not Flushed Correctly when Stalled in the Pipeline
3X14 NoFix Undefined Data Processing-‘like’ Instructions are Interpreted as an MSR Instruction
4X14 NoFix Debug Unit Synchronization with the TXRXCTRL Register
5X14 NoFix Extra Circuitry Is Not JTAG Boundary Scan Compliant
6X15 NoFix Incorrect Decode of Unindexed Mode, Using Addressing Mode 5, Can Corrupt Protected
Registers
7X15 NoFix Load Immediately Following a DMM Flush Entry is Also Flushed
8X15 NoFix Trace Buffer Does Not Operate Below 1.3 V
9X15 NoFix Data Cache Unit Can Stall for a Single Cycle
10 X16 NoFix Aborted Store that Hits the Data Cache May Mark Writeback Data As Dirty
11 X17 NoFix Performance Monitor Unit Event 0x1 Can Be Incremented Erroneously by Unrelated
Events
12 X17 NoFix In Special Debug State, Back-to-Back Memory Operations Where the First Instruction
Aborts May Cause a Hang
13 X18 NoFix Accesses to the CP15 ID register with opcode2 > 0b001 returns unpredictable values
14 X18 NoFix Disabling and re-enabling the MMU can hang the core or cause it to execute the wrong
code
15 X19 NoFix Updating the JTAG parallel register requires an extra TCK rising edge

Specification Update 9
Intel®80219 General Purpose PCI Processor
Summary Table of Changes
Non-Core Errata
No. Steppings Page Status Errata
A-0
1X20 NoFix The ATU Returns Invalid Data for the DWORD that Target Aborted from the MCU when
Using 32-Bit Memory, ECC Enabled and in PCI Mode
2X20 NoFix PBI Issue When Using 16-bit PBI Transactions in PCI Mode
3X21 NoFix MCU Pointers are Incorrect following a Restoration from a Power Fail
4X21 NoFix PMU Does Not Account for when the Arbiter Deasserts GNT# One Cycle before
FRAME#
5X21 NoFix Lost Data During Bursts of Large Number of Partials with 32-bit ECC Memory
6X22 NoFix The MTTR1 (Core Multi-Transaction Timer) is not operating due to improper behavior of
the core internal bus request signal (REQ#)
7X22 NoFix The MCU supports a page size of 2 Kbytes for 64-bit mode
8X23 NoFix Vih Minimum Input High Voltage (Vih) level for the PCI pins

10 Specification Update
Intel®80219 General Purpose PCI Processor
Summary Table of Changes
Documentation Changes
Specification Changes
No. Steppings Page Specification Changes
A-0
1X24 Signal NC2 was renamed to P_BMI (AE23). New function added to signal P_BMI.
Specification Clarifications
No. Steppings Page Status Specification Clarifications
A-0
1X26 NoFix The Intel® 80219 general purpose PCI processor is compliant with the PCI Local Bus
Specification, Revision 2.2 but it is not compliant with PCI Local Bus Specification,
Revision 2.3
2X26 NoFix Modifications to the Hot-Debug procedure are necessary for the Intel® 80219 general
purpose PCI processor when flat memory mapping is not used (Virtual Address =
Physical Address)
3X27 Doc BAR0 Configuration When Using the Messaging Unit (MU)
4X27 Doc Reading Unpopulated SDRAM Memory Banks
5X27 Doc 32-bit Writes-to-Unaligned 64-bit Addresses, are Promoted to 64-bit Aligned Writes
6X28 Doc In-order Delivery not guaranteed for data blocks described by a single DMA descriptor
7X28 Doc Writing to reserved registers can cause unexpected behavior
No. Document Revision Page Status Documentation Changes
None for this revision of this specification update.