Intel RH80536GC0332M - Pentium M 1.8 GHz Processor User manual

Intel® Pentium® M Processor on
90 nm Process with 2-MB L2
Cache
Datasheet
January 2006
Document Number: 302189-008

2Datasheet
IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
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RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®Pentium®M processor on 90 nm process with 2-MB L2 cache may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across
different processor families. See www.intel.com/products/processor_number for details.
Intel, Pentium, Celeron, MMX, Intel SpeedStep andthe Intel logo aretrademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004—2006, Intel Corporation. All rights reserved

Datasheet 3
Contents
1 Introduction....................................................................................................................................7
1.1 Terminology..........................................................................................................................9
1.2 References ...........................................................................................................................9
2 Low Power Features....................................................................................................................11
2.1 Clock Control and Low Power States .................................................................................11
2.1.1 Normal State..........................................................................................................11
2.1.2 AutoHALT Power-Down State ...............................................................................11
2.1.3 Stop-Grant State....................................................................................................12
2.1.4 HALT/Grant Snoop State.......................................................................................12
2.1.5 Sleep State ............................................................................................................13
2.1.6 Deep Sleep State...................................................................................................13
2.1.7 Deeper Sleep State ...............................................................................................14
2.2 Enhanced Intel SpeedStep®Technology ...........................................................................14
2.3 Front Side Bus Low Power Enhancements ........................................................................15
2.4 Processor Power Status Indicator (PSI#) Signal ................................................................15
3 Electrical Specifications .............................................................................................................17
3.1 Power and Ground Pins......................................................................................................17
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................17
3.2 Voltage Identification ..........................................................................................................17
3.3 Catastrophic Thermal Protection........................................................................................18
3.4 Signal Terminations and Unused Pins................................................................................19
3.5 FSB Frequency Select Signals (BSEL[1:0]) .......................................................................19
3.6 FSB Signal Groups.............................................................................................................19
3.7 CMOS Signals ....................................................................................................................20
3.8 Maximum Ratings...............................................................................................................21
3.9 Processor DC Specifications ..............................................................................................21
4 Package Mechanical Specifications and Pin Information .......................................................47
4.1 Processor Pinout and Pin List.............................................................................................54
4.2 Alphabetical Signals Reference..........................................................................................70
5 Thermal Specifications and Design Considerations................................................................77
5.1 Thermal Specifications .......................................................................................................80
5.1.1 Thermal Diode .......................................................................................................80
5.1.2 Thermal Diode Offset.............................................................................................81
5.1.3 Intel®Thermal Monitor...........................................................................................82

4Datasheet
Figures
2-1 Clock Control States...................................................................................................................11
3-1 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#A)............................31
3-2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#A) ...................32
3-3 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#B)............................33
3-4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#B) ...................34
3-5 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#C) ...........................35
3-6 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#C)...................36
3-7 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#D) ...........................37
3-8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#D)...................38
3-9 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#E)............................39
3-10Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#E) ...................40
3-11Active VCC and ICC Load Line ..................................................................................................43
3-12Deep Sleep VCC and ICC Load Line.........................................................................................44
4-1 Micro-FCPGA Package Top and Bottom Isometric Views .........................................................47
4-2 Micro-FCPGA Package - Top and Side Views...........................................................................48
4-3 Micro-FCPGA Package - Bottom View.......................................................................................49
4-4 Micro-FCBGA Package Top and Bottom Isometric Views .........................................................51
4-5 Micro-FCBGA Package Top and Side Views .............................................................................52
4-6 Micro-FCBGA Package Bottom View.........................................................................................54
4-7 The Coordinates of the Processor Pins as Viewed from the Top of the Package......................55

Datasheet 5
Tables
1-1 References ...................................................................................................................................9
3-1 Voltage Identification Definition ..................................................................................................18
3-2 FSB Pin Groups..........................................................................................................................20
3-3 Processor DC Absolute Maximum Ratings.................................................................................21
3-4 Voltage and Current Specifications - Standard Voltage Processors ..........................................22
3-5 Voltage and Current Specifications - Low Voltage Processors ..................................................24
3-6 Voltage and Current Specifications - Ultra Low Voltage Processors..........................................26
3-7 Voltage and Current Specifications (Continued).........................................................................28
3-8 Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#A........................31
3-9 Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#A...............32
3-10Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#B........................33
3-11Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#B...............34
3-12Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#C........................35
3-13Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#C...............36
3-14Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#D........................37
3-15Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#D...............38
3-16Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#E........................39
3-17Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#E...............40
3-18Voltage Tolerances for the Intel®Pentium®M Processor LV (Active State)..............................41
3-19Voltage Tolerances for the Intel®Pentium®M Processor LV (Deep Sleep State).....................42
3-20Voltage Tolerances for the Intel®Pentium®M Processor ULV (Active State)............................42
3-21Voltage Tolerances for the Intel®Pentium®M Processor ULV (Deep Sleep State)...................43
3-22FSB Differential BCLK Specifications.........................................................................................44
3-23AGTL+ Signal Group DC Specifications.....................................................................................45
3-24CMOS Signal Group DC Specifications......................................................................................45
3-25Open Drain Signal Group DC Specifications..............................................................................46
4-1 Micro-FCPGA Package Dimensions...........................................................................................50
4-2 Micro-FCBGA Package Dimensions...........................................................................................53
4-3 Pin Listing by Pin Name..............................................................................................................57
4-4 Pin Listing by Pin Number ..........................................................................................................63
4-5 Signal Description.......................................................................................................................70
5-1 Power Specifications for the Intel®Pentium M Processor..........................................................78
5-2 Thermal Diode Interface.............................................................................................................81
5-3 Thermal Diode Specification.......................................................................................................81

6Datasheet
Revision History
§
Revision Description Date
001 Initial release of datasheet May 2004
002 Added Intel®Pentium®M processor 725 and 715 specifications June 2004
003
• Specifications of Intel®Pentium®M processor Low Voltage 738
and Ultra Low Voltage 733 & 723 added in chapter 3 and chapter
5.
• Chapter 2 section 2.1.3 - Missing Stop Grant State title added.
Description was previously merged with Auto Halt state section
and is unchanged.
• Table 4 - Max ratings specifications updated
July 2004
004 Added Intel®Pentium®M processor 765 specifications October 2004
005
• Added Intel®Pentium®M processor 753 and 758 specifications
• Added Execute Disable support feature and lead free SLI
(second layer interconnect) Micro-FCPGA packaging
information in chapter 1
• Added Table 3-20 AGTL + Signal Group Signal DC
Specifications
• Table 3-18 - Voltage Tolerances for Intel®Pentium®M
processor ULV (Deep Sleep State) updated
January 2005
006 • Added Intel®Pentium®M processor 778 specifications July 2005
007 Updated Intel® Pentium®M processor 753 and 733J specifications
for optimized VID July 2005
008 Added Intel®Pentium®M processor 773 specifications January 2006

Datasheet 7
Introduction
1Introduction
The Intel®Pentium®M processor based on 90 nm process technology featuring 2-MB L2 cache
and 400-MHz front side bus (FSB) is the next generation high- performance, low-power mobile
processor based on the Intel®Pentium®processor architecture.
Throughout this document, Intel Pentium M processor based on 90 nm technology featuring 2-MB
L2 cache and 400 MHz FSB will be referred to as Pentium M processor, or simply the processor,
including low voltage and ultra low voltage processors.
This document contains specifications for the Pentium M processors 765/ 755/ 745/ 735/ 725/ 715
Standard Voltage, 778/758/738 Low Voltage and 773/753/733J/733/723 Ultra Low Voltage.
Intel processor numbers are not a measure of performance. Processor numbers differentiate
features within each processor family, not across different processor families. See www.intel.com/
products/processor_number for details.
The following list provides some of the key features on this processor:
•Supports Intel®Architecture with Dynamic Execution
•On-die, primary 32-KB instruction cache and 32-KB write-back data cache
•On-die, 2 MB second level cache with Advanced Transfer Cache Architecture
•Way set associativity and ECC (Error Correcting Code) support
•Data Prefetch Logic
•Streaming SIMD extensions 2 (SSE2)
•400 MHz, source-synchronous FSB
•Advanced power management features including Enhanced Intel SpeedStep®technology
•Micro-FCPGA and Micro-FCBGA packaging technologies
•Manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect.
•Support for MMX™ technology and Internet Streaming SIMD instructions
•The processor’s data prefetch logic fetches data to the L2 cache before L1 cache requests
occurs, resulting in reduced bus cycle penalties and improved performance
•Micro-FCPGA and Micro-FCBGA packaging technologies, including lead free SLI (second
level interconnect) technology for the Micro-FCBGA package (for Pentium M processors 755,
745, 778, 758, 738, 773, 753, 733J/733, 723)
•Execute Disable Bit support for enhanced security (available on processors with CPU
Signature = 06D8h and recommended for implementation on Intel®915 Express chipset
family-based platforms only)
The Pentium M processor will be manufactured on Intel’s advanced 90 nm process technology
with copper interconnect. The processor maintains support for MMX technology and Internet
Streaming SIMD instructions and full compatibility with IA-32 software. The on-die, 32-KB
Level 1 instruction and data caches along with the 2-MB L2 cache with advanced transfer cache

8Datasheet
Introduction
architecture enable significant performance improvement over existing mobile processors. The
processor’s data prefetch logic fetches data to the L2 cache before L1 cache requests occurs,
resulting in reduced bus cycle penalties and improved performance.
The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
The Pentium M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The
400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve
performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced
Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling
technology with low power enhancements.
The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic
switching between multiple voltage and frequency points. This results in optimal performance
without compromising low power. The processor features the Auto Halt, Stop Grant, Deep Sleep,
and Deeper Sleep low power states.
The Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and
surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-
FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is
referred to as the mPGA479M socket.
Pentium M processors with CPU Signature = 06D8h will also include the Execute Disable Bit
capability. This feature combined with a support operating system allows memory to be marked as
executable or non executable. If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the
system. See the Intel®Architecture Software Developer's Manual for more detailed information.
Intel will validate this feature only on Intel 915 Express chipset family based platforms and
recommends customers implement BIOS changes related to this feature, only on Intel 915 Express
chipset family based platforms.
Note: The term AGTL+ is used to refer to Assisted GTL+ signalling technology on some Intel processors.

Datasheet 9
Introduction
1.1 Terminology
1.2 References
Material and concepts available in the following documents may be beneficial when reading this
document. Please note that “platform design guides,” when used throughout this document, refers
to the platform design guides listed below:
Term Definition
# A “#” symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the “#” symbol implies
that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and
D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
XXXX means that the specification or value is yet to be determined.
Front Side Bus
(FSB) Refers to the interface between the processor and system core logic (also known as the chipset components).
Table 1-1. References (Sheet 1 of 2)
Document Document Number/
Location1
IntelPentiumM Processor on 90 nm Process with 2-MB L2 Cache -
Specification Update http://www.intel.com/
design/mobile/specupdt/
302209.htm
Mobile Intel915PM/GM/GMS and 910GML Express Chipset Datasheet http://www.intel.com/
design/mobile/datashts/
305264.htm
Mobile Intel915PM/GM/GMS and 910GML Express Chipset Specification
Update http://www.intel.com/
design/mobile/specupdt/
307167.htm
Intel855PM Chipset Platform Design Guide: For use with IntelPentiumM and
IntelCeleronProcessors http://developer.intel.com/
design/mobile/desguide/
252614.htm
Intel855PM Chipset Memory Controller Hub (MCH) Datasheet http://developer.intel.com/
design/chipsets/datashts/
252613.htm
Intel855PM Chipset MCH DDR 333/200/266 MHz Specification Update http://developer.intel.com/
design/chipsets/specupdt/
253488.htm
Intel855GM/GME Chipset Graphics and Memory Controller Hub (GMCH)
Datasheet http://developer.intel.com/ design/chipsets/datashts/
252615.htm
Intel855GM/GME Chipset Graphics and Memory Controller Hub (GMCH)
Chipset Specification Update http://developer.intel.com/ design/chipsets/specupdt/
253572.htm
Intel855GM/855GME Chipset Platform Design Guide http://developer.intel.com/
design/mobile/desguide/
252616.htm

10 Datasheet
Introduction
NOTE: Contact your Intel representative for the latest revision and document number of this document.
§
IA-32 IntelArchitecture Software Developer's Manual http://www.intel.com/
design/pentium4/
manuals/index_new.htm
Volume 1: Basic Architecture
Volume 2A: Instruction Set Reference
Volume 2B: Instruction Set Reference
Volume 3: System Programming Guide
Table 1-1. References (Sheet 2 of 2)
Document Document Number/
Location1

Datasheet 11
Low Power Features
2Low Power Features
2.1 Clock Control and Low Power States
The Pentium M processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep Sleep,
and Deeper Sleep states for optimal power management. See Figure 2-1 for a visual representation
of the processor low-power states.
2.1.1 Normal State
This is the normal operating state for the processor.
2.1.2 AutoHALT Power-Down State
AutoHALT Power-Down is a low-power state entered when the processor executes the HALT
instruction. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to
immediately initialize itself.
A system management interrupt (SMI) handler will return execution to either Normal state or the
AutoHALT Power-Down state. See the IA-32 Intel®Architecture Software Developer's Manual,
Volume 3: System Programmer's Guide for more information.
Figure 2-1. Clock Control States
snoop
occurs
Stop
Grant
Normal Sleep
HALT/
Grant
Snoop
Auto Halt Deep
Sleep
STPCLK# asserted SLP# asserted
SLP# deasserted
STPCLK# deasserted
snoop
serviced
HLT
instruction
snoop
serviced snoop
occurs
DPSLP#
de-asserted DPSLP#
asserted
STPCLK#
asserted
STPCLK#
deasserted
halt
break
V0001-04
core voltage raised
core voltage lowered
Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
Deeper
Sleep

12 Datasheet
Low Power Features
The system can generate a STPCLK# while the processor is in the AutoHALT Power-Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
While in AutoHALT Power-Down state, the processor will process bus snoops and interrupts.
2.1.3 Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven
(allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the FSB should be driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be
deasserted ten or more bus clocks after the de-assertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
FSB (see Section 2.1.3). A transition to the Sleep state (see Section 2.1.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the Normal State. Only one occurrence of each event
will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts
delivered on the FSB.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if
there is any pending interrupt latched within the processor. Pending interrupts that are blocked by
the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to
system logic that it should return the processor to the Normal state.
2.1.4 HALT/Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop-Grant state or
in AutoHALT Power-Down state. During a snoop or interrupt transaction, the processor enters the
HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been
serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched.
After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant
state or AutoHALT Power-Down state, as appropriate.

Datasheet 13
Low Power Features
2.1.5 Sleep State
A low power state in which the processor maintains its context, maintains the phase-locked loop
(PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant
state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the
SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state.
SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may
result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or
RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state by asserting the DPSLP# pin. (See Section 2.1.6.) While the processor is in the Sleep
state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.6 Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped
during the Deep Sleep state for additional platform level power savings.
BCLK stop/restart timings on 855PM and Intel 855GM chipset-based platforms are as follows:
•Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock
chip will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds.
•Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The platform clock
chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6
BCLK periods later.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after
DPSLP# deassertion, as described above. A period of 30 microseconds (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in
Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant
state will result in unpredictable behavior.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.

14 Datasheet
Low Power Features
2.1.7 Deeper Sleep State
The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
to the platform design guides listed in Table 1-1.
2.2 Enhanced Intel SpeedStep®Technology
The Pentium M processor features Enhanced Intel SpeedStep technology. Unlike previous
implementations of Intel SpeedStep technology, this technology enables the processor to switch
between multiple frequency and voltage points instead of two. This will enable superior
performance with optimal power savings. Switching between states is software controlled unlike
previous implementations where the GHI# pin is used to toggle between two states. Following are
the key features of Enhanced Intel SpeedStep technology:
•Multiple voltage/frequency operating points provide optimal performance at the lowest power.
•Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model
Specific Registers) thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, Vcc is ramped up by placing a
new value on the VID pins and the PLL then locks to the new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the new
frequency and the Vcc is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in progress, the
new transition is deferred until its completion.
•The processor controls voltage ramp rates internally to ensure glitch free transitions.
•Low transition latency and large number of transitions possible per second.
— Processor core (including L2 cache) is unavailable for up to 10 s during the frequency
transition
— The bus protocol (BNR# mechanism) is used to block snooping
•No bus master arbiter disable required prior to transition and no processor cache flush
necessary.
•Improved Intel®Thermal Monitor mode.
— When the on-die thermal sensor indicates that the die temperature is too high, the
processor can automatically perform a transition to a lower frequency/voltage specified in
a software programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to acceptable
levels, an up transition to the previous frequency/voltage point occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling
better system level thermal management.

Datasheet 15
Low Power Features
2.3 Front Side Bus Low Power Enhancements
The Pentium M processor incorporates the following front side bus (processor system bus) low
power enhancements:
•Dynamic FSB Power Down
•BPRI# control for address and control input buffers
•Dynamic On Die Termination disabling
•Low VCCP (I/O termination voltage)
The Pentium M processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates them only
when data bus activity occurs, resulting in significant power savings with no performance impact.
BPRI# control also allows the processor address and control input buffers to be turned off when the
BPRI# signal is inactive. The on-die termination on the processor FSB buffers is disabled when the
signals are driven low, resulting in additional power savings. The low I/O termination voltage is on
a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all
times.
2.4 Processor Power Status Indicator (PSI#) Signal
The Pentium M processor incorporates the PSI# signal that is asserted when the processor is in a
low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and
deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator,
resulting in platform power savings and extended battery life. PSI# can also be used to simplify
voltage regulator designs since it removes the need for integrated 100 s timers required to mask
the PWRGOOD signal during Deeper Sleep transitions. It also helps loosen PWRGOOD
monitoring requirements in the Deeper Sleep state.
§

16 Datasheet
Low Power Features

Datasheet 17
Electrical Specifications
3Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the Pentium M processor has a large number of VCC (power)
and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins
must be connected to system ground planes. Use of multiple power and ground planes is
recommended to reduce I*R drop. Please refer to the platform design guides for more details. The
processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Pentium M processor core frequency is a
multiple of the BCLK[1:0] frequency. In regards to processor clocking, the Pentium M processor
uses a differential clocking implementation.
3.2 Voltage Identification
The Pentium M processor uses six voltage identification pins, VID[5:0], to support automatic
selection of power supply voltages. The VID pins for the Pentium M processor are CMOS outputs
driven by the processor VID circuitry. Table 3-1 specifies the voltage level corresponding to the
state of VID[5:0]. A “1” in this refers to a high-voltage level and a “0” refers to low-voltage level.

18 Datasheet
Electrical Specifications
3.3 Catastrophic Thermal Protection
The Pentium M processor supports the THERMTRIP# signal for catastrophic thermal protection.
An external thermal sensor should also be used to protect the processor and the system against
excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor
internal clocks and activity, leakage current can be high enough such that the processor cannot be
protected in all conditions without the removal of power to the processor. If the external thermal
sensor detects a catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP#
signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent
permanent silicon damage due to thermal runaway.
Table 3-1. Voltage Identification Definition
VID VID
5 4 3 2 1 0
VCC
V5 4 3 2 1 0
VCC
V
0 0 0 0 0 0 1.708 1 0 0 0 0 0 1.196
0 0 0 0 0 1 1.692 1 0 0 0 0 1 1.180
0 0 0 0 1 0 1.676 1 0 0 0 1 0 1.164
0 0 0 0 1 1 1.660 1 0 0 0 1 1 1.148
0 0 0 1 0 0 1.644 1 0 0 1 0 0 1.132
0 0 0 1 0 1 1.628 1 0 0 1 0 1 1.116
0 0 0 1 1 0 1.612 1 0 0 1 1 0 1.100
0 0 0 1 1 1 1.596 1 0 0 1 1 1 1.084
0 0 1 0 0 0 1.580 1 0 1 0 0 0 1.068
0 0 1 0 0 1 1.564 1 0 1 0 0 1 1.052
0 0 1 0 1 0 1.548 1 0 1 0 1 0 1.036
0 0 1 0 1 1 1.532 1 0 1 0 1 1 1.020
0 0 1 1 0 0 1.516 1 0 1 1 0 0 1.004
0 0 1 1 0 1 1.500 1 0 1 1 0 1 0.988
0 0 1 1 1 0 1.484 1 0 1 1 1 0 0.972
0 0 1 1 1 1 1.468 1 0 1 1 1 1 0.956
0 1 0 0 0 0 1.452 1 1 0 0 0 0 0.940
0 1 0 0 0 1 1.436 1 1 0 0 0 1 0.924
0 1 0 0 1 0 1.420 1 1 0 0 1 0 0.908
0 1 0 0 1 1 1.404 1 1 0 0 1 1 0.892
0 1 0 1 0 0 1.388 1 1 0 1 0 0 0.876
0 1 0 1 0 1 1.372 1 1 0 1 0 1 0.860
0 1 0 1 1 0 1.356 1 1 0 1 1 0 0.844
0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828
0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812
0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796
0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780
0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764
0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748
0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732
0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716
0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700

Datasheet 19
Electrical Specifications
3.4 Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future Pentium M processors. See Section 4.2 for a pin listing of the processor and the
location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Unused active high inputs should be connected through a resistor
to ground (VSS). Unused outputs can be left unconnected.
For details on signal terminations, please refer to the platform design guides.
The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1-k
pull-down resistors.
3.5 FSB Frequency Select Signals (BSEL[1:0])
These signals are used to select the FSB clock frequency. They should be connected between the
processor and the chipset MCH and clock generator on Intel 915 Express chipset family based
platforms. These signals must be left unconnected on platforms designed with the Intel 855 chipset
family. On these platforms, FSB clock frequency should be configured on the motherboard.
3.6 FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 3-2 identifies which signals are common clock, source
synchronous, and asynchronous.

20 Datasheet
Electrical Specifications
NOTES:
1. Refer to Chapter 4 for signal descriptions and termination requirements.
2. BPM[2:0}# and PRDY# are AGTL+ output only signals.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.
3.7 CMOS Signals
CMOS input signals are shown in Table 3-2. Legacy output FERR#, IERR# and other non-AGTL+
signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not
have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals
are required to be asserted for at least three BCLKs in order for the processor to recognize them.
See Section 3.9 for the DC and AC specifications for the CMOS signal groups.
Table 3-2. FSB Pin Groups
Signal Group Type Signals1
AGTL+ Common Clock Input Synchronous
to BCLK[1:0] BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY#
AGTL+ Common Clock I/O Synchronous
to BCLK[1:0] ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#
AGTL+ Source Synchronous I/O Synchronous
to assoc.
strobe
AGTL+ Strobes Synchronous
to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input Asynchronous A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/
NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output Asynchronous FERR#, IERR#, PROCHOT#, THERMTRIP#
CMOS Output Asynchronous PSI#, VID[5:0], BSEL[1:0]
CMOS Input Synchronous
to TCK TCK, TDI, TMS, TRST#
Open Drain Output Synchronous
to TCK TDO
FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]2
Power/Other COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,
THERMDA, THERMDC, VCC, VCCA[3:0], VCCP, VCCQ[1:0],
VCC_SENSE, VSS, VSS_SENSE
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[31:17]# ADSTB[1]#
D[15:0]#, DINV0# DSTBP0#, DSTBN0#
D[31:16]#, DINV1# DSTBP1#, DSTBN1#
D[47:32]#, DINV2# DSTBP2#, DSTBN2#
D[63:48]#, DINV3# DSTBP3#, DSTBN3#