Intel NIOS II User manual

Nios II Processor Reference Guide
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Contents
1. Introduction................................................................................................................... 8
1.1. Nios II Processor System Basics.............................................................................. 8
1.2. Getting Started with the Nios II Processor.................................................................9
1.3. Customizing Nios II Processor Designs....................................................................10
1.4. Configurable Soft Processor Core Concepts..............................................................11
1.4.1. Configurable Soft Processor Core............................................................... 11
1.4.2. Flexible Peripheral Set and Address Map......................................................11
1.4.3. Automated System Generation.................................................................. 12
1.5. Intel FPGA IP Evaluation Mode...............................................................................13
1.6. Introduction Revision History.................................................................................13
2. Processor Architecture..................................................................................................14
2.1. Processor Implementation.....................................................................................15
2.2. Register File........................................................................................................16
2.3. Arithmetic Logic Unit............................................................................................ 17
2.3.1. Unimplemented Instructions......................................................................17
2.3.2. Custom Instructions................................................................................. 17
2.3.3. Introduction to Nios II Floating Point Custom Instructions..............................18
2.4. Reset and Debug Signals...................................................................................... 21
2.5. Exception and Interrupt Controllers........................................................................ 22
2.5.1. Exception Controller................................................................................. 22
2.5.2. EIC Interface...........................................................................................23
2.5.3. Internal Interrupt Controller...................................................................... 23
2.6. Memory and I/O Organization................................................................................24
2.6.1. Instruction and Data Buses....................................................................... 25
2.6.2. Cache Memory.........................................................................................27
2.6.3. Tightly-Coupled Memory........................................................................... 29
2.6.4. Address Map........................................................................................... 30
2.6.5. Memory Management Unit.........................................................................30
2.6.6. Memory Protection Unit............................................................................ 31
2.7. JTAG Debug Module............................................................................................. 32
2.7.1. JTAG Target Connection............................................................................ 32
2.7.2. Download and Execute Software................................................................ 33
2.7.3. Software Breakpoints............................................................................... 33
2.7.4. Hardware Breakpoints.............................................................................. 33
2.7.5. Hardware Triggers....................................................................................33
2.7.6. Trace Capture..........................................................................................34
2.8. Processor Architecture Revision History...................................................................35
3. Programming Model......................................................................................................36
3.1. Operating Modes..................................................................................................36
3.1.1. Supervisor Mode......................................................................................36
3.1.2. User Mode.............................................................................................. 37
3.2. Memory Management Unit.................................................................................... 37
3.2.1. Recommended Usage............................................................................... 37
3.2.2. Memory Management............................................................................... 38
3.2.3. Address Space and Memory Partitions.........................................................39
3.2.4. TLB Organization..................................................................................... 41
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3.2.5. TLB Lookups............................................................................................42
3.3. Memory Protection Unit........................................................................................ 43
3.3.1. Memory Regions...................................................................................... 43
3.3.2. Overlapping Regions.................................................................................45
3.3.3. Enabling the MPU.....................................................................................45
3.4. Registers............................................................................................................ 45
3.4.1. General-Purpose Registers........................................................................ 45
3.4.2. Control Registers..................................................................................... 46
3.4.3. Shadow Register Sets...............................................................................65
3.5. Working with the MPU.......................................................................................... 68
3.5.1. MPU Region Read and Write Operations.......................................................68
3.5.2. MPU Initialization..................................................................................... 69
3.5.3. Debugger Access..................................................................................... 69
3.6. Working with ECC................................................................................................ 69
3.6.1. Enabling ECC...........................................................................................69
3.6.2. Handling ECC Errors................................................................................. 70
3.6.3. Injecting ECC Errors................................................................................. 70
3.7. Exception Processing............................................................................................74
3.7.1. Terminology............................................................................................ 74
3.7.2. Exception Overview..................................................................................75
3.7.3. Exception Latency.................................................................................... 77
3.7.4. Reset Exceptions......................................................................................77
3.7.5. Break Exceptions..................................................................................... 78
3.7.6. Interrupt Exceptions.................................................................................79
3.7.7. Instruction-Related Exceptions...................................................................83
3.7.8. Other Exceptions..................................................................................... 88
3.7.9. Exception Processing Flow.........................................................................88
3.7.10. Determining the Cause of Interrupt and Instruction-Related Exceptions......... 93
3.7.11. Handling Nested Exceptions.....................................................................94
3.7.12. Handling Nonmaskable Interrupts.............................................................96
3.7.13. Masking and Disabling Exceptions.............................................................96
3.8. Memory and Peripheral Access...............................................................................98
3.8.1. Cache Memory.........................................................................................99
3.9. Instruction Set Categories................................................................................... 100
3.9.1. Data Transfer Instructions....................................................................... 100
3.9.2. Arithmetic and Logical Instructions........................................................... 101
3.9.3. Move Instructions...................................................................................101
3.9.4. Comparison Instructions......................................................................... 102
3.9.5. Shift and Rotate Instructions................................................................... 102
3.9.6. Program Control Instructions................................................................... 103
3.9.7. Other Control Instructions....................................................................... 104
3.9.8. Custom Instructions............................................................................... 104
3.9.9. No-Operation Instruction.........................................................................105
3.9.10. Potential Unimplemented Instructions..................................................... 105
3.10. Programming Model Revision History...................................................................105
4. Instantiating the Nios II Processor.............................................................................106
4.1. Main Nios II Tab.................................................................................................106
4.2. Vectors Tab....................................................................................................... 107
4.2.1. Reset Vector.......................................................................................... 107
4.2.2. Exception Vector.................................................................................... 108
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4.2.3. Fast TLB Miss Exception Vector.................................................................108
4.3. Caches and Memory Interfaces Tab.......................................................................109
4.3.1. Instruction Cache...................................................................................110
4.3.2. Flash Accelerator....................................................................................111
4.3.3. Data Cache........................................................................................... 111
4.3.4. Tightly-coupled Memories........................................................................111
4.3.5. Peripheral Region................................................................................... 112
4.4. Arithmetic Instructions Tab..................................................................................112
4.4.1. Arithmetic Instructions............................................................................112
4.4.2. Arithmetic Implementation...................................................................... 113
4.5. MMU and MPU Settings Tab................................................................................. 113
4.5.1. MMU.....................................................................................................114
4.5.2. MPU..................................................................................................... 115
4.6. JTAG Debug Tab.................................................................................................115
4.7. Advanced Features Tab....................................................................................... 117
4.7.1. ECC......................................................................................................117
4.7.2. Interrupt Controller Interfaces................................................................. 118
4.7.3. Shadow Register Sets............................................................................. 118
4.7.4. Reset Signals.........................................................................................118
4.7.5. CPU ID Control Register Value..................................................................119
4.7.6. Generate Trace File.................................................................................119
4.7.7. Exception Checking................................................................................ 119
4.7.8. Branch Prediction................................................................................... 120
4.7.9. RAM Memory Protection.......................................................................... 120
4.8. The Quartus Prime IP File....................................................................................120
4.9. Instantiating the Nios II Processor Revision History.................................................120
5. Nios II Core Implementation Details...........................................................................121
5.1. Device Family Support........................................................................................ 121
5.2. Nios II/f Core.................................................................................................... 122
5.2.1. Overview.............................................................................................. 122
5.2.2. Arithmetic Logic Unit.............................................................................. 123
5.2.3. Memory Access...................................................................................... 124
5.2.4. Tightly-Coupled Memory......................................................................... 127
5.2.5. Memory Management Unit.......................................................................128
5.2.6. Memory Protection Unit...........................................................................128
5.2.7. Execution Pipeline.................................................................................. 129
5.2.8. Instruction Performance.......................................................................... 130
5.2.9. Exception Handling.................................................................................131
5.2.10. ECC....................................................................................................133
5.2.11. JTAG Debug Module.............................................................................. 134
5.3. Nios II/s Core....................................................................................................135
5.3.1. Overview.............................................................................................. 135
5.3.2. Arithmetic Logic Unit.............................................................................. 135
5.3.3. Memory Access...................................................................................... 137
5.3.4. Tightly-Coupled Memory......................................................................... 138
5.3.5. Execution Pipeline.................................................................................. 138
5.3.6. Instruction Performance.......................................................................... 139
5.3.7. Exception Handling.................................................................................140
5.3.8. JTAG Debug Module................................................................................140
5.4. Nios II/e Core....................................................................................................140
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5.4.1. Overview.............................................................................................. 141
5.4.2. Arithmetic Logic Unit.............................................................................. 141
5.4.3. Memory Access...................................................................................... 141
5.4.4. Instruction Execution Stages....................................................................141
5.4.5. Instruction Performance.......................................................................... 142
5.4.6. Exception Handling.................................................................................142
5.4.7. JTAG Debug Module................................................................................142
5.5. Nios II Core Implementation Details Revision History.............................................. 143
6. Nios II Processor Versions..........................................................................................144
6.1. Nios II Versions................................................................................................. 144
6.2. Architecture Revisions.........................................................................................144
6.3. Core Revisions...................................................................................................145
6.3.1. Nios II/f Core........................................................................................ 145
6.3.2. Nios II/s Core........................................................................................ 145
6.3.3. Nios II/e Core........................................................................................145
6.4. JTAG Debug Module Revisions..............................................................................145
6.5. Nios II Processor Versions Revision History............................................................ 145
7. Application Binary Interface....................................................................................... 146
7.1. Data Types........................................................................................................146
7.2. Memory Alignment............................................................................................. 146
7.3. Register Usage.................................................................................................. 147
7.4. Stacks.............................................................................................................. 148
7.4.1. Frame Pointer Elimination........................................................................149
7.4.2. Call Saved Registers............................................................................... 149
7.4.3. Further Examples of Stacks..................................................................... 149
7.4.4. Function Prologues................................................................................. 151
7.5. Arguments and Return Values.............................................................................. 152
7.5.1. Arguments............................................................................................ 153
7.5.2. Return Values........................................................................................ 153
7.6. DWARF-2 Definition............................................................................................154
7.7. Object Files....................................................................................................... 154
7.8. Relocation.........................................................................................................154
7.9. ABI for Linux Systems........................................................................................ 157
7.9.1. Linux Toolchain Relocation Information......................................................157
7.9.2. Linux Function Calls................................................................................160
7.9.3. Linux Operating System Call Interface.......................................................161
7.9.4. Linux Process Initialization...................................................................... 162
7.9.5. Linux Position-Independent Code..............................................................162
7.9.6. Linux Program Loading and Dynamic Linking..............................................164
7.9.7. Linux Conventions..................................................................................167
7.10. Development Environment.................................................................................167
7.11. Application Binary Interface Revision History........................................................168
8. Instruction Set Reference........................................................................................... 169
8.1. Word Formats....................................................................................................169
8.1.1. I-Type...................................................................................................169
8.1.2. R-Type.................................................................................................. 169
8.1.3. J-Type...................................................................................................170
8.2. Instruction Opcodes........................................................................................... 170
8.3. Assembler Pseudo-Instructions............................................................................ 172
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8.4. Assembler Macros.............................................................................................. 172
8.5. Instruction Set Reference.................................................................................... 173
8.5.1. add ..................................................................................................... 174
8.5.2. addi .................................................................................................... 175
8.5.3. and ..................................................................................................... 176
8.5.4. andhi ...................................................................................................177
8.5.5. andi .................................................................................................... 177
8.5.6. beq ..................................................................................................... 178
8.5.7. bge ..................................................................................................... 178
8.5.8. bgeu.................................................................................................... 179
8.5.9. bgt.......................................................................................................179
8.5.10. bgtu .................................................................................................. 180
8.5.11. ble .................................................................................................... 180
8.5.12. bleu ...................................................................................................180
8.5.13. blt ..................................................................................................... 181
8.5.14. bltu.................................................................................................... 181
8.5.15. bne ................................................................................................... 182
8.5.16. br ......................................................................................................182
8.5.17. break .................................................................................................183
8.5.18. bret ...................................................................................................184
8.5.19. call .................................................................................................... 184
8.5.20. callr ...................................................................................................185
8.5.21. cmpeq ............................................................................................... 185
8.5.22. cmpeqi ...............................................................................................186
8.5.23. cmpge ............................................................................................... 186
8.5.24. cmpgei ...............................................................................................187
8.5.25. cmpgeu ..............................................................................................188
8.5.26. cmpgeui .............................................................................................188
8.5.27. cmpgt ................................................................................................189
8.5.28. cmpgti ............................................................................................... 189
8.5.29. cmpgtu .............................................................................................. 189
8.5.30. cmpgtui ............................................................................................. 190
8.5.31. cmple................................................................................................. 190
8.5.32. cmplei ................................................................................................190
8.5.33. cmpleu ...............................................................................................191
8.5.34. cmpleui ..............................................................................................191
8.5.35. cmplt .................................................................................................191
8.5.36. cmplti ................................................................................................ 192
8.5.37. cmpltu ............................................................................................... 193
8.5.38. cmpltui .............................................................................................. 193
8.5.39. cmpne ............................................................................................... 194
8.5.40. cmpnei ...............................................................................................194
8.5.41. custom .............................................................................................. 195
8.5.42. div .................................................................................................... 196
8.5.43. divu ...................................................................................................197
8.5.44. eret ................................................................................................... 197
8.5.45. flushd ................................................................................................ 198
8.5.46. flushda ...............................................................................................199
8.5.47. flushi ................................................................................................. 200
8.5.48. flushp ................................................................................................ 201
8.5.49. initd .................................................................................................. 201
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8.5.50. initda .................................................................................................203
8.5.51. initi ................................................................................................... 204
8.5.52. jmp ................................................................................................... 205
8.5.53. jmpi .................................................................................................. 205
8.5.54. ldb / ldbio ...........................................................................................206
8.5.55. ldbu / ldbuio ....................................................................................... 207
8.5.56. ldh / ldhio .......................................................................................... 208
8.5.57. ldhu / ldhuio ....................................................................................... 209
8.5.58. ldw / ldwio ......................................................................................... 210
8.5.59. mov ...................................................................................................211
8.5.60. movhi ................................................................................................ 211
8.5.61. movi ..................................................................................................212
8.5.62. movia ................................................................................................ 212
8.5.63. movui ................................................................................................ 212
8.5.64. mul ................................................................................................... 213
8.5.65. muli ...................................................................................................214
8.5.66. mulxss ...............................................................................................214
8.5.67. mulxsu ...............................................................................................215
8.5.68. mulxuu .............................................................................................. 215
8.5.69. nextpc ............................................................................................... 216
8.5.70. nop ................................................................................................... 217
8.5.71. nor .................................................................................................... 217
8.5.72. or ......................................................................................................217
8.5.73. orhi ................................................................................................... 218
8.5.74. ori ..................................................................................................... 218
8.5.75. rdctl .................................................................................................. 219
8.5.76. rdprs ................................................................................................. 219
8.5.77. ret .....................................................................................................220
8.5.78. rol ..................................................................................................... 220
8.5.79. roli .................................................................................................... 221
8.5.80. ror .................................................................................................... 221
8.5.81. sll ......................................................................................................222
8.5.82. slli .....................................................................................................222
8.5.83. sra .................................................................................................... 223
8.5.84. srai ....................................................................................................223
8.5.85. srl ..................................................................................................... 224
8.5.86. srli .................................................................................................... 225
8.5.87. stb / stbio l..........................................................................................225
8.5.88. sth / sthio .......................................................................................... 226
8.5.89. stw / stwio ......................................................................................... 227
8.5.90. sub.....................................................................................................228
8.5.91. subi ...................................................................................................229
8.5.92. sync .................................................................................................. 229
8.5.93. trap ...................................................................................................230
8.5.94. wrctl ..................................................................................................230
8.5.95. wrprs .................................................................................................231
8.5.96. xor .................................................................................................... 232
8.5.97. xorhi ..................................................................................................232
8.5.98. xori ................................................................................................... 233
8.6. Instruction Set Reference Revision History.............................................................233
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1. Introduction
We have ended development of new Nios® II Classic processor features with the
Intel® Quartus® Prime 14.0 release. New features are implemented only in the Nios II
processor core. Although the Classic processor remains supported, we recommend
that you use the Nios II core for future designs.
This handbook describes the Nios II processor from a high-level conceptual description
to the low-level details of implementation. The chapters in this handbook describe the
Nios II processor architecture, the programming model, and the instruction set. The
Nios II processor is only availabe in the Intel Quartus Prime 14.1 release and above.
This handbook assumes you have a basic familiarity with embedded processor
concepts. You do not need to be familiar with any specific Intel FPGA technology or
with Intel FPGA development tools. This handbook limits discussion of hardware
implementation details of the processor system. The Nios II processors are designed
for Intel FPGA devices, and so this handbook does describe some FPGA
implementation concepts. Your familiarity with FPGA technology provides a deeper
understanding of the engineering trade-offs related to the design and implementation
of the Nios II processor.
This chapter introduces the Intel FPGA Nios II embedded processor family and
describes the similarities and differences between the Nios II processor and traditional
embedded processors.
Related Information
Nios II Processor webpage
1.1. Nios II Processor System Basics
The Nios II processor is a general-purpose RISC processor core with the following
features:
• Full 32-bit instruction set, data path, and address space
• 32 general-purpose registers
• Optional shadow register sets
• 32 interrupt sources
• External interrupt controller interface for more interrupt sources
• Single-instruction 32 × 32 multiply and divide producing a 32-bit result
• Dedicated instructions for computing 64-bit and 128-bit products of multiplication
• Optional floating-point instructions for single-precision floating-point operations
• Single-instruction barrel shifter
NII-PRG | 2018.04.18
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered

• Access to a variety of on-chip peripherals, and interfaces to off-chip memories and
peripherals
• Hardware-assisted debug module enabling processor start, stop, step, and trace
under control of the Nios II software development tools
• Optional memory management unit (MMU) to support operating systems that
require MMUs
• Optional memory protection unit (MPU)
• Software development environment based on the GNU C/C++ tool chain and the
Nios II Software Build Tools (SBT) for Eclipse
• Integration with Intel FPGA’s SignalTap® II Embedded Logic Analyzer, enabling
real-time analysis of instructions and data along with other signals in the FPGA
design
• Instruction set architecture (ISA) compatible across all Nios II processor systems
• Performance up to 250 DMIPS
• Error correcting code (ECC) support for all Nios II processor internal RAM blocks
A Nios II processor system is equivalent to a microcontroller or “computer on a chip”
that includes a processor and a combination of peripherals and memory on a single
chip. A Nios II processor system consists of a Nios II processor core, a set of on-chip
peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a
single Intel FPGA device. Like a microcontroller family, all Nios II processor systems
use a consistent instruction set and programming model.
1.2. Getting Started with the Nios II Processor
The easiest way to start designing effectively is to use an Intel development kit that
includes a ready-made development board and the Nios II Embedded Design Suite
(EDS) containing all the software development tools necessary to write Nios II
software.
The Nios II EDS includes the following two closely-related software development tool
flows:
• The Nios II SBT
• The Nios II SBT for Eclipse
Both tools flows are based on the GNU C/C++ compiler. The Nios II SBT for Eclipse™
provides a familiar and established environment for software development. Using the
Nios II SBT for Eclipse, you can immediately begin developing and simulating Nios II
software applications.
The Nios II SBT also provides a command line interface.
Using the Nios II hardware reference designs included in an Intel development kit, you
can prototype an application running on a board before building a custom hardware
platform.
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Figure 1. Example of a Nios II Processor System
Nios II
Processor Core
SDRAM
Controller
On-Chip ROM
Tristate bridge to
off-chip memory
System Interconnect Fabric
JTAG
Debug Module
SDRAM
Memory
Flash
Memory
SRAM
Memory
UART
Timer1
Timer2
LCD Display Driver
General-Purpose I/O
Ethernet Interface
CompactFlash
Interface
LCD
Screen
Ethernet
MAC/PHY
Compact
Flash
Buttons,
LEDs, etc.
TXD
RXD
JTAG connection
to software debugger
Clock
Reset
Data
Inst.
If the prototype system adequately meets design requirements using an Intel-
provided reference design, you can copy the reference design and use it without
modification in the final hardware platform. Otherwise, you can customize the Nios II
processor system until it meets cost or performance requirements.
Related Information
All Development Kits - Intel FPGA webpage
1.3. Customizing Nios II Processor Designs
In practice, most FPGA designs implement some extra logic in addition to the
processor system. Intel FPGAs provide flexibility to add features and enhance
performance of the Nios II processor system. You can also eliminate unnecessary
processor features and peripherals to fit the design in a smaller, lower-cost device.
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Because the pins and logic resources in Intel FPGA devices are programmable, many
customizations are possible:
• You can rearrange the pins on the chip to simplify the board design. For example,
you can move address and data pins for external SDRAM memory to any side of
the chip to shorten board traces.
• You can use extra pins and logic resources on the chip for functions unrelated to
the processor. Extra resources can provide a few extra gates and registers as glue
logic for the board design; or extra resources can implement entire systems. For
example, a Nios II processor system consumes only 5% of a large Intel FPGA,
leaving the rest of the chip’s resources available to implement other functions.
• You can use extra pins and logic on the chip to implement additional peripherals
for the Nios II processor system. Intel FPGA offers a library of peripherals that
easily connect to Nios II processor systems.
1.4. Configurable Soft Processor Core Concepts
This section introduces Nios II concepts that are unique or different from other
discrete microcontrollers. The concepts described in this section provide a foundation
for understanding the rest of the features discussed in this handbook.
1.4.1. Configurable Soft Processor Core
The Nios II processor is a configurable soft IP core, as opposed to a fixed, off-the-shelf
microcontroller. You can add or remove features on a system-by-system basis to meet
performance or price goals. Soft means the processor core is not fixed in silicon and
can be targeted to any Intel FPGA family.
You are not required to create a new Nios II processor configuration for every new
design. Intel FPGA provides ready-made Nios II system designs that you can use as is.
If these designs meet your system requirements, there is no need to configure the
design further. In addition, you can use the Nios II instruction set simulator to begin
writing and debugging Nios II applications before the final hardware configuration is
determined.
1.4.2. Flexible Peripheral Set and Address Map
A flexible peripheral set is one of the most notable differences between Nios II
processor systems and fixed microcontrollers. Because the Nios II processor is
implemented in programmable logic, you can easily build made-to-order Nios II
processor systems with the exact peripheral set required for the target applications.
Intel FPGA provides software constructs to access memory and peripherals generically,
independently of address location. Therefore, the flexible peripheral set and address
map does not affect application developers.
There are two broad classes of peripherals: standard peripherals and custom
peripherals.
1.4.2.1. Standard Peripherals
Intel FPGA provides a set of peripherals commonly used in microcontrollers, such as
timers, serial communication interfaces, general-purpose I/O, SDRAM controllers, and
other memory interfaces. The list of available peripherals continues to increase as
Intel FPGA and third-party vendors release new peripherals.
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Related Information
Embedded Peripherals IP User Guide
1.4.2.2. Custom Components
You can also create custom components and integrate them in Nios II processor
systems. For performance-critical systems that spend most CPU cycles executing a
specific section of code, it is a common technique to create a custom peripheral that
implements the same function in hardware.
This approach offers a double performance benefit:
• Hardware implementation is faster than software.
• Processor is free to perform other functions in parallel while the custom peripheral
operates on data.
Related Information
Creating Platform Designer Components
1.4.2.3. Custom Instructions
Like custom peripherals, custom instructions allow you to increase system
performance by augmenting the processor with custom hardware. You can achieve
significant performance improvements, often on the order of 10 to 100 times, by
implementing performance-critical operations in hardware using custom instruction
logic.
The custom logic is integrated into the Nios II processor’s arithmetic logic unit (ALU).
Similar to native Nios II instructions, custom instruction logic can take values from up
to two source registers and optionally write back a result to a destination register.
Because the processor is implemented on reprogrammable Intel FPGAs, software and
hardware engineers can work together to iteratively optimize the hardware and test
the results of software running on hardware.
From the software perspective, custom instructions appear as machine-generated
assembly macros or C functions, so programmers do not need to understand assembly
language to use custom instructions.
1.4.3. Automated System Generation
Intel FPGA’s Platform Designer system integration tools fully automate the process of
configuring processor features and generating a hardware design that you program in
an Intel FPGA device. The Platform Designer graphical user interface (GUI) enables
you to configure Nios II processor systems with any number of peripherals and
memory interfaces. You can create entire processor systems without performing any
schematic or HDL design entry. Platform Designer can also import HDL design files,
providing an easy mechanism to integrate custom logic in a Nios II processor system.
After system generation, you can download the design onto a board, and debug
software executing on the board. To the software developer, the processor architecture
of the design is set. Software development proceeds in the same manner as for
traditional, nonconfigurable processors.
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1.5. Intel FPGA IP Evaluation Mode
You can evaluate the Nios II processor without a license. With Intel FPGA's free Intel
FPGA IP Evaluation Mode feature, you can perform the following actions:
• Simulate the behavior of a Nios II processor within your system.
• Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily.
• Generate time-limited device programming files for designs that include Nios II
processors.
• Program a device and verify your design in hardware.
You only need to purchase a license for the Nios II processor when you are completely
satisfied with its functionality and performance, and want to take your design to
production.
Related Information
AN 320: Using Intel FPGA IP Evaluation Mode
For more information about Intel FPGA IP Evaluation Mode.
1.6. Introduction Revision History
Document
Version
Changes
2018.04.18 • Implemented editorial enhancements.
• Changed the document part number to NII-PRG.
• Corrected incorrect callouts of ldio/stio to ldwio/ stwio throughout the document.
2016.10.28 Maintenance release.
2015.04.02 Initial release
1. Introduction
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2. Processor Architecture
This chapter describes the hardware structure of the Nios II processor, including a
discussion of all the functional units of the Nios II architecture and the fundamentals
of the Nios II processor hardware implementation.
The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn
necessitates a set of functional units that implement the instructions. A Nios II
processor core is a hardware design that implements the Nios II instruction set and
supports the functional units described in this document. The processor core does not
include peripherals or the connection logic to the outside world. It includes only the
circuits required to implement the Nios II architecture.
The Nios II architecture defines the following functional units:
• Register file
• Arithmetic logic unit (ALU)
• Interface to custom instruction logic
• Exception controller
• Internal or external interrupt controller
• Instruction bus
• Data bus
• Memory management unit (MMU)
• Memory protection unit (MPU)
• Instruction and data cache memories
• Tightly-coupled memory interfaces for instructions and data
• JTAG debug module
NII-PRG | 2018.04.18
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered

Figure 2. Nios II Processor Core Block Diagram
Exception
Controller
Internal
Interrupt
Controller
Arithmetic
Logic Unit
General
Purpose
Registers
Control
Registers
Nios II Processor Core
reset
clock
JTAG
interface
to software
debugger
Custom
I/O
Signals
irq[31..0]
JTAG
Debug Module
Program
Controller
&
Address
Generation
Custom
Instruction
Logic
Data Bus
Tightly Coupled
Data Memory
Tightly Coupled
Data Memory
Data
Cache
Instruction
Cache
Instruction Bus
Tightly Coupled
Instruction Memory
Tightly Coupled
Instruction Memory
cpu_resetrequest
cpu_resettaken
Memory
Management
Unit
Translation
Lookaside
Buffer
Instruction
Regions
Memory
Protection
Unit
Data
Regions
External
Interrupt
Controller
Interface
eic_port_data[44..0]
eic_port_valid
Shadow
Register
Sets
Required
Module Optional Module
Key
2.1. Processor Implementation
The functional units of the Nios II architecture form the foundation for the Nios II
instruction set. However, this does not indicate that any unit is implemented in
hardware. The Nios II architecture describes an instruction set, not a particular
hardware implementation. A functional unit can be implemented in hardware,
emulated in software, or omitted entirely.
A Nios II implementation is a set of design choices embodied by a particular Nios II
processor core. All implementations support the instruction set defined in the
Instruction Set Reference chapter.
Each implementation achieves specific objectives, such as smaller core size or higher
performance. This flexibility allows the Nios II architecture to adapt to different target
applications.
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Implementation variables generally fit one of three trade-off patterns: more or less of
a feature; inclusion or exclusion of a feature; hardware implementation or software
emulation of a feature. An example of each trade-off follows:
• More or less of a feature—For example, to fine-tune performance, you can
increase or decrease the amount of instruction cache memory. A larger cache
increases execution speed of large programs, while a smaller cache conserves on-
chip memory resources.
• Inclusion or exclusion of a feature—For example, to reduce cost, you can choose
to omit the JTAG debug module. This decision conserves on-chip logic and
memory resources, but it eliminates the ability to use a software debugger to
debug applications.
• Hardware implementation or software emulation—For example, in control
applications that rarely perform complex arithmetic, you can choose for the
division instruction to be emulated in software. Removing the divide hardware
conserves on-chip resources but increases the execution time of division
operations.
For information about which Nios II cores supports what features, refer to the Nios II
Core Implementation Details chapter of the Nios II Processor Reference Handbook.
For complete details about user-selectable parameters for the Nios II processor, refer
to the Instantiating the Nios II Processor chapter of the Nios II Processor Reference
Handbook.
Related Information
•Instantiating the Nios II Processor on page 106
•Nios II Core Implementation Details on page 121
•Instruction Set Reference on page 169
2.2. Register File
The Nios II architecture supports a flat register file, consisting of thirty-two 32-bit
general-purpose integer registers, and up to thirty-two 32-bit control registers. The
architecture supports supervisor and user modes that allow system code to protect the
control registers from errant applications.
The Nios II processor can optionally have one or more shadow register sets. A shadow
register set is a complete set of Nios II general-purpose registers. When shadow
register sets are implemented, the CRS field of the status register indicates which
register set is currently in use. An instruction access to a general-purpose register
uses whichever register set is active.
A typical use of shadow register sets is to accelerate context switching. When shadow
register sets are implemented, the Nios II processor has two special instructions,
rdprs and wrprs, for moving data between register sets. Shadow register sets are
typically manipulated by an operating system kernel, and are transparent to
application code. A Nios II processor can have up to 63 shadow register sets.
The Nios II architecture allows for the future addition of floating-point registers.
For details about shadow register set implementation and usage, refer to “Registers”
and “Exception Processing” in the Programming Model chapter of the Nios II Processor
Reference Handbook.
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For details about the rdprs and wrprs instructions, refer to the Instruction Set
Reference chapter of the Nios II Processor Reference Handbook.
Related Information
•Programming Model on page 36
•Instruction Set Reference on page 169
2.3. Arithmetic Logic Unit
The Nios II ALU operates on data stored in general-purpose registers. ALU operations
take one or two inputs from registers, and store a result back in a register. The ALU
supports the data operations described in the table below. To implement any other
operation, software computes the result by performing a combination of the
fundamental operations.
Table 1. Operations Supported by the Nios II ALU
Category Details
Arithmetic The ALU supports addition, subtraction, multiplication, and division on signed and unsigned operands.
Relational The ALU supports the equal, not-equal, greater-than-or-equal, and less-than relational operations (==, !=
>=, <) on signed and unsigned operands.
Logical The ALU supports AND, OR, NOR, and XOR logical operations.
Shift and Rotate The ALU supports shift and rotate operations, and can shift/rotate data by 0 to 31 bit positions per
instruction. The ALU supports arithmetic shift right and logical shift right/left. The ALU supports rotate left/
right.
2.3.1. Unimplemented Instructions
Some Nios II processor core implementations do not provide hardware to support the
entire Nios II instruction set. In such a core, instructions without hardware support
are known as unimplemented instructions.
The processor generates an exception whenever it issues an unimplemented
instruction so your exception handler can call a routine that emulates the operation in
software. Unimplemented instructions do not affect the programmer’s view of the
processor.
For a list of potential unimplemented instructions, refer to the Programming Model
chapter of the Nios II Processor Reference Handbook.
Related Information
Programming Model on page 36
2.3.2. Custom Instructions
The Nios II architecture supports user-defined custom instructions. The Nios II ALU
connects directly to custom instruction logic, enabling you to implement operations in
hardware that are accessed and used exactly like native instructions.
Refer to "Custom Instruction Tab" in the Instantiating the Nios II Processor chapter of
the Nios II Processor Reference Handbook for additional information.
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Related Information
•Instantiating the Nios II Processor on page 106
•Nios II Custom Instruction User Guide
2.3.3. Introduction to Nios II Floating Point Custom Instructions
The Nios II architecture supports single precision floating point instructions with either
of two optional components:
• Floating point hardware 2(1) (FPH2)—This component supports floating point
instructions as specified by the IEEE Std 754-2008 but with simplified, non-
standard rounding modes. The basic set of floating point custom instructions
includes single precision floating point addition, subtraction, multiplication,
division, square root, integer to float conversion, float to integer conversion,
minimum, maximum, negate, absolute, and comparisons.
• Floating point hardware (FPH1)—This component supports floating point
instructions as specified by the IEEE Std 754-1985. The basic set of floating point
custom instructions includes single-precision floating point addition, subtraction,
and multiplication. Floating point division is available as an extension to the basic
instruction set.
Note: For optimum performance and device footprint, Intel recommends using
FPH2 rather than FPH1.
These floating point instructions are implemented as custom instructions. The table
below lists a detailed description of the conformance to the IEEE standards.
Table 2. Hardware Conformance with IEEE 754-1985 and IEEE 754-2008 Floating
Point Standard
Feature Floating Point Hardware
Implementation with IEEE
754-1985
Floating Point Hardware 2
Implementation with IEEE
754-2008
Operations Addition/
subtraction
Implemented Implemented
Multiplication Implemented Implemented
Division Optional Implemented
Square root Not implemented, this operation is
implemented in software.
Implemented
Integer to float/
float to integer
Not implemented, this operation is
implemented in software.
Implemented
Minimum/
maximum
Not implemented, this operation is
implemented in software.
Implemented
Negate/absolute Not implemented, this operation is
implemented in software.
Implemented
Comparisons Not implemented, this operation is
implemented in software.
Implemented
Precision Single Implemented Implemented
continued...
(1) Second generation
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Feature Floating Point Hardware
Implementation with IEEE
754-1985
Floating Point Hardware 2
Implementation with IEEE
754-2008
Double Not implemented. Double precision
operations are implemented in
software.
Not implemented. Double precision
operations are implemented in
software.
Exception
conditions
Invalid operation Result is Not a Number (NaN) Result is Not a Number (NaN)
Division by zero Result is ±infinity Result is ±infinity
Overflow Result is ±infinity Result is ±infinity
Inexact Result is a normal number Result is a normal number
Underflow Result is ±0 Result is ±0
Rounding Modes Round to nearest Implemented Implemented (roundTiesToAway mode)
Round toward
zero
Not implemented Implemented (truncation mode)
Round toward
+infinity
Not implemented Not implemented
Round toward –
infinity
Not implemented Not implemented
NaN Quiet Implemented No distinction is made between
signaling and quiet NaNs as input
operands. A result that produces a NaN
may produce either a signaling or quiet
NaN.
Signaling Not implemented
Subnormal
(denormalized)
numbers
Subnormal operands are treated as
zero. The FPH2 custom instructions do
not generate subnormal numbers.
• The comparison, minimum,
maximum, negate, and absolute
operations support subnormal
numbers.
• The add, subtract, multiply, divide,
square root, and float to integer
operations do NOT support
subnormal numbers. Subnormal
operands are treated as signed
zero. The FPH1 custom instructions
do not generate subnormal
numbers.(2)
• The integer to float operation
cannot create subnormal numbers.
Software
exceptions
Not implemented. IEEE 754-1985
exception conditions are detected and
handled as described elsewhere in this
table.
Not implemented. IEEE 754-2008
exception conditions are detected and
handled as described elsewhere in this
table.(2)
Status flags Not implemented. IEEE 754-1985
exception conditions are detected and
handled as described elsewhere in this
table.
Not implemented. IEEE 754-2008
exception conditions are detected and
handled as described elsewhere in this
table.(2)
Note: The FPH2 component also supports faithful rounding, which is not an IEEE 754-defined
rounding mode. Faithful rounding rounds results to either the upper or lower nearest
single-precision numbers. Therefore, the result produced is one of two possible values
and the choice between the two is not defined. The maximum error of faithful
rounding is 1 unit in the last place (ulp). Errors may not be evenly distributed.
(2) This operation is not fully compliant with IEEE 754-2008.
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Related Information
Nios II Custom Instruction User Guide
2.3.3.1. Nios II Floating Point Hardware 2 Component
Table 3. Floating Point Custom Instruction 2 Operation Summary
In this table, a and b are assumed to be single-precision floating-point values.
Operation(3) N(4) Cycles Result Subnormal Rounding GCC
Inference
fdivs 255 16 a ÷ b Flush to 0 Nearest a / b
fsubs 254 5 a – b Flush to 0 Faithful a – b
fadds 253 5 a + b Flush to 0 Faithful a + b
fmuls 252 4 a x b Flush to 0 Faithful a * b
fsqrts 251 8 aFaithful sqrtf()(5)
floatis 250 4 int_to_float(a) Not applicable Not applicable Casting
fixsi 249 2 float_to_int(a) Flush to 0 Truncation Casting
round 248 2 float_to_int(a) Flush to 0 Nearest lroundf()(5)
Reserved 234 to 247 Undefined Undefined
fmins 233 1 (a < b) ? a : b Supported None fminf()(5)
fmaxs 232 1 (a < b) ? b : a Supported None fmaxf()(5)
fcmplts 231 1 (a < b) ? 1 : 0 Supported None a < b
fcmples 230 1 (a ≤ b) ? 1 : 0 Supported None a <= b
fcmpgts 229 1 (a > b) ? 1 : 0 Supported None a > b
fcmpges 228 1 (a ≥ b) ? 1 : 0 Supported None a >= b
fcmpeqs 227 1 (a = b) ? 1 : 0 Supported None a == b
fcmpnes 226 1 (a ≠ b) ? 1 : 0 Supported None a != b
fnegs 225 1 -a Supported None -a
fabss 224 1 |a| Supported None fabsf()
(3) These names match the names of the corresponding GCC command-line options except for
round, which GCC does not support.
(4) Specifies the 8 bit fixed custom instruction for the operation.
(5) Nios II GCC version 4.7.3 is not able to reliably replace calls to newlib floating-point functions
with the equivalent custom instruction even though it has Flush to 0-mcustom-<operation>
command-line options and pragma support for these operations. Instead, the custom
instruction must be invoked directly using the GCC __builtin_custom_* facility. The
Floating Point Custom Instruction 2 component includes a C header file that provides the
required #define macros to invoke the custom instruction directly.
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