Intel SBC 711 Quick user guide

SBC 711
ANALOG INPUT BOARD
.
HARDWARE REFERENCE MANUAL
•
Manual OrderNumber:9800485A
-
Copyright ©1977
IIntel Corporation, 3065 Bowers Avenue,Santa Clara,California 95051
I

PREFACE I
This manual providejs general information,installation,programming information, principlesof operation, and service information
for the Intel SBC 711Analog Input board.Additional information is available in the following document:Intel MULTIBUS Inter-
facing,Application oteAP-28.
The information in thi~manualis subjectto change without notice. Intel Corporation makes no warrantyof anykind with regard to this
material, including, but not limited to, the impliedwarranties of merchantability and fitness for a particular purpose. Intel Corporation
assumes no responsibility for anyerrors that may appear in thismanual and makesno commitment to updatenor to keep current the
information contained in this manual.
No part of this manual may be copiedor reproduced in anyform or byany means without the prior written consent of Intel Corporation.
The following are tra?emarks of Intel Corporation and may be used to describe Intel products:
ICE-30
ICE-80
INSITE
INTEL
INTELLEC
LIBRARYMANAGER
MCS
MEGACHASSIS
MICROMAP
MULTIBUS
PROMPT
UPI
RMX

CHAPTER 1
GENERAL INFORM ATION Page
Introduction ....... . ......... . . ......... . .. . . . . I-I
Description. ................................... 1-1
Equipment Supplied 1-2
Specifications. . . . . .. . . . . . ......... . ........... . 1-2
CHAPTER 2
PREPARATION FOR USE Page
Introduction . ............... . .............. . . . . 2-1
Unpacking and Inspection. . ...................... 2-1
Installation Considerations2-1
Power Requirement. ............ . . . ...........2-1
Cooling Requirement 2-1
Physical Dimensions . .................. . ... . . . 2-1
Bus Interface Requirements. . ............. . . . . . 2-1
Jumper Configurations 2-1
Memory Base Address 2-5
Multiplexer Input. ...... . ..... . ........... . . . . 2-6
ADC Configuration........................... 2-6
ADC Trigger . . .............................. 2-6
Interrupts . . .......... . ...... . ....... . . . . . ... 2-7
Transfer Acknowledge Delay................... 2-7
Auxiliary Power (Special) . . ..................... . 2-8
Multiplexer Channel Expansion.................. . 2-9
Current Loop InputResistors ... . ................ . 2-9
Analog Input Cabling .. ......................... 2-10
Board Installation 2-13
CHAPTER 3
PROGRAMMING INFORMATION Page
Introduction .................................. . 3-1
Memory Base Address 3-1
Memory Address Assignments.. . ............. . .. . 3-1
Read/Write Formats 3-1
Multiplexer Address andGain. ................. 3-1
Last Channel .. .............................. 3-2
Command................................... 3-2
Status. .................................. . . . 3-2
Clear Interrupt Bit. .. . ........................ 3-2
ADC Data 3-2
Programming Examples 3-3
ONTENTS I
CHAPTER 4
PRINCIPLES OF OPERATION Page
Introduction ............. . . .. . ................ . 4-1
Functional Description 4-1
Analog Input Multiplexer . . . . ......... . ..... . .. 4-1
Programmable Gain Amplifier. . ........ . ....... 4-1
Sample-and-Hold Amplifier. . . .. . ..............4-1
Analog-to-Digital Converter. . ....... . . ........ . 4-1
DC-DC Converter.... . . . . .. . ...4-1
Control and Bus Interface. . . .................. . 4-1
Circuit Analysis. . . . . ......................... . . 4-1
Initialization. ............................... . 4-2
Base Address Decoding 4-2
Command Decoding. ... .. .... . .4-2
Write Commands. ....................... . . . 4-2
Read Commands. ....... . .................. 4-2
Data Buffers 4-5
Registers 4-5
Command Register . ..... . ..................4-5
Multiplex Address Register 4-5
Last Channel Register. .......... . ......... . . 4-5
Status Register. ........... . . . .......... . . ..4-5
Analog Input Operation 4-6
Random Channel . . . .............. . . .... . ... 4-6
Repetitive Single Channel.................... 4-7
Sequential Channel Scan. . .............. . . . . . 4-7
CHAPTER 5
SER VICE INFORM ATION Page
Introduction . . . ..................... . ..........5-1
Calibration . . ................ . ............... . . 5-1
Test Equipment Required . ..... . . . ............. 5-1
Preliminary Procedure. ........................ 5-1
ADC Calibration Procedure 5-1
PGA Offset..................... . ........ . 5-1
ADC Offset. ............................. . 5-1
ADC Range. ..............................5-2
Service Diagrams 5-2
Reshipment 5-2
APPENDIX A
CALIBRA TION PROGRAM

TABLES I
Specifications .
Multibus Connector PI PinAssignments .
Multibus Signal Functions.
SBC 711 AC Characteristics .
SBC 711 DC Characferistics .
ADC OutputBinary Fode Jumpers .
ADC Range and Polarization Jumpers .
Internal TADC/ clockRate Jumpers .
Board InterruptJumJers .
Multibus Interrupt JUflpers .
Transfer Acknowledge Delay Jumpers.
AuxiliaryPower Jumpers .
AuxiliaryPower Connector P2Pin Assignments.
Current Loop Input Resistors .
Analog Input Connector J2 Pin Assignments .
Analog Input Connector 13 Pin Assignments .
Memory Address Assignments.
Programmable Gain Vs ADC Full-Scale Range .
Programming Examples .
Write Command Decoder A15 Output Signals.
Read Command Decoder A 16 Output Signals.
Power Supply Voltage Checks .
ADC Offset and Range Adjustment Test Input .
Voltage Source Input Required for ADC Offset
and Range Adjustment .
ADC Offset and Range Adjustment Readings .
2-10
2-10
2-11
3-1
3-2
3-4
4-2
4-5
5-1
5-1
ILLUSTRATIONS I
Figure Title
SBC 711 Analog InPtt Board .
Bus Exchange Timinf.
MemoryBase Address Jumper Block .
Multiplexer Input Selection Jumpers .
External TADC/ Clock Characteristicsand Jumpers .
Single-Ended Analog InputCabling .
Differential Analog Input Cabling
(Differential Sources) .
Diff~rential Analog ~nputCabling
(Single-Ended Sources) .
Current Source Input Cabling .
MUX Address and Gain Format .
Last Channel Register Format .
Command Register Format .
Status Register Format .
Clear Interrupt Bit Format .
ADC Data Format _
SBC 711 Block Diagram .
SBC 711 Parts Location Diagram .
SBC 711 Schematic Diagram .
2-13
3-1
3-2
3-2
3-2
3-2
3-3
4-3
5-3
5-5
1-1
2-5
2-6
2-7
2-8
2-11

I
CHAPTER 1
j G_E_N_E_R_A_L_IN_F_O_R_M_A_T_IO_N_
1·1. INTRODUfTION
The SBC 711 Analog Input board is a member of acomplete
line of Intel SBC 80 systemexpansion modules. The SBC 711
is a analog input subsystem which, under microprocessor con-
trol,performs the ba ic functionsof data acquisition for analog-
to-digitalconversion. There arethree programmable modes of
operation for the acquisitionofanaloginputs:repetitive single
channelinput, sequential channel scan input,and random
channel input. I
1·2. DESCRIPrlON
The SBC 711 (figlfe I-I) is designed to be plugged into a
standard SBC 604/914 Modular Backplane and Cardcage to
interface directly Jith an Intel SBC 80 Single Board Com-
puter or used with the Intel IntellecMicrocomputer Develop-
ment System (MDS).
The SBC 711 multiplexer can accommodate 8 differential or 16
single-ended analog input channels. Sockets are provided so
that the multiplex capability can optionally be expanded to
accommodate an additional 8 differentialor 16 single-ended
channels by installing two 16-pin dual in-line package (DIP)
multiplexers.All input channels are protected to ±28V by
clamping diodes and fusible current-limit resistors;this in-
suresthe board against potentially destructive overloadsunder
fault conditions.
The differential input channels have provisions for the in-
stallation of discrete 250-ohm ± 1.0%1/4W resistors in order
to accept 4- to 20-mA current loop inputs. The temperature
coefficient of these resistorsmust be <0.01 %fC.
The selected differential or single-ended inputis applied to the
analog-to-digital converter (ADC) via a programmable gain
amplifier which,under program control,provides gains of I, 2,
4,or 8.The ADC is a 12-bit,35.7-microsecond, successive

approximation device withan internal sample-and-hold (Sill)
amplifier.The ADC can be jumper-selected for + 5V,+ JOV,
±5V, and ± JOV full-scale inputs. The AID conversion pro-
cess can be initiated by anexternal trigger,internal pacer clock,
or by programmed command.Systeminterrupts can be gener-
ated by (I) end-of-conversion, (2) end-of-scan,or (3) internal
pacer clock.
The external trigger is usefulwhentheAIDconversion istobe
synchronized to some external event. The internal pacer clock
(jumper-selectable intervalsfrom 975 microsecondstoI
second) allows precise, evenly spaced AIDconversionswhere
signal reconstruction is required.
The following are supplied with the SBC 711 Analog Input
board:
a.Schematic Diagram,dwgno. 2001397
b.Assembly Drawing, dwgno. 1001395
Specificationsfor the SBC 711 Analog Input board are listed
in table 1-1.
Vee =+5V±5%.
Ice =I.7Amaximum.
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity: 0° to 55°C(32° to131°F).
To 90%, without condensation.
PHYSICAL CHARACTERISTICS
Width:
Depth:
Thickness:
Weight:
30.48 em(12.00 inches).
17.15 em(6.75 inches).
1.27em(0.50 inch).
454gm(16 ounces).
Reserves a blockof 16 contiguousmemorylocations relative to a jumper-
selectablememorybase address. Programming information is pro-
vided in Chapter 3.
ANALOG INPUT
Number of Channels: 8 differential or 16 single-ended; expandable to 16 differential or 32
single-ended using two plug- in 8: I multiplexers (Harris HI 818A or
equi valent).
12-bits(0.025%), bipolar or unipolar.
<20 nanoseconds.
5 nanoseconds.
Gain AID Input Range
X+5V +IOV ±5V ±IOV
I +5V +IOV ±5V ±IOV
2+2.5V +5V ±2.5V ±5V
41.25V +2.5V ± 1.25V ±2.5V
80.625V + 1.25V ±0.625V ± I.25V
Power Off:680ohms.
Power On: > 100 megohms.
4 to 20 mA using customer-installed discrete 250-ohm ± 1% I 4W
resistors; resistor temperature coefficient must be <O.OI%f'C.
Balanced: <5000 ohms.
Unbalanced: < 1000 ohms.
Resolution:
S H Aperature Time:
S/H Uncertainty:
)
Jumper
Selectable
}Pm,,,mm,bl,

Common Mor,e Rejection(CMR):
Common Mo~e Voltage (CMV):
Input Overvoltage Protection:
Overall Accuracy (25°C):
60 dB (differential input).
± 1O.24V (signal pluscom'mon mode).
±28V (de);28V peak ac.
0.05%FSR ± 1/2 LSB (gain XI).
0.07%FSR ±1/2 LSB (gain X2, X4, X8).
(Includes 3a noise,linearity,offset gain, and dynamic response errors.)
0.0025%FSRJOC(Gain XI).
0.0030%FSRJOC (Gain X2,X4,X8).
28kHz.
THROUGHPUT*
Sample Rate (Single Channel):
Channel-to-Orannel Rate:
EXTERNAL TRIGGER:
17kHz.
16 kHz.
TTL compatible;1.5 f.Lsec(minimum)pulse width, better than 50 nsec
rise time.
1000
-- msec where n =0 through 10.
2"
INTERFACE CONNECTORS: No. of Pin Centers
Interface Mating Connectors
Pins in. mm
PI Multibus86 0.156 3.96 CDC VPBOIE43AOOAI
P2± 15V60 0.12.54 CDC VPBO IB30AOOA2
Aux Power Tl H3-11130
12 1st 8/16 50 0.1 2.54 3M 3415-0000 or
Input T1 H3-12125
Channels
13Expander50 0.1 2.54 Same as 12
8/16 Input
Channels
*Assuming 2-MHz CPU clock. Includestime required to transfer data from the SBC 711 to system memory.

CHAPTER 2
PREPARATION FOR USE
This chapter provides instructions for installingthe SBC 711
Analog Input board. These instructions include unpacking and
inspection;installation considerations such as power and cool-
ing requirements]physicaldimensions, and businterface
requirements; jumper configurations; optional auxiliary power
connections; mUIt~leXer channel expansion; current loop input
resistor installatio I; analog input cabling;and board installation.
Inspect the shipping carton immediatelyupon receipt for evi-
dence of mishandling during transit.Ifthe shipping carton is
severely damage~or waterstained,request that the carrier's
agent be present rhen the carton isopened.If the carrier's
agentis not present when the carton is opened and the con-
tents of the cart09are damaged,keep the carton and packing
material for the a~ent's inspection.
For repairstoa prbduct damaged in shipment,contact the Intel
Technical Support center (seeparagraph 5-10)to obtain a
Return Authorization Number and further instructions.A pur-
chase order will be required to complete the repair.Acopyof the
purchase order should be submitted tothe carrier with your
claim.
It is suggested that salvageableshipping cartonsand packing
material be saved I for futureuse in the event the product must
be shipped.
The SBC 711 isdesigned fo interface with an Intel SBC 80
Single Board Computer based systemor an Intel Intellec
Microcomputer Development System (MDS).Important in-
stallation and interfacing criteriaarepresented in following
paragraphs.
2-4.POWER REQUIREMENT
TheSBC 711 requ1ires +5V (±0.25V) at1.7A maximum.For
installation in an SBC80 Single Board Computer based system,
ensure that the system powersupplyhas sufficient + 5V current
overhead to accommodate the additional requirement.For in-
stallation in an Intellec MDS,calculate the total +5V current
requirement for the standard modulesand all installed optional
modules. Ensure that the additional 1.7A (maximum) current
requirement will not exceed the capacity of the + 5V supply.
2-5. COOLING REQUIREMENT
The SBC 711 dissipates 121 gram-calories/minute(0.49
Btu/minute) and adequate circulation of air mustbe provided to
prevent a temperature rise above 55°C(131°F). The system
80 enclosures and the Intellec MDS include fans to provide
adequate intake and exhaust of ventilating air.
a.Width:
b.Height:
c. Thickness:
30.48 cm (12.00 inches)
17.15 cm (6.75 inches)
1.27 cm (0.50 inch)
2-7. BUS INTERFACE REQUIREMENTS
The SBC 711 is designed for installation in a standard
Intel SBC 604/614 Modular Backplane and Cardcage or in the
Intellec MDS motherboard. As shown in figure 1-1,edge
connector PI provides interface to the Multibus.Connector PI
pin assignments are listed in table 2-1 and descriptionsof the
signal functions are given in table 2-2;an alternative mating
connector for PI is specified in table 1-1.Edge connector P2
is an auxiliary power input/output connector as described in
paragraph 2-15.
The ac and dc characteristics of the SBC 711 are presented in
tables 2-3 and 2-4, respectively.The bus exchange timing for
memory read and write operationsis shown infigure 2-1.
Instruction for configuring jumpersfor various control functions
of the SBC 711 are provided in following paragraphs.

PIN* SIGNAL FUNCTIONPIN* SIGNALFUNCTION
IGND
}
Ground44 ADRF
2GND 45 ADRC
3 +5 VDC
}
46 ADRD
4+5 VDC Power input 47 ADRAI
5+5 VDC 48 ADRB
6 +5 VDC 49 ADR8
750 ADR9
851ADR6 Address bus
952 ADR7
1053 ADR4
IIGND
}
Ground 54 ADR5
12GND 55 ADR2
13 56 ADR3
14 INIT System Initialize 57 ADRO
15 58 ADRI/
16 59
1760
18 61
19 MRDC MemoryRead Command 62
20 MWTC MemoryWrite Command 63
21 64
22 65
23 XACK/Transfer Acknowledge 66
24 INHI Inhibit RAM 67 DAT6
25 68 DAT7
26 INH2 Inhibit ROM 69 DAT4
2770 DAT5 Data bus
28 71 DAT2I
29 72 DAT3
30 73DATO
31CCLK/Constant Clock 74DATI
32 75GND
}
Ground
33 76 GND
34 77
35 INT6Interrupt request on level678
36 INTI Interrupt request on level 7 79
37INT4 Interrupt request on level 4 80
38 INT5 Interrupt request on level581 +5VDC
}
39 INT2IInterrupt request on level 2 82 +5VDC Power input
40 INT3 Interrupt request on level383 +5 VDC
41INTO Interrupt request on level084 +5 VDC
42 INTI Interrupt request on level I 85 GND
}
Ground
43 ADRE
1
86 GND
*All unassigned pinsare reserved.

SIGNAL FUNCTIONAL DESCRIPTION
ADRO/-ADRF/Address.These 16 lines transmit the address of the ADC and various registers on theSBC 711.
ADRF/ isthe most significant bit.
CCLK Constant Clock. A clock signal of constant frequency supplied by the system controller.The
frequency, period,and duty cycle of CCLK depends on which controller is employed.
DATO/-DAT7/ Data.These eight bidirectional lines transmit and receive data to and from the addressed
register on the SBC 711.
INIT/Initialize. Clears certain registerson the SBC 711.
INHI/ InhibitRAM.Generated when the SBC 711 isaddressed to prevent any RAM sharingthe same
addressfrom responding.
INH2/ Inhibit ROM.Generated when the SBC 711 is addressed to prevent any ROM (or PROM)
sharing the same address from responding.
INTO/-INTI/ Interrupt. These eight lines input interrupt requests to the system controller.INTO/ has the
highest priorityand INTI/has the lowest priority.
MRDC/MemoryRead Commond.Indicates that the address of the SBC 711 is on the Multibus address
linesand thatthe output of the addressed register is to be read (placed) onto the
Multibusdata lines.
MWTC/ Memory WriteCommond.Indicatesthat the address of the SBC 711 is on the Multibus
address lines and that the contentson the Multibusdata lines are to be loaded into the
addressed register.
XACK
Transfer Acknowledge.lndicatesthat the SBC 711 has completed the specified Memory Read
or MemoryWrite operation.That is, data has been placed onto or accepted from the
Multibusdatalines.
PARAMETkRMIMIMUM MAXIMUM DESCRIPTION REMARKS
(nsec) (nsec)
tAS 50 Address Setup to Command
tDS 50 Write DataSetup to Command
*txACK 50 1500 Command to Transfer Acknowledge Jumper selectable. See para-
graph 2-14.
tWCMD 100 Write Command Pulse Width
tAH 50 Address Hold Time
tDH 50Write DataHold Time
tDHR 0Read Data Hold Time
tTO 65 Acknowledge Turn Off Delay
tACC 200 Access Time to Read Data
tRCMD 250Read Command Pulse Width
tCCLK 100Constant Clock From system controller
*Assuming a CCLK frequency of 9.216 MHz.

SIGNALS SYMBOL PARAMETERDESCRIPTION TEST CONDITIONS MIN. MAX. UNITS
ADRO/-ADRF/ VIL Input Low Voltage 0.8 V
MRDC/ Vm Input High Voltage 2.0 V
MWTC/ IlL Input Current at Low V VIN
= 0.4-0.4mA
1m Input Current at High V VIN
= 2.720 p.,A
*CL Capacitive Load18 pF
XACK
VOL Output Low Voltage IOL
= 32 mA 0.4V
VOHOutput High Voltage IOH
= -5.2 mA 2.4V
ILH Output Leakage High Vo
= 2.440 p.,A
ILL Output Leakage Low Vo
= 0.4-40 p.,A
*CLCapacitive Load 15 pF
DATO/-DAT7/ VOL Output Low Voltage IOL
= 55 mA 0.6 V
VOH Output High VoltageIOH
= -10 mA 2.4V
VILInput LowVoltage 0.95 V
VmInputHigh Voltage 2.0 V
IlL InputCurrent at Low V VIN
= 0.45 -0.25 mA
ILHOutput Leakage High Vo
= 5.25 100 p.,A
*CL Capacitive Load 18pF
INIT VIL Input Low Voltage0.8 V
VmInput High Voltage 2.0 V
IlL Input Current at Low VVIN
= 0.4-1.6mA
1m Input Current at High V VIN
= 2.4400 p.,A
*CLCapacitive Load18 pF
INHI/-INH2/ VOL Output Low Voltage IOL
= 16 mA 0.4V
INTO/-INTI/ VOHOutput High Voltage OPEN COLLECTOR
VILInput Low Voltage 0.8 V
VmInput High Voltage 2.0 V
IlL Input Current at Low V VIN
= 0.4-1.6mA
IlL Input Current at High V VIN
= 2.4400 p.,A
*CLCapacitive Load 22 pF
*Capacitance values are approximations.

twCMD
l--tAS 'XACK
ADDRESS
MWTCI
XACKI
I
f--tDS
DATAl
X
VALID DATA
A.WRITE TO REGISTER
AOORES~ O#X~ x=
••• t_Ac_C
'AA)
_____X MA VA_L_ID_DA_T_A_--I
2-9.MEMORY BASE ADDRESS
The system processor communicateswith the SBC 711 by
issuing Memory Readand MemoryWrite commands.The
memory addresses used for thesecommandsare relative to a
16-bit base address that must lie on a 16-byte boundary;this
memory base address is assigned bythe user bymeans of
jumperwires installed ina 16-pin DIP header.The header is
then installed in IC socket M4 as shown in figure 5-1
zoneB7.
The 16-pin DIP header is configured at the factory for memory
base address F700; i.e., the SBC 711 willrecognize memory
addresses F700-F70F.Figure 2-2 showstwo examples of how to
configure the desired memory base address.Figure 2-2A shows
the jumpers as configured at the factory; figure 2-2B shows
asan example how to configure the jumpers for a memory
base address of 1230. Note that eachof the address bits
ADRF/-ADR4/ must be jumpered either to GND or +5V.

M4 M4
TOP VIEW TOP VIEW
FUNCTION PINPIN FUNCTION FUNCTION PIN PIN FUNCTION
NC 16 +5V NC 16 +5V
AOR4/15AORF/AOR4/ 15 AORF/
AOR5/14 AORE/AOR5/ 14 ADRE
ADR6/13 ADRD/ADR6/13 ADRD/
ADR7/12 ADRC/ADR7/ 12 ADRC/
ADRB/11 ADRAtADRB/ 11 ADRAt
NC 10 ADR9/NC 10 ADR9/
GND 9ADRB GND 9ADRB
Pin connected to +5Y allows (recognizes) a logic "1".
Pin connected to GNDallows (recognizes) a logic "0".
The multiplexer can accommodate 16 single-ended or 8 differ-
ential input channels, and can be expanded to accommodate
an additional 16 single-ended or 8 differentialinput channels
as described in paragraph2-16. TheSBC 711 is shipped with
jumpers configured for single-endedchannel operation as
shown in figure 2-3A. If differential channel operation is
required, reconfigure the jumpers as illustrated in figure 2-3B.
The jumpers shown infigure 2-3 are illustrated for clarity;
in practice, keep the jumpers as short as possible.
The ADC is configured at the factory to convert the analog
input voltage to a straight binary coded output.If an offset
binary-coded output is desired, reconfigure the jumpersas
listed in table 2-5.
Table 2-6 lists the jumpers required to select the desired full-
scale input voltage range and polarization. As indicated in
table 2-6, the ADC is configured at the factory for ± IOY
full-scale voltage operation. The ADCshould be recalibrated
each time it is reconfigured for a different full scale voltage
range.(Refer to Chapter 5.)
If the current range is used, precision resistorsmust be installed
as described in paragraph2-17. Also if the current range is used,
the multiplexer input must beconfigured for differential channel
operation as described in paragraph 2-10.
FUNCTION JUMPERS
Straight BinaryCode *66-67
Offset BinaryCode (2's Complement) 67-70
NOTES:
I.Refer to figure5-1;terminals 66-70 are located in
zone C3.
*Factory configuration;remove jumper if reconfig-
uring foroffset binary code.
2-12. ADC TRIGGER
A trigger pulse (TADC/), which is required to start the ND
conversion at precise intervals, may be obtained from the on-
board pacer clock or from anexternal TADC/ clock. If the
on-board pacer clock is used, select and jumper the desired
TADC/ clock rate as listed in table 2-7.If more precise timing
isrequired than supplied bythe on-board pacer clock, an
external TADC/ clock maybe input via pin 42 of connector J2.
Figure 2-4 providesthe external TADC/ clock characteristics
and jumper connections.

FULL-SCALE VOLTAGE RANGEl FULL-SCALE CURRENTRANGE2
+5V +IOV±5V ±IOV 4-20 mA
JUMPERS 3JUMPERS3
58-59 58-71 58-71 *58-71 58-59
60-61 60-61 60-62 *60-62 60-61
NOTES:
I.Configure m,Itiplexer jumpers as required for single-ended or differential channel operation;refer to paragraph 2-10.
2. Configure jultiplexer jumpers for differential channel operation; refer to paragraph 2-10.
3. Refer to figure 5-1. Terminals58through 62 are located in zonesC4, C3; terminal 71 islocated inzone C2.
* Factory configuration;remove jumpersif reconfiguring for a different voltage range or for current range.
A
I
~INGLE-ENDED CHANNELS
~" ~"
24
25
~26 50 52 54 56
27
S
I
DIFFERENTIAL CHANNELS
~23
I 24
~
G"
026
o 0
50 525456
27
487.4
NOTE:
I
Refer to figure 5-1.Terminals 23 through 27arelocated in
zone C4; terminals 51 through 57 are located in zone S5.
The SSC 732 provides two jumperselectableinterrupts which
may be interfaced to the systemcomputer viathe Multibus.
Select interrupt" A" and/or interrupt "S"by connecting the
jumpers as specified in table 2-8.
After interrupt "A" and/or Interrupt "S" jumpers have been
connected,these interruptscan be individually connected to
separate Multibusinterrupt lines or OR-tied to one Multibus
interrupt line. (Refer to table 2-9.) To connect Interrupt
"A"to MultibusINT7/, for example, connect a jumper
between terminals78 and 81;to OR-tie both Interrupt "A"
and "S" to Multibus INT3/,connect a jumper between
terminals78,79,and 85.
2-14. TRANSFER ACKNOWLEDGE DELAY
The SSC 71 I generatesa Transfer Acknowledge (XACK )
signal in response to Memory Readand Memory Write
Commands from the system computer.As listed in table 2-10,
the XACK response from the SSC 711 may be delayed for
50 nanosecondsto 1.5 microseconds after the receipt of a
command in order to ensure compatability with the system
computer timing.(Refer to paragraphs 4-11 and 4-12.)
CLOCK RATE JUMPER
1.000 sec 40-28
500.0 msec 40-31
250.0 msec 40-30
62.50 msec 40-33
31.25 msec 40-32
15.63 msec40-35
7.813 msec40-34
3.906 msec 40-37
1.953 msec 40-36
976.6 f.tsec
*40-38
NOTES:
1.Terminals are located in figure 5-1 zone C7.
*Factory configuration;remove jumper if reconfiguring
for different clock rate.

39-40
48-49*
NOTE:
1. Refer to figure 5-1.Terminals 39 and 40 are located in
zone C7;terminals 48 and 49 are located in zone C6.
*Factory configuration.
INTERRUPT "A"INTERRUPT "B"
PACEREOC EOS PACER EOC EOS
JUMPER' JUMPER'
63-64 64-96 *64-65 63-95 *95-96 65-95
**41-32 **41-32
NOTES:
1.Refer to figure5-1;terminalsare located in the following zones:41 (C7),63 (C4), 64-65 (C3), 95(C4),96 (C3).
*Factory configuration;remove appropriate jumper if reconfiguration is required.
**Pacer interrupt factory set to31.25 msec.If different interval is desired,disconnect jumper 41-32 and jumper terminal41
to appropriate clock ratejumper listed in table 2-7.
FUNCTION TERMINAL'
SBC 711 Interrupt "A" 78
Interrupt "B"79
INTO/86
INT1/87
INT2I 84
MULTIBUS INn/ 85
INT4/82
INT5/83
INT6/80
INTI/81
NOTE:
1.Refer to figure 5-1;terminals78 through 87are located
in zone B6.
The tolerance of the XACK delaydepends on the duty cycle
of the Constant Clock (CCLK ) signal generated by the system
computer; Le., the shorter the duty cycle of CCLK/,the
greater the accuracy of the delay.The delay timer is advanced
on the leading edge of CCLK , and XACK is generatedon
the trailing edge of CCLK .
Terminals 72, 73,77,and 76 must each be connected to
either terminal 74 or 75.For instance, toenforce a delay of
1.0 microsecond, jumper terminals 73 and 76 to terminal 74;
jumper terminals 72 and 77 to termina175. (Refer to table 2-10.)
The SBC 711 includes a dc-to-dc converter module (M5)
which supplies +15V and -15V power at 150 mA tothe
analog circuits.In some special applications the user may wish
to power an external function from this converter or remove the
converter and power the SBC 711analog circuits froman
external regulated source.Table 2-11lists the factory installed
jumpers to accommodate auxiliary power inputs or outputs.

JUMPERS I
DELAY (TYP)
72 73 77 76 (j.Lsec)
74 74 74 74 *0.05
74 74 74 75 0.1
74 74 75 74 0.2
I0.3
74
7
475 75
74 f574 74 0.4
74
7
574 75 0.5
74
t~
75 74 0.6
74 75 75 0.7
75
f:
74 74 0.8
75 74 75 0.9
75 75 74 1.0
75
7
475 75 1.1
75
~;
74 74 1.2
75 74 75 1.3
75 175 7574 1.4
75 f575 75 1.5
NOTES:
I.
Refer to figure 5-1;terminals72through 77 are located
in zone B7.
*Factory configuration;removejumpersif reconfigur-
ing for different delay.
Auxiliary pow r isinput or output viaedge connector P2.
Pinassignment are listed in table 2-12 and the required mating
connector is s cified in table 1-1 (Specifications).Install the
mating connec r for P2 in line with the backplane mating
connector for I.(See figure 1-1.)
FUNCTION JUMPER
1
+15V *90-91
-15V *92-93
Analog Return/AuxiliaryPowerCommon *88-89
NOTE:
I.
Refer to figure 5-1;terminals 88 through 93 are located
in zone B2.
*Jumpers are factoryinstalled.
2-16. MULTIPLEXER CHANNEL
EXPANSION
The SBC 711 can be expanded by an additional 16 single-
ended or 8 differential input channels by installing two Harris
H1818A 8: 1Multiplexers. Install the multiplexers in IC sockets
A2 and A5. Refer to figure 5-1 zone C4. Orient the multiplexer
IC;s with the notched ends (pin I) facing in the same direction
asthe other IC's on the board.
The SBC 711 can be adapted toaccept 4- to 20-mA current
loop inputs by the installation of discrete 250-ohm ± 1%
1/4W resistors; one discrete resistor is required for each channel.
Refer to table 2-13 and install a resistor(s) in the appropriate
channel(s). It should be noted that the ADC must be operated
in the differential input mode for current loop applications.
PIN* FUNCTION PIN*FUNCTION
21 AnalogReturn/AuxPwr Common 22 AnalogReturn/Aux Pwr Common
23 +15V 24 +15V
25 -15V 26-15V
NOTE:
All odd-numbered pins (1,3, ... 59) are on component side of the board.Pin I is the left-most pin when viewed from the com-
ponent side of theboard with theboard extractors at the top.
*Unlisted p'ns are reserved for futureuse.

DIFF RESISTOR DIFF2RESISTOR
CHAN CHAN
0R22 8R30
IR21 9R29
2 R20 10 R28
3RI9 II R27
4 RI8 12 R26
5RI7 13 R25
6RI6 14 R24
7 RI5 15 R23
NOTES:
1.Refer to figure 5-1. R 15 through R22are located in zone
D5; R23 through R30 are located in zone D4.
2.Channels 8-15 available only when H 1818A multiplexers
are installed.See paragraph 2-16.
Connector J2 providesthe interface between the 8 standard
differential analog channels(CH 0 through CH 7) or 16
single-ended channels(CH 0 through CH 15). Refer to
table 2-14.
Connector 13 providesthe interface between the 8 user-
expanded differentialchannels (CH 8 through CH 15) or
16 single-ended channels (CH 16 through CH 31).Refer to
table2-15.
Figures2-5 and 2-6 illustrate methods of connecting single-
ended and differential voltage sources to the SBC 711 inputs.
Figure 2-7 shows single-ended sources connected as differ-
ential inputs to eliminate ground loops and thereby reduce the
common-mode voltage.Figure 2-8 illustrates the method of
connecting current source inputs.
PIN SINGLE-ENDED DIFFERENTIAL PINSINGLE-ENDED DIFFERENTIAL
INot Used Not Used2Not UsedNot Used
3 Analog Return Analog Return4CH 0 CH 0 HI
56CH 8CH 0 LO
78CH 1 CH I HI
910CH 9 CH 1 LO
II 12CH 2 CH 2 HI
13 14 CH 10 CH2LO
15 16 CH 3 CH 3 HI
17 18 CH II CH 3 LO
19 20 CH 4 CH 4 HI
21 22 CH 12CH4LO
2324 CH 5 CH 5 HI
25 26 CH 13CH 5 LO
27 28 CH 6 CH 6 HI
29 30 CH 14 CH 6 LO
31
,
32 CH 7 CH 7 HI
33 Analog Return Analog Return34 CH 15 CH 7 LO
35 Not Used Not Used 36 Not Used Not Used
37 Not Used Not Used38 Not Used Not Used
39 Digital Common Digital fommon40 Clock Out Clock Out
41
~
42Ext.Trigger In Ext.Trigger In
43 44 EOC StatusOut EOC Status Out
45 Digital Common Digital Common46 EOS StatusOut EOS Status Out
47 Analog Return Analog Return 48Analog Return Analog Return
49 -15V -15V 50 +15V +15V
NOTE:
All odd-numbered pins (l, 3, ... 49) are oncomponent side of the board.Pin I istheright-most pin when viewed from the com-
ponent side with the board extractors atthe top.