Intel SBC 711 Quick user guide

SBC 711
ANALOG INPUT BOARD
.
HARDWARE REFERENCE MANUAL
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Manual OrderNumber:9800485A
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Copyright ©1977
IIntel Corporation, 3065 Bowers Avenue,Santa Clara,California 95051
I

PREFACE I
This manual providejs general information,installation,programming information, principlesof operation, and service information
for the Intel SBC 711Analog Input board.Additional information is available in the following document:Intel MULTIBUS Inter-
facing,Application oteAP-28.
The information in thi~manualis subjectto change without notice. Intel Corporation makes no warrantyof anykind with regard to this
material, including, but not limited to, the impliedwarranties of merchantability and fitness for a particular purpose. Intel Corporation
assumes no responsibility for anyerrors that may appear in thismanual and makesno commitment to updatenor to keep current the
information contained in this manual.
No part of this manual may be copiedor reproduced in anyform or byany means without the prior written consent of Intel Corporation.
The following are tra?emarks of Intel Corporation and may be used to describe Intel products:
ICE-30
ICE-80
INSITE
INTEL
INTELLEC
LIBRARYMANAGER
MCS
MEGACHASSIS
MICROMAP
MULTIBUS
PROMPT
UPI
RMX

CHAPTER 1
GENERAL INFORM ATION Page
Introduction ....... . ......... . . ......... . .. . . . . I-I
Description. ................................... 1-1
Equipment Supplied 1-2
Specifications. . . . . .. . . . . . ......... . ........... . 1-2
CHAPTER 2
PREPARATION FOR USE Page
Introduction . ............... . .............. . . . . 2-1
Unpacking and Inspection. . ...................... 2-1
Installation Considerations2-1
Power Requirement. ............ . . . ...........2-1
Cooling Requirement 2-1
Physical Dimensions . .................. . ... . . . 2-1
Bus Interface Requirements. . ............. . . . . . 2-1
Jumper Configurations 2-1
Memory Base Address 2-5
Multiplexer Input. ...... . ..... . ........... . . . . 2-6
ADC Configuration........................... 2-6
ADC Trigger . . .............................. 2-6
Interrupts . . .......... . ...... . ....... . . . . . ... 2-7
Transfer Acknowledge Delay................... 2-7
Auxiliary Power (Special) . . ..................... . 2-8
Multiplexer Channel Expansion.................. . 2-9
Current Loop InputResistors ... . ................ . 2-9
Analog Input Cabling .. ......................... 2-10
Board Installation 2-13
CHAPTER 3
PROGRAMMING INFORMATION Page
Introduction .................................. . 3-1
Memory Base Address 3-1
Memory Address Assignments.. . ............. . .. . 3-1
Read/Write Formats 3-1
Multiplexer Address andGain. ................. 3-1
Last Channel .. .............................. 3-2
Command................................... 3-2
Status. .................................. . . . 3-2
Clear Interrupt Bit. .. . ........................ 3-2
ADC Data 3-2
Programming Examples 3-3
ONTENTS I
CHAPTER 4
PRINCIPLES OF OPERATION Page
Introduction ............. . . .. . ................ . 4-1
Functional Description 4-1
Analog Input Multiplexer . . . . ......... . ..... . .. 4-1
Programmable Gain Amplifier. . ........ . ....... 4-1
Sample-and-Hold Amplifier. . . .. . ..............4-1
Analog-to-Digital Converter. . ....... . . ........ . 4-1
DC-DC Converter.... . . . . .. . ...4-1
Control and Bus Interface. . . .................. . 4-1
Circuit Analysis. . . . . ......................... . . 4-1
Initialization. ............................... . 4-2
Base Address Decoding 4-2
Command Decoding. ... .. .... . .4-2
Write Commands. ....................... . . . 4-2
Read Commands. ....... . .................. 4-2
Data Buffers 4-5
Registers 4-5
Command Register . ..... . ..................4-5
Multiplex Address Register 4-5
Last Channel Register. .......... . ......... . . 4-5
Status Register. ........... . . . .......... . . ..4-5
Analog Input Operation 4-6
Random Channel . . . .............. . . .... . ... 4-6
Repetitive Single Channel.................... 4-7
Sequential Channel Scan. . .............. . . . . . 4-7
CHAPTER 5
SER VICE INFORM ATION Page
Introduction . . . ..................... . ..........5-1
Calibration . . ................ . ............... . . 5-1
Test Equipment Required . ..... . . . ............. 5-1
Preliminary Procedure. ........................ 5-1
ADC Calibration Procedure 5-1
PGA Offset..................... . ........ . 5-1
ADC Offset. ............................. . 5-1
ADC Range. ..............................5-2
Service Diagrams 5-2
Reshipment 5-2
APPENDIX A
CALIBRA TION PROGRAM

TABLES I
Specifications .
Multibus Connector PI PinAssignments .
Multibus Signal Functions.
SBC 711 AC Characteristics .
SBC 711 DC Characferistics .
ADC OutputBinary Fode Jumpers .
ADC Range and Polarization Jumpers .
Internal TADC/ clockRate Jumpers .
Board InterruptJumJers .
Multibus Interrupt JUflpers .
Transfer Acknowledge Delay Jumpers.
AuxiliaryPower Jumpers .
AuxiliaryPower Connector P2Pin Assignments.
Current Loop Input Resistors .
Analog Input Connector J2 Pin Assignments .
Analog Input Connector 13 Pin Assignments .
Memory Address Assignments.
Programmable Gain Vs ADC Full-Scale Range .
Programming Examples .
Write Command Decoder A15 Output Signals.
Read Command Decoder A 16 Output Signals.
Power Supply Voltage Checks .
ADC Offset and Range Adjustment Test Input .
Voltage Source Input Required for ADC Offset
and Range Adjustment .
ADC Offset and Range Adjustment Readings .
2-10
2-10
2-11
3-1
3-2
3-4
4-2
4-5
5-1
5-1
ILLUSTRATIONS I
Figure Title
SBC 711 Analog InPtt Board .
Bus Exchange Timinf.
MemoryBase Address Jumper Block .
Multiplexer Input Selection Jumpers .
External TADC/ Clock Characteristicsand Jumpers .
Single-Ended Analog InputCabling .
Differential Analog Input Cabling
(Differential Sources) .
Diff~rential Analog ~nputCabling
(Single-Ended Sources) .
Current Source Input Cabling .
MUX Address and Gain Format .
Last Channel Register Format .
Command Register Format .
Status Register Format .
Clear Interrupt Bit Format .
ADC Data Format _
SBC 711 Block Diagram .
SBC 711 Parts Location Diagram .
SBC 711 Schematic Diagram .
2-13
3-1
3-2
3-2
3-2
3-2
3-3
4-3
5-3
5-5
1-1
2-5
2-6
2-7
2-8
2-11

I
CHAPTER 1
j G_E_N_E_R_A_L_IN_F_O_R_M_A_T_IO_N_
1·1. INTRODUfTION
The SBC 711 Analog Input board is a member of acomplete
line of Intel SBC 80 systemexpansion modules. The SBC 711
is a analog input subsystem which, under microprocessor con-
trol,performs the ba ic functionsof data acquisition for analog-
to-digitalconversion. There arethree programmable modes of
operation for the acquisitionofanaloginputs:repetitive single
channelinput, sequential channel scan input,and random
channel input. I
1·2. DESCRIPrlON
The SBC 711 (figlfe I-I) is designed to be plugged into a
standard SBC 604/914 Modular Backplane and Cardcage to
interface directly Jith an Intel SBC 80 Single Board Com-
puter or used with the Intel IntellecMicrocomputer Develop-
ment System (MDS).
The SBC 711 multiplexer can accommodate 8 differential or 16
single-ended analog input channels. Sockets are provided so
that the multiplex capability can optionally be expanded to
accommodate an additional 8 differentialor 16 single-ended
channels by installing two 16-pin dual in-line package (DIP)
multiplexers.All input channels are protected to ±28V by
clamping diodes and fusible current-limit resistors;this in-
suresthe board against potentially destructive overloadsunder
fault conditions.
The differential input channels have provisions for the in-
stallation of discrete 250-ohm ± 1.0%1/4W resistors in order
to accept 4- to 20-mA current loop inputs. The temperature
coefficient of these resistorsmust be <0.01 %fC.
The selected differential or single-ended inputis applied to the
analog-to-digital converter (ADC) via a programmable gain
amplifier which,under program control,provides gains of I, 2,
4,or 8.The ADC is a 12-bit,35.7-microsecond, successive

approximation device withan internal sample-and-hold (Sill)
amplifier.The ADC can be jumper-selected for + 5V,+ JOV,
±5V, and ± JOV full-scale inputs. The AID conversion pro-
cess can be initiated by anexternal trigger,internal pacer clock,
or by programmed command.Systeminterrupts can be gener-
ated by (I) end-of-conversion, (2) end-of-scan,or (3) internal
pacer clock.
The external trigger is usefulwhentheAIDconversion istobe
synchronized to some external event. The internal pacer clock
(jumper-selectable intervalsfrom 975 microsecondstoI
second) allows precise, evenly spaced AIDconversionswhere
signal reconstruction is required.
The following are supplied with the SBC 711 Analog Input
board:
a.Schematic Diagram,dwgno. 2001397
b.Assembly Drawing, dwgno. 1001395
Specificationsfor the SBC 711 Analog Input board are listed
in table 1-1.
Vee =+5V±5%.
Ice =I.7Amaximum.
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity: 0° to 55°C(32° to131°F).
To 90%, without condensation.
PHYSICAL CHARACTERISTICS
Width:
Depth:
Thickness:
Weight:
30.48 em(12.00 inches).
17.15 em(6.75 inches).
1.27em(0.50 inch).
454gm(16 ounces).
Reserves a blockof 16 contiguousmemorylocations relative to a jumper-
selectablememorybase address. Programming information is pro-
vided in Chapter 3.
ANALOG INPUT
Number of Channels: 8 differential or 16 single-ended; expandable to 16 differential or 32
single-ended using two plug- in 8: I multiplexers (Harris HI 818A or
equi valent).
12-bits(0.025%), bipolar or unipolar.
<20 nanoseconds.
5 nanoseconds.
Gain AID Input Range
X+5V +IOV ±5V ±IOV
I +5V +IOV ±5V ±IOV
2+2.5V +5V ±2.5V ±5V
41.25V +2.5V ± 1.25V ±2.5V
80.625V + 1.25V ±0.625V ± I.25V
Power Off:680ohms.
Power On: > 100 megohms.
4 to 20 mA using customer-installed discrete 250-ohm ± 1% I 4W
resistors; resistor temperature coefficient must be <O.OI%f'C.
Balanced: <5000 ohms.
Unbalanced: < 1000 ohms.
Resolution:
S H Aperature Time:
S/H Uncertainty:
)
Jumper
Selectable
}Pm,,,mm,bl,

Common Mor,e Rejection(CMR):
Common Mo~e Voltage (CMV):
Input Overvoltage Protection:
Overall Accuracy (25°C):
60 dB (differential input).
± 1O.24V (signal pluscom'mon mode).
±28V (de);28V peak ac.
0.05%FSR ± 1/2 LSB (gain XI).
0.07%FSR ±1/2 LSB (gain X2, X4, X8).
(Includes 3a noise,linearity,offset gain, and dynamic response errors.)
0.0025%FSRJOC(Gain XI).
0.0030%FSRJOC (Gain X2,X4,X8).
28kHz.
THROUGHPUT*
Sample Rate (Single Channel):
Channel-to-Orannel Rate:
EXTERNAL TRIGGER:
17kHz.
16 kHz.
TTL compatible;1.5 f.Lsec(minimum)pulse width, better than 50 nsec
rise time.
1000
-- msec where n =0 through 10.
2"
INTERFACE CONNECTORS: No. of Pin Centers
Interface Mating Connectors
Pins in. mm
PI Multibus86 0.156 3.96 CDC VPBOIE43AOOAI
P2± 15V60 0.12.54 CDC VPBO IB30AOOA2
Aux Power Tl H3-11130
12 1st 8/16 50 0.1 2.54 3M 3415-0000 or
Input T1 H3-12125
Channels
13Expander50 0.1 2.54 Same as 12
8/16 Input
Channels
*Assuming 2-MHz CPU clock. Includestime required to transfer data from the SBC 711 to system memory.