Intel 852GME Guide

Intel
®
852GME, Intel
®
852GMV and
Intel
®
852PM Chipset Platforms
Design Guide
For Use with the Mobile Intel
®
Pentium
®
4 Processor supporting Hyper-
Threading Technology on 90-nm process technology, Mobile Intel
®
Pentium
®
4 Processor, Intel
®
Celeron
®
Processor, and Intel
®
Celeron
®
D
Processors on 90 nm Process and in the 478-pin Package
June 2004
Order Number: 253026-004
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852GME, Intel
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852GMV and Intel
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852PM Chipset Platforms Design Guide
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
The information provided in this report, and related materials and presentations, are intended to illustrate the effects of certain design variables as
determined by modeling, and are neither a recommendation nor endorsement of any specific system-level design practices or targets. The model results
are based on a simulated notebook configuration, and do not describe or characterize the properties of any specific, existing system design. A detailed
description of the simulated notebook configuration is available upon request.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 852GME/852PM/852GMV Chipsets, Mobile Intel Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology,
Mobile Intel Pentium 4 processor and Intel Celeron processor may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
Intel, Intel logo, Pentium, Intel NetBurst, Celeron and Intel SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in
the United States and other countries.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2004

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Contents
1. Introduction.................................................................................................................................19
1.1. Referenced Documents .................................................................................................20
1.2. Conventions and Terminology .......................................................................................21
2. System Overview........................................................................................................................23
2.1. Intel 852GME Chipset Platform System Features.........................................................23
2.1.1. Host Interface .................................................................................................23
2.1.1.1. Mobile Intel Pentium 4 Processor supporting Hyper-Threading
Technology on 90-nm process technology .....................................23
2.1.1.2. Mobile Intel Pentium 4 Processor ...................................................24
2.1.1.3. Intel Celeron D Processor on 90 nm process and in the 478-pin
package...........................................................................................25
2.1.1.4. Intel Celeron Processor ..................................................................25
2.1.2. Intel 852GME Graphics Memory Controller Hub (GMCH).............................25
2.1.2.1. Multiplexed AGP and Intel
®
DVO Interface.....................................25
2.1.2.2. Accelerated Graphics Port (AGP) Interface....................................26
2.1.2.3. Integrated System Memory DRAM Controller ................................26
2.1.2.4. Internal Graphics Controller ............................................................26
2.1.3. Package/Power ..............................................................................................27
2.1.4. Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) ................................27
2.1.5. Firmware Hub (FWH) .....................................................................................28
2.2. Intel 852PM Chipset Platform System Features............................................................30
2.2.1. Host Interface .................................................................................................30
2.2.1.1. Mobile Intel Pentium 4 Processor ...................................................30
2.2.1.2. Intel Celeron Processor ..................................................................30
2.2.2. 852PM Memory Controller Hub (MCH)..........................................................30
2.2.2.1. Accelerated Graphics Port (AGP) Interface....................................30
2.2.2.2. Integrated System Memory DRAM Controller ................................31
2.2.3. Package/Power ..............................................................................................31
2.2.4. Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) ................................31
2.2.5. Firmware Hub (FWH) .....................................................................................31
2.3. Intel 852GMV Chipset Platform System Features.........................................................33
2.3.1. Host Interface .................................................................................................33
2.3.1.1. Intel Celeron Processor ..................................................................33
2.3.2. Intel 852GMV Graphics Memory Controller Hub (GMCH).............................33
2.3.2.1. Multiplexed AGP and Intel
®
DVO Interface.....................................33
2.3.2.2. Integrated System Memory DRAM Controller ................................34
2.3.2.3. Internal Graphics Controller ............................................................34
2.3.3. Package/Power ..............................................................................................34
2.3.4. Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) ................................35
2.3.5. Firmware Hub (FWH) .....................................................................................35
3. General Design Considerations .................................................................................................37
3.1. Recommended Board Stack-Up....................................................................................37
3.2. Alternate Stack Ups .......................................................................................................39
4. FSB Design Guidelines ..............................................................................................................41
4.1. FSB Routing Guidelines ................................................................................................41

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4.1.1.
Return Path Evaluation.................................................................................. 43
4.2. OPTIMIZED/COMPAT# Topology for Intel
®
852GME/852GMV/852PM
Only Platforms............................................................................................................... 43
4.3. General Topology and Layout Guidelines..................................................................... 44
4.3.1. Data Signals .................................................................................................. 44
4.3.2. Address Signals............................................................................................. 44
4.3.3. Strobe Signals ............................................................................................... 44
4.3.4. Common Clock Signals ................................................................................. 44
4.3.5. Source Synchronous (SS) Signals ................................................................ 45
4.3.6. Common Clock (CC) AGTL+ Signals ............................................................ 46
4.3.7. Asynchronous AGTL+ Signals ...................................................................... 47
4.3.7.1. Topologies ...................................................................................... 47
4.3.7.1.1. Topology 1A: Open Drain (OD) Signals Driven by the
Processor – IERR# and FERR#................................... 47
4.3.7.1.2. Topology 1B: Open Drain (OD) Signals Driven by the
Processor –THERMTRIP# ........................................... 48
4.3.7.1.3. Topology 1C: Open Drain (OD) Signals Driven by the
Processor –PROCHOT# .............................................. 49
4.3.7.1.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-
M – PWRGOOD ........................................................... 50
4.3.7.1.5. Topology 2B: CMOS Signals Driven by ICH4-M –
DPSLP#........................................................................ 51
4.3.7.1.6. Topology 2C: CMOS Signals Driven by ICH4-M –
A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#,
and STPCLK#............................................................... 52
4.3.7.1.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU
and FWH – INIT#.......................................................... 53
4.3.7.2. Voltage Translation Circuit ............................................................. 54
4.3.8. AGTL+ I/O Buffer Compensation .................................................................. 54
4.3.8.1. Mobile Intel Pentium 4 Processor AGTL+ I/O Buffer
Compensation ................................................................................ 55
4.3.9. Processor RESET# Signal ............................................................................ 55
4.4. Host Vrefs......................................................................................................................57
4.5. ITP Debug Port.............................................................................................................. 57
4.5.1. Logic Analyzer Interface (LAI) ....................................................................... 57
4.5.1.1. Mechanical Considerations ............................................................ 57
4.5.1.2. Electrical Considerations ................................................................ 57
4.6. Mobile Intel Pentium 4 Processor and 852GME/852GMV/852PMChipset FSB Signal
Package Lengths .......................................................................................................... 58
5. Platform Power Requirements ................................................................................................... 63
6. System Memory Design Guidelines (DDR-SDRAM) ................................................................. 65
6.1. Length Matching and Length Formulas......................................................................... 66
6.2. Package Length Compensation .................................................................................... 66
6.3. Topologies and Routing Guidelines .............................................................................. 67
6.3.1. Clock Signals – SCK[5:0], SCK#[5:0] ............................................................ 67
6.3.1.1. Clock Topology Diagram ................................................................ 67
6.3.1.2. Memory Clock Routing Guidelines ................................................. 68
6.3.1.3. Clock Length Matching Requirements ........................................... 69
6.3.1.4. Clock Reference Lengths ............................................................... 70
6.3.1.5. Clock Package Length Table ......................................................... 71

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6.3.1.6.
Clock Routing Example...................................................................72
6.3.2. Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0]..........................................72
6.3.2.1. Data Bus Topology..........................................................................74
6.3.2.2. SDQS to Clock Length Matching Requirements.............................75
6.3.2.3. Data to Strobe Length Matching Requirements..............................77
6.3.2.4. SDQ to SDQS Mapping ..................................................................77
6.3.2.5. SDQ/SDQS Signal Package Lengths .............................................79
6.3.2.6. Memory Data Routing Example ......................................................80
6.3.3. Control Signals – SCKE[3:0], SCS#[3:0] .......................................................81
6.3.3.1. Control Signal Topology..................................................................82
6.3.3.2. Control Signal Routing Guidelines..................................................82
6.3.3.3. Control to Clock Length Matching Requirements ...........................83
6.3.3.4. Memory Control Routing Example ..................................................85
6.3.3.5. Control Group Package Length Table ............................................86
6.3.4. Command Signals – SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.......86
6.3.4.1. Command Topology 1.....................................................................87
6.3.4.2. Command Topology 1 Routing Guidelines .....................................88
6.3.4.3. Command Topology 1 Length Matching Requirements .................89
6.3.4.4. Command Topology 2.....................................................................91
6.3.4.5. Command Topology 2 Routing Guidelines .....................................92
6.3.4.6. Command Topology 2 Length Matching Requirements .................93
6.3.4.7. Command Topology 2 Routing Example ........................................95
6.3.4.8. Command Topology 3.....................................................................96
6.3.4.9. Command Topology 3 Routing Guidelines .....................................97
6.3.4.10. Command Topology 3 Length Matching Requirements .................98
6.3.4.11. Command Group Package Length Table .....................................100
6.3.5. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]...............................................101
6.3.5.1. CPC Signal Topology....................................................................102
6.3.5.2. CPC Signal Routing Guidelines ....................................................102
6.3.5.3. CPC to Clock Length Matching Requirements .............................103
6.3.5.4. CPC Group Package Length Table ..............................................104
6.3.6. Feedback – RCVENOUT#, RCVENIN#.......................................................105
6.4. Routing Updates for “High-Density” Memory Device Support.....................................105
6.5. ECC Disable Guidelines ..............................................................................................105
6.5.1. GMCH/MCH ECC Functionality Disable ......................................................105
6.5.2. DDR Memory ECC Functionality Disable ....................................................106
6.6. System Memory Compensation...................................................................................106
6.7. SMVREF Generation ...................................................................................................106
6.8. DDR Power Delivery....................................................................................................106
6.9. External Thermal Sensor Based Throttling (ETS#) .....................................................107
6.9.1. ETS# Usage Model ......................................................................................107
6.9.2. ETS# Design Guidelines ..............................................................................107
6.9.3. Thermal Sensor Routing and Placement Guidelines...................................107
7. Integrated Graphics Display Port .............................................................................................109
7.1. Analog RGB/CRT Guidelines ......................................................................................109
7.1.1. RAMDAC/Display Interface..........................................................................109
7.1.2. Reference Resistor (REFSET).....................................................................109
7.1.3. RAMDAC Board Design Guidelines.............................................................110
7.1.4. RAMDAC Routing Guidelines ......................................................................111
7.1.5. DAC Power Requirements...........................................................................113
7.1.6. HSYNC and VSYNC Design Considerations...............................................114

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7.1.7.
DDC and I2C Design Considerations.......................................................... 114
7.2. LVDS Transmitter Interface......................................................................................... 114
7.2.1. LVDS Length Matching Constraints ............................................................ 115
7.2.2. LVDS Package Length Compensation........................................................ 115
7.2.3. LVDS Routing Guidelines............................................................................ 116
7.3. Digital Video Out Port.................................................................................................. 118
7.3.1. DVO Interface Signal Groups ...................................................................... 118
7.3.1.1. DVOB Interface Signals................................................................ 118
7.3.1.2. DVOC Interface Signals ............................................................... 118
7.3.1.3. Common Signals for Both DVO Ports .......................................... 119
7.3.2. DVOB and DVOC port Interface Routing Guidelines .................................. 119
7.3.2.1. Length Mismatch Requirements................................................... 119
7.3.2.2. Package Length Compensation ................................................... 120
7.3.2.3. DVOB and DVOC Routing Guidelines ......................................... 120
7.3.2.4. DVOB and DVOC Port Termination ............................................. 122
7.3.3. DVOB and DVOC Assumptions, Definitions, and Specifications ................ 122
7.3.4. DVOB and DVOC Simulation Method ......................................................... 123
7.4. DVOB and DVOC port Flexible (Modular) Design ...................................................... 124
7.4.1. DVOB and DVOC Module Design ............................................................... 124
7.4.1.1. Generic Connector Model............................................................. 125
7.5. DVO GMBUS and DDC Interface Considerations ...................................................... 125
7.5.1. Leaving the GMCH DVOB or DVOC Port Unconnected ............................. 126
7.6. Miscellaneous Input Signals and Voltage Reference.................................................. 127
8. AGP Port Design Guidelines.................................................................................................... 128
8.1. AGP Interface.............................................................................................................. 128
8.1.1. AGP 2.0 ....................................................................................................... 128
8.1.2. AGP Interface Signal Groups ...................................................................... 129
8.2. AGP Routing Guidelines ............................................................................................. 130
8.2.1. 1x Timing Domain Routing Guidelines ........................................................ 130
8.2.1.1. Trace Length Requirements for AGP 1X...................................... 130
8.2.1.2. Trace Spacing Requirements....................................................... 131
8.2.1.3. Trace Length Mismatch ................................................................ 131
8.2.2. 2x/4x Timing Domain Routing Guidelines ................................................... 131
8.2.2.1. Trace Length Requirements for AGP 2X/4X ................................ 131
8.2.2.2. Trace Spacing Requirements....................................................... 132
8.2.2.3. Trace Length Mismatch Requirements ........................................ 133
8.2.3. AGP Clock Skew ......................................................................................... 134
8.2.4. AGP Signal Noise Decoupling Guidelines................................................... 134
8.2.5. AGP Interface Package Lengths ................................................................. 135
8.2.6. AGP Routing Ground Reference ................................................................. 136
8.2.7. Pull-ups........................................................................................................ 136
8.2.8. AGP VDDQ and VCC .................................................................................. 138
8.2.9. VREF Generation for AGP 2.0 (2X and 4X) ................................................ 138
8.2.9.1. 1.5-V AGP Interface (2X/4X) ........................................................ 138
8.2.10. AGP Compensation ..................................................................................... 138
8.2.11. PM_SUS_CLK/AGP_PIPE# Design Consideration .................................... 138
9. Hub Interface............................................................................................................................ 140
9.1. Hub Interface Compensation ...................................................................................... 140
9.2. Hub Interface Data HL[10:0] and Strobe Signals........................................................ 141
9.2.1. HL[10:0] and Strobe Signals Internal Layer Routing ................................... 141

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9.2.2.
Terminating HL[11].......................................................................................143
9.3. Hub VREF/VSWING Generation/Distribution ..............................................................143
9.3.1. Single Generation Voltage Reference Divider Circuit..................................143
9.3.2. Locally Generated Voltage Reference Divider Circuit .................................144
9.3.3. Single GMCH and ICH4-M Voltage Generation / Separate Divider Circuit
for VSWING/VREF.......................................................................................145
9.3.4. Separate GMCH and ICH4-M Voltage Generation / Separate Divider
Circuits for VREF and VSWING...................................................................146
9.4. Hub Interface Decoupling Guidelines ..........................................................................146
10. I/O Subsystem ..........................................................................................................................148
10.1. IDE Interface ................................................................................................................148
10.1.1. Cabling .........................................................................................................148
10.1.2. Primary IDE Connector Requirements.........................................................149
10.1.3. Secondary IDE Connector Requirements....................................................150
10.1.4. Mobile IDE Swap Bay Support.....................................................................151
10.1.4.1. ICH4-M IDE Interface Tri-State Feature .......................................151
10.1.4.2. S5/G3 to S0 Boot Up Procedures for IDE Swap Bay ...................152
10.1.4.3. Power Down Procedures for Mobile Swap Bay ............................152
10.1.4.4. Power Up Procedures After Device “Hot” Swap Completed ........152
10.2. PCI ...............................................................................................................................153
10.3. AC’97 ...........................................................................................................................153
10.3.1. AC’97 Routing ..............................................................................................157
10.3.2. Motherboard Implementation .......................................................................157
10.3.2.1. Valid Codec Configurations ..........................................................158
10.3.3. SPKR Pin Configuration...............................................................................158
10.4. USB 2.0 Guidelines and Recommendations ...............................................................159
10.4.1. Layout Guidelines ........................................................................................159
10.4.1.1. General Routing and Placement...................................................159
10.4.1.2. USB 2.0 Trace Separation ............................................................160
10.4.1.3. USBRBIAS Connection.................................................................160
10.4.1.4. USB 2.0 Termination.....................................................................161
10.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................161
10.4.1.6. USB 2.0 Trace Length Guidelines ................................................161
10.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................162
10.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................162
10.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................162
10.4.3. USB Power Line Layout Topology ...............................................................162
10.4.4. EMI Considerations......................................................................................163
10.4.4.1. Common Mode Chokes ................................................................163
10.4.5. ESD ..............................................................................................................164
10.4.6. USB Selective Suspend ...............................................................................164
10.5. I/O APIC (I/O Advanced Programmable Interrupt Controller) .....................................164
10.6. SMBus 2.0/SMLink Interface .......................................................................................165
10.6.1. SMBus Architecture and Design Considerations.........................................166
10.6.1.1. SMBus Design Considerations .....................................................166
10.6.1.2. General Design Issues/Notes .......................................................167
10.6.1.3. High Power/Low Power Mixed Architecture..................................167
10.6.1.4. Calculating the Physical Segment Pull-Up Resistor .....................167
10.7. FWH .............................................................................................................................169
10.7.1. FWH Decoupling ..........................................................................................169

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10.7.2.
In Circuit FWH Programming....................................................................... 169
10.7.3. FWH INIT# Voltage Compatibility................................................................ 169
10.7.4. FWH V
PP
Design Guidelines........................................................................ 170
10.7.5. FWH INIT# Assertion/Deassertion Timings................................................. 170
10.8. RTC ............................................................................................................................. 171
10.8.1. RTC Crystal ................................................................................................. 172
10.8.2. External Capacitors ..................................................................................... 173
10.8.3. RTC Layout Considerations ........................................................................ 174
10.8.4. RTC External Battery Connections.............................................................. 174
10.8.5. RTC External RTCRST# Circuit .................................................................. 175
10.8.6. V
BIAS
DC Voltage and Noise Measurements ............................................... 176
10.8.7. SUSCLK....................................................................................................... 176
10.8.8. RTC-Well Input Strap Requirements ........................................................... 176
10.9. Internal LAN Layout Guidelines .................................................................................. 176
10.9.1. Footprint Compatibility ................................................................................. 177
10.9.2. Intel
®
82801DBM ICH4-M – LAN Connect Interface Guidelines ................. 178
10.9.2.1. Bus Topologies............................................................................. 178
10.9.2.1.1. LOM (LAN On Motherboard) Point-To-Point
Interconnect................................................................ 178
10.9.2.2. Signal Routing and Layout ........................................................... 179
10.9.2.3. Crosstalk Consideration ............................................................... 179
10.9.2.4. Impedances .................................................................................. 179
10.9.2.5. Line Termination........................................................................... 180
10.9.2.6. Terminating Unused LAN Connect Interface Signals................... 180
10.9.3. Intel 82562ET / Intel 82562EM Guidelines.................................................. 180
10.9.3.1. Guidelines for Intel 82562ET / Intel 82562EM Component
Placement..................................................................................... 180
10.9.3.2. Crystals and Oscillators................................................................ 180
10.9.3.3. Intel 82562ET / Intel 82562EM Termination Resistors................. 181
10.9.3.4. Critical Dimensions....................................................................... 181
10.9.3.4.1. Distance from Magnetics Module to RJ-45
(Distance A)................................................................ 182
10.9.3.4.2. Distance from Intel 82562ET / 82562ET to Magnetics
Module (Distance B)................................................... 182
10.9.3.5. Reducing Circuit Inductance ........................................................ 182
10.9.3.5.1. Terminating Unused Connections.............................. 183
10.9.3.5.2. Termination Plane Capacitance ................................. 183
10.9.4. Intel 82562ET/EM Disable Guidelines......................................................... 184
10.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM ............... 184
10.9.6. General Intel 82562ET/82562EM/82551QM/82540EP Differential Pair
Trace Routing Considerations ..................................................................... 185
10.9.6.1.1. Trace Geometry and Length ...................................... 186
10.9.6.1.2. Signal Isolation ........................................................... 186
10.9.6.1.3. Magnetics Module General Power and Ground Plane
Considerations............................................................ 187
10.9.6.2. Common Physical Layout Issues ................................................. 188
10.10. Power Management Interface ..................................................................................... 189
10.10.1. SYS_RESET# Usage Model ....................................................................... 189
10.10.2. PWRBTN# Usage Model............................................................................. 189
10.10.3. Power Well Isolation Control Strap Requirements ...................................... 189
10.11. CPU CMOS Considerations ........................................................................................ 190

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11.
Platform Clock Routing Guidelines...........................................................................................193
11.1. System Clock Groups ..................................................................................................193
11.2. Clock Group Topologies and Routing Constraints ......................................................195
11.2.1. Host Clock Group.........................................................................................195
11.2.1.1. Host Clock Group General Routing Guidelines ............................197
11.2.1.2. Clock to Clock Length Matching and Compensation....................197
11.2.1.3. EMI Constraints.............................................................................197
11.2.2. CLK66 Clock Group .....................................................................................198
11.2.3. Host Clock to CLK66 Routing Recommendations .......................................199
11.2.4. CLK33 Clock Group .....................................................................................200
11.2.5. PCI Clock Group ..........................................................................................201
11.2.6. CLK14 Clock Group .....................................................................................202
11.2.7. DOTCLK Clock Group..................................................................................203
11.2.8. SSCCLK Clock Group..................................................................................204
11.2.9. USBCLK Clock Group..................................................................................205
11.3. CK-408 Clock Power Supply Decoupling ....................................................................205
11.4. CK-408 PWRDWN# Signal Connections ....................................................................206
12. Platform Power Delivery Guidelines.........................................................................................207
12.1. Definitions ....................................................................................................................207
12.2. Platform Power Requirements.....................................................................................208
12.3. Voltage Supply.............................................................................................................209
12.3.1. Power Management States..........................................................................209
12.3.2. Power Supply Rail Descriptions...................................................................210
12.4. 852GME/852GMV/852PMGMCH/ICH4-M Platform Power-Up Sequence .................211
12.4.1. ICH4-M Power Sequencing Requirements..................................................213
12.4.1.1. 3.3 V/1.5 V Power Sequencing .....................................................213
12.4.1.2. V
5REF
/ 3.3 V Sequencing................................................................213
12.4.1.3. V
5REF_SUS
Design Guidelines .........................................................214
12.4.2. GMCH Power Sequencing Requirements ...................................................215
12.4.3. DDR Power Sequencing Requirements ......................................................215
12.4.4. PWR ICH4-M SYS_RESET# Signal ............................................................216
12.5. DDR Power Delivery Design Guidelines .....................................................................216
12.5.1. DDR Interface Decoupling Guidelines .........................................................217
12.5.1.1. GMCH VCCSM Decoupling Guidelines........................................217
12.5.1.2. DDR SO-DIMM System Memory Decoupling Guidelines.............218
12.5.2. 2.5-V Power Delivery Guidelines .................................................................218
12.5.3. DDR Reference Voltage...............................................................................218
12.5.3.1. SMVREF Layout and Routing Recommendations........................220
12.5.3.2. DDR VREF Requirements ............................................................222
12.5.4. DDR SMRCOMP Resistive Compensation .................................................222
12.5.5. DDR VTT Termination..................................................................................223
12.6. Clock Driver Power Delivery Guidelines......................................................................224
12.7. Decoupling Recommendations....................................................................................226
12.7.1. Processor Decoupling Guidelines................................................................226
12.7.2. Intel 852GME/852GMV/852PMGMCH Decoupling Guidelines ...................226
12.7.3. Intel ICH4-M Decoupling Guidelines............................................................227
12.7.4. DDR VTT High Frequency and Bulk Decoupling.........................................228
12.7.5. Hub Interface Decoupling.............................................................................229
12.7.6. FWH Decoupling ..........................................................................................229
12.7.7. General LAN Decoupling .............................................................................229

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12.7.8.
CK-408 Clock Driver Decoupling................................................................. 229
12.8. Intel 852GME/852GMV/852PMGMCH Analog Power Delivery.................................. 230
12.8.1. Analog Supply Filter Requirements ............................................................. 230
12.8.2. Recommended Routing/Component Placement......................................... 231
12.9. Intel 852GME/852GMV/852PMMaximum Supply Current Numbers .......................... 231
12.10. Intel ICH4-M Power Consumption Numbers ............................................................... 232
12.11. Thermal Design Power................................................................................................ 233
13. Test Signals ............................................................................................................................. 234
13.1. Mobile Intel Pentium 4 Processor Reserved Signals .................................................. 234
13.2. Intel 852GME / 852PM GMCH RSVD Signals ............................................................ 235
14. Platform Design Checklist........................................................................................................ 236
14.1. General Information..................................................................................................... 236
14.2. Customer Implementation of Voltage Rails................................................................. 237
14.3. Design Checklist Implementation................................................................................ 238
14.4. In Target Probe (ITP) .................................................................................................. 242
14.5. Decoupling Recommendations ................................................................................... 242
14.6. Power-up Sequence.................................................................................................... 243
14.7. CK-408 Clock Checklist............................................................................................... 245
14.7.1. Resistor Recommendations ........................................................................ 245
14.8. 852GME/852GMV/852PMChecklist............................................................................ 247
14.8.1. System Memory........................................................................................... 247
14.8.1.1. GMCH System Memory Interface ................................................ 247
14.8.1.2. DDR SO-DIMM Interface.............................................................. 248
14.8.1.3. SO-DIMM Decoupling Recommendation ..................................... 250
14.8.2. FSB .............................................................................................................. 250
14.8.3. Hub Interface ............................................................................................... 251
14.8.4. Graphics Interfaces...................................................................................... 251
14.8.4.1. LVDS ............................................................................................ 251
14.8.4.2. AGP/DVO ..................................................................................... 251
14.8.4.3. DAC .............................................................................................. 255
14.8.5. Miscellaneous .............................................................................................. 256
14.8.6. GMCH Decoupling Recommendations ....................................................... 257
14.8.7. GMCH Power-up Sequence ........................................................................ 258
14.9. ICH4-M Checklist ........................................................................................................ 259
14.9.1. PCI Interface and Interrupts ........................................................................ 259
14.9.2. GPIO ............................................................................................................ 261
14.9.3. AGP_BUSY# Design Requirement ............................................................. 262
14.9.4. (SMBus) System Management Interface .................................................... 262
14.9.5. AC ’97 Interface ........................................................................................... 263
14.9.6. ICH4-M Power Management Interface........................................................ 264
14.9.7. FWH/LPC Interface...................................................................................... 265
14.9.8. USB Interface .............................................................................................. 265
14.9.9. Hub Interface ............................................................................................... 265
14.9.10. RTC Circuitry ............................................................................................... 268
14.9.11. LAN Interface............................................................................................... 269
14.9.12. Primary IDE Interface .................................................................................. 269
14.9.13. Secondary IDE Interface ............................................................................. 270
14.9.14. Miscellaneous Signals ................................................................................. 270
14.9.15. ICH4-M Decoupling Recommendations ...................................................... 271

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852PM and Intel
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14.9.16.
ICH4-M Power-up Sequence .......................................................................272
14.10. USB Power Checklist...................................................................................................274
14.10.1. Downstream Power Connection ..................................................................274
14.11. FWH Checklist .............................................................................................................275
14.11.1. Resistor Recommendations.........................................................................275
14.12. LAN/HomePNA Checklist ............................................................................................275
14.12.1. Resistor Recommendations (for 82562ET / 82562 EM) ..............................275
14.12.2. Decoupling Recommendations ....................................................................276
15. Schematics ...............................................................................................................................277

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12 Intel
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852GMV and Intel
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852PM Chipset Platforms Design Guide
Figures
Figure 1. Intel 852GME GMCH System Block Diagram .......................................................... 29
Figure 2. Intel 852PM Chipset System Block Diagram............................................................ 32
Figure 3. Intel 852GMV GMCH System Block Diagram .......................................................... 36
Figure 4. Recommended Board Stack-Up Dimensions ........................................................... 38
Figure 5. Cross-Sectional View of 2:1 Ratio ............................................................................ 42
Figure 6. Cross-Sectional View of 2.5:1 Ratio ......................................................................... 43
Figure 7. Processor Topology.................................................................................................. 45
Figure 8. SS Topology for Address and Data .......................................................................... 46
Figure 9. Routing Illustration for Topology 1A ......................................................................... 47
Figure 10. Routing Illustration for Topology 1B ....................................................................... 48
Figure 11. Routing Illustration for Topology 1C ....................................................................... 49
Figure 12. Routing Illustration for Topology 2A ....................................................................... 50
Figure 13. Routing Illustration for Topology 2B ....................................................................... 51
Figure 14. Routing Illustration for Topology 2C ....................................................................... 52
Figure 15. Routing Illustration for Topology 3.......................................................................... 53
Figure 16. Voltage Translation Circuit for 3.3-V Receivers ..................................................... 54
Figure 17. Routing Recommendation for COMP[1:0] .............................................................. 55
Figure 18. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector... 56
Figure 19. Processor RESET# Signal Routing Topology with ITP700FLEX Connector ......... 56
Figure 20. Memory Clock Routing Topology SCK/SCK#[5:0] ................................................. 67
Figure 21. Memory Clock Trace Length Matching Diagram .................................................... 70
Figure 22. Clock Signal Routing Example ............................................................................... 72
Figure 23. Data Signal Routing Topology................................................................................ 74
Figure 24. SDQS to Clock Trace Length Matching Diagram................................................... 76
Figure 25. SDQ/SDM to SDQS Trace Length Matching Diagram ........................................... 78
Figure 26. Data Signals Group Routing Example.................................................................... 80
Figure 27. Control Signal Routing Topology............................................................................ 82
Figure 28. Control Signal to Clock Trace Length Matching Diagram ...................................... 84
Figure 29. Control Signals Group Routing Example................................................................ 85
Figure 30. Command Routing for Topology 1.......................................................................... 87
Figure 31. Topology 1 Command Signal to Clock Trace Length Matching Diagram .............. 90
Figure 32. Command Routing Topology 2 ............................................................................... 91
Figure 33. Topology 2 Command Signal to Clock Trace Length Matching Diagram .............. 94
Figure 34. Example of Command Signal Group ...................................................................... 95
Figure 35. Command Routing Topology 3 ............................................................................... 96
Figure 36. Topology 3 Command Signal to Clock Trace Length Matching Diagram .............. 99
Figure 37. Command per Clock Signal Routing Topology ....................................................102
Figure 38. CPC Signals to Clock Length Matching Diagram................................................. 104
Figure 39. DDR Memory Thermal Sensor Placement ........................................................... 108
Figure 40. Rset Placement .................................................................................................... 110
Figure 41. GMCH DAC Routing Guidelines with Docking Connector ................................... 111
Figure 42. DAC R, G, B Routing and Resistor Layout Example............................................ 113
Figure 43. DVOB and DVOC Simulations Model................................................................... 123
Figure 44. Driver-Receiver Waveforms Relationship Specification ....................................... 123
Figure 45. DVO Enabled Simulation Model ...........................................................................124
Figure 46. Generic Module Connector Parasitic Model.........................................................125
Figure 47. GVREF Reference Voltage................................................................................... 127
Figure 48. AGP Layout Guidelines ........................................................................................132
Figure 49. DPMS Circuit ........................................................................................................139
Figure 50. Hub Interface Routing Example............................................................................ 140

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Figure 51. Single VREF/VSWING Voltage Generation Circuit for Hub Interface ................. 144
Figure 52. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit......... 145
Figure 53. Shared GMCH and ICH4-M Reference Voltage with Separate Voltage Divider
Circuit for VSWING and VREF .............................................................................. 145
Figure 54. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits
for ICH4-M and GMCH .......................................................................................... 146
Figure 55. Connection Requirements for Primary IDE Connector ........................................ 149
Figure 56. Connection Requirements for Secondary IDE Connector ................................... 150
Figure 57. PCI Bus Layout Example ..................................................................................... 153
Figure 58. Intel 82801DBM ICH4-M AC’97 – Codec Connection ......................................... 154
Figure 59. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ................................. 155
Figure 60. Intel 82801DBM AC’97 – AC_SDOUT/AC_SYNC Topology............................... 155
Figure 61. Intel 82801DBM AC’97 – AC_SDIN Topology ..................................................... 156
Figure 62. Example Speaker Circuit...................................................................................... 159
Figure 63. Recommended USB Trace Spacing .................................................................... 160
Figure 64. USBRBIAS Connection........................................................................................ 161
Figure 65. Good Downstream Power Connection................................................................. 163
Figure 66. Common Mode Choke Schematic ....................................................................... 163
Figure 67. SMBUS 2.0/SMLink Protocol ............................................................................... 166
Figure 68. High Power/Low Power Mixed V
CC
_
SUSPEND
/V
CC
_
CORE
Architecture ..................... 167
Figure 69. FWH VPP Isolation Circuitry ................................................................................ 170
Figure 70. RTCX1 and SUSCLK Relationship in ICH4-M..................................................... 171
Figure 71. External Circuitry for the ICH4-M Where the Internal RTC is Not Used .............. 171
Figure 72. External Circuitry for the ICH4-M RTC................................................................. 172
Figure 73. Diode Circuit to Connect RTC External Battery ................................................... 175
Figure 74. RTCRST# External Circuit for the ICH4-M RTC .................................................. 175
Figure 75. Intel 82801DBM ICH4-M/Platform LAN Connect Section.................................... 177
Figure 76. Single Solution Interconnect ................................................................................ 178
Figure 77. LAN_CLK Routing Example................................................................................. 179
Figure 78. Intel 82562ET / Intel 82562EM Termination ........................................................ 181
Figure 79. Critical Dimensions for Component Placement ................................................... 181
Figure 80. Termination Plane ................................................................................................ 183
Figure 81. Intel 82562ET/EM Disable and Power Down Circuitry ........................................ 184
Figure 82. Trace Routing....................................................................................................... 186
Figure 83. Ground Plane Separation..................................................................................... 187
Figure 84. RTC Power Well Isolation Control........................................................................ 190
Figure 85. ICH4-M CPU CMOS Signals with CPU and FWH ............................................... 191
Figure 86. Clock Distribution Diagram................................................................................... 194
Figure 87. Source Shunt Termination Topology ................................................................... 195
Figure 88. CLK66 Clock Group Topology ............................................................................. 198
Figure 89. BCLK to GCLKIN Timing Requirement................................................................ 199
Figure 90. CLK33 Group Topology ....................................................................................... 200
Figure 91. PCI Clock Group Topology .................................................................................. 201
Figure 92. CLK14 Clock Group Topology ............................................................................. 202
Figure 93. DOTCLK Clock Topology..................................................................................... 203
Figure 94. SSCCLK Clock Topology ..................................................................................... 204
Figure 95. USBCLK Clock Topology ..................................................................................... 205
Figure 96. Platform Power Delivery Architectural Block Diagram......................................... 208
Figure 97. GMCH / ICH4-M Platform Power-Up Sequence .................................................. 211
Figure 98. Power On Sequencing Timing Diagram (VR Circuitry)........................................ 213
Figure 99. Example V
5REF
/ 3.3 V Sequencing Circuitry ......................................................... 214
Figure 100. V5REF_SUS with 5V_ALWAYS Connection Option (Recommended) ............. 214

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14 Intel
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852GME, Intel
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852GMV and Intel
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852PM Chipset Platforms Design Guide
Figure 101. V5REF_SUS with 3.3V_ALWAYS and VCC5 or VCC5_SUS Connection
Option .....................................................................................................................215
Figure 102. DDR Power Delivery Block Diagram ..................................................................217
Figure 103. DDR SMRCOMP Resistive Compensation ........................................................ 223
Figure 104. SMVSWINGL and SMVSWINGH Reference Voltage Generation Circuit..........223
Figure 105. Decoupling Capacitors Placement and Connectivity.......................................... 225
Figure 106. Minimized Loop Inductance Example................................................................. 228
Figure 107. Example Analog Supply Filter............................................................................. 230
Figure 108. Routing Illustration for INIT# ............................................................................... 241
Figure 109. VCCIOPLL, VCCA and VSSA Power Distribution.............................................. 241
Figure 110. Voltage Translation Circuit for PROCHOT# .......................................................241
Figure 111. Mobile Intel Pentium 4 Processor Power Up Sequence..................................... 244
Figure 112. Clock Power-down Implementation ....................................................................246
Figure 113. Reference Voltage Level for SMVREF ............................................................... 248
Figure 114. 852GME HXSWING & HYSWING Reference Voltage Generation Circuit ........250
Figure 115. DPMS Clock Implementation..............................................................................253
Figure 116. Q-SWITCH Circuit .............................................................................................. 254
Figure 117. 852GME Power-up Sequence............................................................................ 258
Figure 118. Separated GMCH and ICH4-M VSWING/VREF Reference Voltage Circuit...... 266
Figure 119. Single or Locally Generated GMCH & ICH4-M HIVREF/HI_VSWING
Circuit......................................................................................................................267
Figure 120. Single Generated GMCH and ICH4-M VSWING/VREF Reference
Voltage/ Local Voltage Divider Circuit for VSWING/VREF .................................... 267
Figure 121. External Circuitry for the RTC............................................................................. 268
Figure 122. ICH4 Power-up Sequence Waveforms............................................................... 273
Figure 123. Good Downstream Power Connection ............................................................... 274
Figure 124. LAN_RST# Design Recommendation ................................................................ 276

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Tables
Table 1. System Bus Routing Summary for the Processor..................................................... 41
Table 2. Processor System Bus Data Signal Routing Guidelines........................................... 45
Table 3. Processor System Bus Address Signal Routing Guidelines ..................................... 45
Table 4. Processor System Bus Control Signal Routing Guidelines....................................... 46
Table 5. Layout Recommendations for Topology 1A .............................................................. 47
Table 6. Layout Recommendations for Topology 1B .............................................................. 48
Table 7. Layout Recommendations for Topology 1C.............................................................. 49
Table 8. Layout Recommendations for Topology 2A .............................................................. 50
Table 9. Layout Recommendations for Topology 2B .............................................................. 51
Table 10. Layout Recommendations for Topology 2C............................................................ 52
Table 11. Layout Recommendations for Topology 3 .............................................................. 53
Table 12. Layout Recommendation for COMP[1:0] ................................................................ 55
Table 13. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector........ 57
Table 14. Mobile Intel Pentium 4 Processor and 852GME Chipset Package Lengths........... 58
Table 15. GMCH/MCH Chipset Memory Signal Groups ......................................................... 65
Table 16. Intel 852GME/852GMV/852PMChipset GMCH/MCH DDR 333 Length Matching
Formulas .................................................................................................................. 66
Table 17. Clock Signal Mapping.............................................................................................. 67
Table 18. Clock Signal Group Routing Guidelines.................................................................. 68
Table 19. Memory Clock Package Lengths............................................................................. 71
Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing
Guidelines ................................................................................................................ 74
Table 21. SDQ/SDM to SDQS Mapping.................................................................................. 77
Table 22. Memory SDQ/SDM/SDQS Package Lengths ......................................................... 79
Table 23. Control Signal to SO-DIMM Mapping ...................................................................... 81
Table 24. Control Signal Routing Guidelines .......................................................................... 82
Table 25. Control Group Package Lengths............................................................................. 86
Table 26. Command Topology 1 Routing Guidelines ............................................................. 88
Table 27. Command Topology 2 Routing Guidelines ............................................................. 92
Table 28. Command Topology 3 Routing Guidelines ............................................................. 97
Table 29. Command Group Package Lengths...................................................................... 100
Table 30. CPC Signal to SO-DIMM Mapping ........................................................................ 101
Table 31. CPC Signal Routing Guidelines ............................................................................ 102
Table 32. CPC Group Package Lengths ............................................................................... 104
Table 33. Recommended GMCH DAC Components............................................................ 112
Table 34. Signal Group and Signal Pair Names ................................................................... 115
Table 35. LVDS Signal Group Routing Guidelines ............................................................... 116
Table 36. LVDS Package Lengths ........................................................................................ 117
Table 37. DVO Interface Trace Length Mismatch Requirements ......................................... 119
Table 38. DVOB and DVOC Routing Guideline Summary.................................................... 120
Table 39. DVOB Interface Package Lengths ........................................................................ 121
Table 40. DVOC Interface Package Lengths ........................................................................ 122
Table 41. Allowable Interconnect Skew Calculation ............................................................. 124
Table 42. DVO Enabled Routing Guideline Summary .......................................................... 125
Table 43. GMBUS Pair Mapping and Options....................................................................... 126
Table 44. AGP 2.0 Signal Groups ......................................................................................... 129
Table 45. AGP 2.0 Data/Strobe Associations ....................................................................... 130
Table 46. Layout Routing Guidelines for AGP 1X Signals .................................................... 131
Table 47. Layout Routing Guidelines for AGP 2X/4X Signals............................................... 133

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852GME, Intel
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852GMV and Intel
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Table 48. AGP 2.0 Data Lengths Relative to Strobe Length ................................................. 133
Table 49. AGP 2.0 Routing Guideline Summary ................................................................... 134
Table 50. AGP Interface Package Lengths ...........................................................................135
Table 51. AGP Pull-Up/Pull-Down Requirements and Straps ...............................................137
Table 52. AGP 2.0 Pull-up Resistor Values...........................................................................137
Table 53. Hub Interface RCOMP Resistor Values................................................................. 140
Table 54. Hub Interface Signals Internal Layer Routing Summary ....................................... 141
Table 55. Hub Interface Package Lengths for ICH4-M..........................................................142
Table 56. Hub Interface Package Lengths for GMCH ...........................................................142
Table 57. Hub Interface VREF/VSWING Reference Voltage Specifications......................... 143
Table 58. Recommended Resistor Values for Single VREF/VSWING Divider Circuit.......... 144
Table 59. Recommended Resistor Values for Separate HIVREF and HI_VSWING
Divider Circuits ....................................................................................................... 145
Table 60. Recommended Resistor Values for HIVREF and HI_VSWING Divider
Circuits for ICH4-M ................................................................................................. 146
Table 61. AC’97 AC_BIT_CLK Routing Summary................................................................. 155
Table 62. AC’97 AC_SDOUT/AC_SYNC Routing Summary ................................................156
Table 63. AC’97 AC_SDIN Routing Summary....................................................................... 156
Table 64. Supported Codec Configurations........................................................................... 158
Table 65. USBRBIAS/USBRBIAS# Routing Summary.......................................................... 161
Table 66. USB 2.0 Trace Length Guidelines (With Common-mode Choke) ......................... 161
Table 67. Bus Capacitance Reference Chart ........................................................................ 168
Table 68. Bus Capacitance/Pull-Up Resistor Relationship....................................................168
Table 69. RTC Routing Summary.......................................................................................... 172
Table 70. LAN Component Connections/Features ................................................................ 177
Table 71. LAN Design Guide Section Reference .................................................................. 178
Table 72. LAN LOM Routing Summary ................................................................................. 179
Table 73. Intel 82562ET/EM Control Signals......................................................................... 184
Table 74. Individual Clock Breakdown...................................................................................193
Table 75. Host Clock Group Routing Constraints.................................................................. 196
Table 76. CLK66 Clock Group Routing Constraints ..............................................................198
Table 77. CLK33 Clock Group Routing Constraints ..............................................................200
Table 78. PCICLK Clock Group Routing Constraints ............................................................ 201
Table 79. CLK14 Clock Group Routing Constraints ..............................................................202
Table 80. DOTCLK Clock Routing Constraints...................................................................... 203
Table 81. SSCCLK Clock Routing Constraints...................................................................... 204
Table 82. USBCLK Clock Routing Constraints...................................................................... 205
Table 83. Power Management States.................................................................................... 209
Table 84. Power Supply Rail Descriptions............................................................................. 210
Table 85. Timing Sequence Parameters for Figure 97..........................................................212
Table 86. Timing Sequence Parameters for Figure 98..........................................................213
Table 87. DDR Power-Up Initialization Sequence ................................................................. 216
Table 88. Absolute vs. Relative Voltage Specification........................................................... 219
Table 89. DDR-SDRAM SO-DIMM Voltage and Current Requirements............................... 219
Table 90. Intel GMCH System Memory Voltage and Current Requirements ........................ 220
Table 91. Termination Voltage and Current Requirements ...................................................220
Table 92. GMCH System Memory I/O SMVREF Calculation ................................................221
Table 93. Effects of Varying Resistor Values in the Divider Circuit ....................................... 221
Table 94. DDR VREF Calculation.......................................................................................... 222
Table 95. Reference Distortion Due to Load Current ............................................................ 222
Table 96. Processor Decoupling Recommendation .............................................................. 226
Table 97. GMCH Decoupling Recommendations.................................................................. 226
Table 98. Decoupling Requirements for the Intel ICH4-M.....................................................228

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Table 99. Analog Supply Filter Requirements....................................................................... 231
Table 100. Icc Maximum Sustained Estimates (Icc REV0.3)................................................ 232
Table 101. Intel ICH4-M Power Consumption Measurements.............................................. 232
Table 102. Intel 852GME/852GMV/852PMGMCH Component Thermal Design Power ...... 233
Table 103. Intel ICH4-M Component Thermal Design Power............................................... 233
Table 104. GMCH “Intel Reserved” Signal Pin-Map Locations............................................. 235
Table 105. GST[2:0] Configurations...................................................................................... 256
Table 106. ICH4-M Power-up Timing Specifications ............................................................ 272

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852GMV and Intel
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852PM Chipset Platforms Design Guide
Revision History
Rev. Document
Number Description Date
-001 253026 Initial Release June 2003
-002 253026 Updates include:
Added information for 852GMV
February 2004
-003 253026 Updates include:
Added information for Mobile Intel Pentium 4 Processor supporting
Hyper-Threading Technology on 90-nm process technology
May 2004
-004 253026 Updates include:
Added information for Intel Celeron D Processor on 90 nm
process and in the 478-pin package
June 2004

Introduction
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Intel
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852GME, Intel
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852GMV and Intel
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852PM Chipset Platforms Design Guide 19
1. Introduction
This design guide provides Intel design recommendations for the Intel
®
852GME, Intel
®
852GMV
GMCH and the Intel
®
852PM MCH chipset based systems. These design guidelines ensure maximum
flexibility for board designers while reducing the risk of board related issues. The Intel 852GME, Intel
852GMV and Intel 852PM chipsets are pin compatible. Carefully follow the design information and
debug recommendations in this document.
The Mobile Intel
®
Pentium
®
4 processor, Mobile Intel
®
Pentium
®
4 processor supporting Hyper-
Threading Technology on 90-nm process technology, Intel
®
Celeron
®
processor, or the Intel
®
Celeron
®
D processor on 90 nm process and in the 478-pin package in combination with the 852GME, 852GMV
or 852PM deliver high performance and professional mobile platform solution using internal and/or
external graphics. Section 2 provides an overview of system features of supported processor and chipset
combinations.
All recommendations will apply to all platforms unless specified. Any references to GMCH apply to all
platforms unless otherwise specified. Any reference to Mobile Intel Pentium 4 processor apply to
Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process
technology unless specified. Any reference to the Intel
®
Celeron
®
processor applies to the Intel
®
Celeron
®
D processor on 90 nm process and in the 478-pin package unless specified.

Introduction
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20 Intel
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852GME, Intel
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852GMV and Intel
®
852PM Chipset Platforms Design Guide
1.1. Referenced Documents
Document Document No./Location
Mobile Intel
®
Pentium
®
4 Processor Datasheet http://developer.intel.com/
Mobile Intel
®
Pentium
®
4 Processor supporting Hyper-
Threading Technology on 90-nm process technology
Datasheet
http://developer.intel.com/
Intel
®
Celeron
®
Processor on .13 Micron Process
Datasheet http://developer.intel.com/
Intel
®
Celeron
®
D Processor on 90 nm Process and in the
478-pin Package Datasheet http://developer.intel.com/
Intel
®
852GME Chipset GMCH and Intel
®
852PM Chipset
MCH Datasheet http://developer.intel.com/
Intel
®
852GME and Intel
®
852PM Chipset GMCH
Specification Update http://developer.intel.com/
Intel
®
852GM/852GMV Chipset GMCH Datasheet http://developer.intel.com/
Intel
®
852GM/852GMV Chipset GMCH Specification
Update http://developer.intel.com/
Intel
®
I/O Controller Hub -Mobile(ICH4-M) Datasheet http://developer.intel.com/
Intel
®
I/O Controller Hub-Mobile (ICH4-M) Specification
Update http://developer.intel.com/
Intel
®
DDR 200 JEDEC Spec Addendum Rev 0.9 or later http://developer.intel.com/
Application Note AP-728: ICH/ICH2/ICH2M/ICH4S/ICH4M
Real Time Clock (RTC) Accuracy and Considerations
Under Test Conditions
http://developer.intel.com/
ITP700 Debug Port Design Guide http://developer.intel.com/
JEDEC Standard, JESD79, Double Data Rate (DDR)
SDRAM Specification http://www.jedec.org/
PC2100 DDR SDRAM Unbuffered SO-DIMM Reference
Design Specification http://www.jedec.org/