Intel INTELLEC Quick user guide

INTELLECT DOUBLEDENSITY
DISKETTEOPERATINGSYSTEM
HARDWARE REFERENCE MANUAL
Copyright © 1977 Intel Corporation
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PREFACE
This reference manual isthe primarysource of information forthe hardware
within the INTELLEC DoubleDensityDisketteOperatingSystem. It explains
how the DisketteSystem is installed, howit communicates with the INTELLEC
Microcomputer DevelopmentSystem, andhowit functions internally.
Refer tothe ISIS-II System User's Guide(ordernumber98-306) for complete
instructions onhowto operate the DisketteSystem. For information onthe
V J hostsystem, refer tothe INTELLECMicrocomputerDevelopmentSystemHard-
ware Reference Manual andtothe INTELLEC MicrocomputerDevelopment
SystemOperator'sManual.
Hi

Chapter
Title
TABLE OF CONTENTS
Page Chapter Title
Page
INTRODUCTION 1-1
1.1 SYSTEMOVERVIEW 1-1
1.2 RECORDINGFORMAT 1-4
OPERATIONAL SUMMARY AND
PROGRAMMINGCONSIDERATIONS
2-1
2.1 CHANNELCOMMANDS 2-2
2.2 DISKETTEOPERATIONS 2-5
2.3I/O PARAMETERBLOCK 2-8
2.4 ERROR INDICATIONS 2-11
THE CHANNEL BOARD 3-1
3.1 FUNCTIONALORGANIZATION OF
THE CHANNEL BOARD 3-1
3.2 THEORY OF OPERATION:
CHANNELBOARD 3-3
3.2.1CHANNEL COMMAND BLOCK . 3-3
3.2.2MICROCONTROL UNIT (MCU)
BLOCK 3-5
3.2.3MICROPROGRAMMEMORY
BLOCK 3-8
3.2.4CENTRAL PROCESSING ELEMENT
(CPE) BLOCK 3-12
3.2.5DATA/CLOCK SHI FT REGISTER
BLOCK 3-15
3.2.6DATAFLOWCONTROLBLOCK . 3-16
3.3 SCHEMATICS/PIN LISTS: CHANNEL
BOARD 3-17
THE INTERFACE BOARD 4-1
4.1 FUNCTIONALORGANIZATION OF
THE INTERFACE BOARD 4-1
4.2 THEORY OF OPERATION:INTERFACE
BOARD 4-3
4.2.1DISKDRIVECONTROL .... 4-3
4.2.2WRITE DATA GENERATOR .. 4-6
4.2.3SERIALDATA/CLOCK
SYNCHRONIZATION 4-10
4.2.4 CYCLIC REDUNDANCY CHECK
(CRC) 4-10
4.2.5 BUS CONTROL 4-13
4.3 SCHEMATICS/PINLISTS:
INTERFACE BOARD 4-15
THE DISKETTEDRIVES 5-1
5.1 FUNCTIONALDESCRIPTION 5-1
5.2 PERFORMANCECHARACTERISTICS ..5-2
5.2.1RECORDINGCHARAC-
TERISTICS 5-2
5.2.2 BIT TRANSFERRATE :'.... 5-2
5.2.3 DATA CAPACITY 5-2
5.2.4LATENCYTIME 5-3
5.2.5POSITIONINGCHARAC-
TERISTICS 5-3
5.2.6 FDD START AND STOP
TIME 5-3
'- ''•' 5.2.7 ERRORRECOVERY 5-3
-**«'• 5.2.8 ENVIRONMENTALLIMITS •-• 5-4
5.2.9WRITEPROTECT 5-4
5.3 INTERFACESPECIFICATIONS 5-4
5.4 DISKETTECARTRIDGESTORAGE
AND HANDLING 5-9
5.5 DISKETTECARTRIDGEWRITE
PROTECT NOTCH 5-11
5.6 ADDITIONALINFORMATION 5-11
DISKETTESYSTEMMICROPROGRAM
6-1
6.1 INTRODUCTION 6-1
6.2 MICROPROGRAM MODULE
DESCRIPTION 6-1
7 UTILIZATION 7-1
7.1 ENVIRONMENTALEXTREMES 7-1
7.2 MOUNTING RECOMMENDATIONS ... 7-1
7.3 ELECTRICALCONNECTIONS 7-1
7.4 BASEADDRESSSELECTION 7-2
7.5 INTERRUPTLEVELSELECTION .... 7-2
8 OPERATINGCHARACTERISTICS 8-1
8.1AC CHARACTERISTICS 8-1
8.2DC CHARACTERISTICS 8-9
-IV

LIST OF ILLUSTRATIONS
Chapter Title Page
1 INTRODUCTION 1-1
1-1 DISKETTESYSTEMBLOCKDIAGRAM 1-2
1-2 PHYSICALDATAFORMAT 1-6
1-3 BYTEREPRESENTATION 1-7
1-4 DATA BYTES 1-7
1-5 DATA BIT1-8
1-6 BIT CELL 1-8
1-7 TRACKFORMAT 1-9
1-8 INDEXADDRESSMARK1-10
1-9 ID ADDRESSMARK1-10
1-10 DATA ADDRESSMARK1-11
1-11 DELETED DATA ADDRESSMARK1-11
2 OPERATIONAL SUMMARY AND PROGRAMMINGCONSIDERATIONS 2-1
2-1 SECTOR FORMAT 2-7
2-2 'DATA' ADDRESSMARK 2-7
2-3 'DELETED DATA' ADDRESSMARK 2-7
2-4 I/O PARAMETERBLOCK (IOPB) FORMAT 2-9
3 CHANNELBOARD 3-1
3-1 CHANNELBOARD:FUNCTIONALBLOCKDIAGRAM 3-2
3-2 3001MICROPROGRAMCONTROL UNIT: FUNCTIONALBLOCK
DIAGRAM 3-6
3-3 3002 CENTRAL PROCESSING ELEMENT:FUNCTIONALBLOCK
DIAGRAM3-14
3-4 SCHEMATICDRAWING:CHANNELBOARD3-21
4 INTERFACEBOARD 4-1
4-1 INTERFACEBOARD:FUNCTIONALBLOCKDIAGRAM 4-2
4-2 HEADMOVEMENTCONTROLTIMING 4-5
4-3 READ INITIATE TIMING 4-6
4-4 M2FM DATAENCODING 4-7
4-5 PRECOMPENSATION TIMING 4-8
4-6 WRITEDATATIMING 4-9
4-7 PHASELOCKEDOSCILLATOR4-11
4-8 READSYNCHRONIZATIONTIMING4-12
4-9BUS CONTROLTIMING4-14
4-10 CLK1/ AND CLK2/ TIMING4-15
4-11 SCHEMATICDRAWING:INTERFACEBOARD4-22
5 DISKETTEDRIVES 5-1
5-1 FDD/FDCCINTERFACELINES 5-6
5-2 FDD DRIVER/RECEIVERCIRCUITS 5-7
5-3 WRITEDATATIMING 5-8
5-4 READ DATA TIMING5-10
5-5 FLEXIBLEDISKCARTRIDGE 5-11

LIST OF ILLUSTRATIONS (Continued)
Chapter Title Page
6 DISKETTESYSTEMMICROPROGRAM 6-1
6-1 INITIALIZATION 6-2
6-2 MAINLINE 6-3
6-3 LOAD MA LOWER 6-4
6-4 LOAD MA UPPER AND START I/O6-5
6-5 READRESULTBYTE 6-6
' 6-6 IOPBLOADER/OPDECODE 6-7
6-7 I/O FINISH 6-8
6-8 SEEK 6-9
6-9 FORMAT6-10
6-10RECALIBRATE6-12
6-11 VERIFY/READ6-13
6-12WRITEDELETED/WRITE6-15
6-13ADDRESSPARAMETERCHECKER6-16
6-14READNEXTMEMORYWORD6-17
6-15WRITE DATA FIELD 6-18
6-16WRITECURRENTCHECK6-19
"" 6-17 TIME-OUT 6-20
6-18ADDRESS MARK DETECT 6-21
6-19HEAD STEPPER 6-22
6-20READDISKBYTE6-23
6-21 PROCESS ADDRESS FIELD 6-24
6-22WRITEADDRESS FIELD 6-25
7 UTILIZATION 7-1
7-1 CONNECTORS ON THE CHANNEL AND INTERFACE BOARDS 7-3
8 OPERATINGCHARACTERISTICS 8-1
'8-1 SLAVECOMMAND TIMING - FDCC 8-2
8-2BUS EXCHANGE TIMING 8-3
8-3 ' MASTERCOMMAND TIMING 8-4
-8-4 STEP/SETTLING TIMINGS 8-6
8-5 READ TIMING 8-7
xB-6 WRITE TIMING 8-7
: 3-7 INDEX TIMING 8-8
WRITE FAULT RESET TIMING 8-8
VI

LIST OF TABLES
Chapter Title Page
1 INTRODUCTION
1-1 DISKETTEDRIVEPERFORMANCESPECIFICATIONS 1-3
2 OPERATIONALSUMMARY AND PROGRAMMINGCONSIDERATIONS
2-1 INTERRUPTCONTROLBITS 2-11
3THE CHANNELBOARD
3-1 AGO INPUT SELECTION 3-7
3-2 MICROINSTRUCTION BIT ASSIGNMENTS 3-9
3-3 CONTROL PULSES AND LEVELS GENERATED BY MICROPROGRAM 3-10
3-4 I-BUS SELECTION BY MASK FIELD BITS 3-12
3-5 K-BUS INPUT SELECTION 3-13
3-6 PIN LIST: P1BUS CONNECTOR 3-17
3-7 PIN LIST: P2 CONTROLLERCONNECTOR 3-19
4THE INTERFACEBOARD
4-1 PIN LIST: P1BUS CONNECTOR 4-16
4-2 PIN LIST: P2 CONTROLLERCONNECTOR 4-18
4-3 J1 DRIVECONNECTOR 4-19
8 OPERATINGCHARACTERISTICS
8-1 DISKETTEOPERATINGSYSTEM/INTELLEC BUSAC CHARACTERISTICS 8-1
8-2 DISKETTEOPERATINGSYSTEM/DRIVEINTERFACE AC CHARACTERISTICS ... 8-5
8-3 DISKETTEOPERATINGSYSTEM DC CHARACTERISTICS(INTELLECBUS) 8-9
8-4 DISKETTEOPERATINGSYSTEM DC CHARACTERISTICS(DRIVE/DISPLAY
INTERFACE) 8-12
VII

-•*:-. ' *
w. Jl "»•'

CHAPTER 1
INTRODUCTION
The INTELLEC Double DensityDiskette Operating Systemprovides a bulk storage capability for Intel's INTELLEC
Microcomputer DevelopmentSystem. The DisketteSystemincludes an intelligentcontroller andupto four diskette
drives. Eachdriveprovides 4,100,096 user-accessible databits of storage with a datatransferrate of 500,000 bits/
second. The controller has beenimplemented with Intel'spowerful Series 3000 Bipolar Computing Elements. The
controller provides an interface tothe INTELLEC Systembus, as well as supporting the four diskette drives. The
DisketteSystemrecords all data inthe Intelsoft-sectored format, described in Section 1.2.
1.1 SYSTEMOVERVIEW
r 4
'- f
In addition totwoor four diskettedrives, their enclosure(s) (twodrives per enclosure) and powersupplies, the
DisketteSystem consists ofthe ChannelBoard andthe InterfaceBoard.These two printed circuit boards reside in
the INTELLEC Systemcabinet and constitute the diskettecontroller.Each ofthe systemcomponents is shown in
\
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. ,3 . ., ... ...~ .~,.~ 3, g.-, - ^ \
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1, i * 5
The ChannelBoard is the primary control module within the DisketteSystem. The ChannelBoard receives, decodes
and responds to channelcommands from a Central Processor Unit (CPU) inthe INTELLEC System. The Channel
Board can access INTELLEC System memory to determine the particular diskette operations tobe performed and
to fetch the parametersrequired forthe successful completion ofthe specifiedoperations. The ChannelBoard also
monitors DisketteSystemstatus and error conditions, and organizes theseindications into 'result type' and 'result
byte' words that canbe read bya CPUinthe INTELLEC System.
* «•' -i ,
The control functions ofthe Channel and InterfaceBoards are provided byan 8-bit microprogrammedprocessor,
implemented with Intel's Series 3000 Bipolar Computing Elements. The 8-bit controller includes four 3002 Central
Processing Elements(2-bit slice per CPE), a 3001Microprogram Control Unit and 512 x 32 bits of 3604 programmable-
read-only-memory (PROM) which stores the microprogram. The processing and control capabilities ofthe Diskette
System are achieved by execution ofthe microprogram. ,
r
The InterfaceBoardprovides the diskettecontroller with a means of communicating with the diskettedrives, as
well as with the INTELLEC Systembus. Under control ofthe microprogram executed from the Channel Board,
the InterfaceBoard generates those signals which cause the read/writehead onthe selecteddrive tobe loaded
(i.e., to come in contact with the diskette platter), then cause the head to move tothe propertrack. The Interface
Boardaccepts the databeing read offthe diskette,interpretscertainsynchronizing bit patterns,checks the validity
ofthe datausing a cyclic redundancy check(CRC) polynomial, and passes the data tothe ChannelBoard.
During write operations, the InterfaceBoard outputs the data and clockbits tothe selecteddrive atthe proper
times. It also generates CRC characters which are appended tothe data;thisallows the data tobe verifiedwhen
itis subsequently read. j i * S
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When the diskette controller requires access to INTELLEC System memory, the InterfaceBoardrequests and maintains
master control ofthe systembus, and generates the appropriatememorycommand.
When a CPUinthe INTELLEC System issues a channelcommand tothe DisketteSystem, the InterfaceBoard
acknowledges the command as required by INTELLECSystem bus protocol.
Each diskettedriveconsists of read/write and control electronics (ona single printed circuit board),drive
mechanism, read/writehead,trackpositioningmechanism andthe removable disketteplatter. These compo-
nents interact to perform the following functions:
• Interpret and generate control signals.
• Moveread/writehead to selected track.
* "r
• Read and write data.
Table 1-1 lists the performance characteristics for each diskettedrive.
TABLE 1-1
DISKETTEDRIVEPERFORMANCESPECIFICATIONS
Capacity (formatted)
Data TransferRate:
Access Time:
Average Access Time:
RotationalSpeed:
Average Latency:
Recording Mode:
Per Disk -
Per Track -
Track to Track -
SettlingTime —
512,512bytes
6,656 bytes
500 kilobits/second
10 ms
10ms
260ms
360RPM
83ms
(M^FM) Modified-Modified FrequencyModulation
The remainingchapters ofthe manualdeal with each ofthe system elements in detail.Chapter 2 describes the
range of operations that canbe performed bythe DisketteSystem, and also providesspecificinformation on
howto program the system to execute each ofthe possibleoperations.Chapters 3 and4 providedetailed
information onthe theory of operation forthe ChannelBoard andthe Interface Board, respectively. The final
section in each of these chaptersprovides a completeschematicdrawing ofthe board as well asa detailed pin
list. The readershouldcontinuallyrefer to theseschematicdrawings inthe course of reading the theory of
operationsections.
1-3

NOTE: To avoid any confusionwhenreferring tothe schematics forthe Channel and Interface Boards, or when
reading the corresponding circuit descriptions, the following notation, concerning the activelevel ofa
signal, will apply:
Whenever a signal is active-low, its mnemonic is followed bya slash; for example
MRDC/ means that the level on that line will below when the memory read
command is true(active). Ifthe signal is subsequentlyinverted,thusmaking it
active-high, the slash is omitted; for example, MRDC means that the level on that
linewill be highwhen the memorycommand is true.
Chapter 5 lists the manufacturer's information onthe diskette drives. Chapter 6 provides the majorstate flow
charts forthe microprogram which is executed bythe Series 3000 Bipolar Microcomputer Set(onthe Channel
Board), and which essentiallycontrolsoperation ofthe DisketteSystem.Chapter 7 providesbasic information
onthe installation anduseofthe DisketteSystem. Finally, Chapter 8 summarizes theACandDC operating
characteristics forthe DisketteSystem.
Beforeproceeding to Chapter 2, however, we firstprovide a comprehensivereview ofthe Intel soft-sectored
recording format which is used bythe DisketteOperatingSystem.
1.2 RECORDINGFORMAT
Thissectionsummarizes the specifications forthe soft-sectoredrecording format used bythe DisketteOperating
System. ->«•;-
!«-»
Physical Data Format:
The physicaldata format isthe format that the diskette controller circuitry mustinteract with. The elements
ofthe physicaldata format arethe hardindexhole,indexmark,sector address marks,sector headers, and data
sectors. The indexmark and sector address marks are recorded with unique clockpatternsrequiring the con-
troller circuitry to accumulate the unique clock patterns for index and sector address mark identification.
Figure 1-2 illustrates the generalphysicaldata format. J .< *•
;-.Y
A 'byte', whenreferring to serial data(being written toor read from the diskettedrive), is defined as eight (8)
consecutive bit cells. The most significant bit cell is defined asbit cell 0 andthe least significant bit cell is
defined asbit cell 7. Whenreference is made toa specificdata bit (i.e.,data bit3),itis with respect tothe
corresponding bit cell(bitcell 3).
During a write operation bit cell 0 of each byte is transferred tothe drive first with bit cell 7 being transferred
last. Correspondingly, the mostsignificant byte of data is transferred tothe diskettefirst andthe least signifi-
cant byte is transferredlast.
Whendata is beingreadback from the drive, bit cell 0 of each byte will be transferredfirst with bit cell 7
last. As with reading, the mostsignificant byte will be transferredfirst from the drive tothe user.
Figure 1-3 illustrates the relationship ofthe bits within a byte and Figure 1-4 illustrates the relationship ofthe
bytes for read and write data.
Data is recorded onthe disketteusing modified modified (M^) frequency modulation asthe recordingmode.Data
written onand readback from the disctakes the form shown in Figure 1-5. Clockbits are written only if there is
no data bitinthebit cell and there wasno data bitor clock bit written inthe previous bit cell. By definition, a
Bit Cell isthe period (2us) consisting ofa clock bit time (1us)anda data bit time (1 us).Figure 1-6 illustrates a
Bit Cell.
1-4

Track Format: > •*' • •*••-»**«** w3
Each trackrecorded ona disketteconsists of52 fixedlengthrecordsalong with necessary gaps for recordupdating.
Figure 1-7 illustrates the format ofone completetrack.
Each field ona track is separated fromadjacent fields bya number of bytescontaining no data. These areas
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are referred toas gaps andare provided to allow the updating ofone field without affectingadjacentfields.
As canbe seen from Figure1-7,there are four differenttypes of gaps on each track:
Gap1 — Post-Index Gap
This gapis defined asthe28 bytes betweenIndex Address Mark andtheID
Address Mark for Sector one (excluding the address markbytes).This gapis
always 28 bytes in length andisnot affected byany updating process.
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Gap 2-ID Gap
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t , The28 bytesbetween theID Field andthe DataField are defined asGap2
(ID Gap).This gap does not vary in size.
Gap 3- Data Gap
' - The28 bytesbetween the Data field andthe next ID field are defined asGap
3 (DataGap). The Data Gapmay vary slightly in lengthafter the adjacent
Data field has beenupdated, dueto differences in diskrotational speed between
formatting and updating of individual data fields.
V / Gap4 — Pre-lndex Gap
The338 bytesbetween the last Datafield ona track andthe Index Address
Mark are defined asGap4 (Pre-lndex Gap). Initially, this gapis nominally
338 bytes in length;however, dueto writefrequency tolerances and diskette
speed tolerancesthis gapmay varyslightly in length. Also, after the data
field of record 52has been updatedthis gapmay again change slightly in
length.
NS---^
Address Marks: \ ,
Address Marks are unique bit patterns one byte in lengthwhich are used to identify the beginning ofIDand
Data fields andto synchronize the deserializing circuitry with the firstbyte of each field. Address Markbytes
are unique from all otherdatabytes in that each Address Markcontains an extraclock bitinbit cell 2. There
are four differenttypes of Address Marks used. Each of these is used to identify differenttypes of fields:
%**
Index Address Mark 'r—"
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; The IndexAddressMark is located atthe beginning of eachtrack andisa fixed
number of bytes in front ofthe firstrecord. Thebit configuration forthe Index
Address Mark is shown in Figure1-8.
ID Address Mark
TheID Address Markbyte is located atthe beginning of each ID field onthe
diskette. Thebit configuration for this Address Mark is shown in Figure1-9.
1-5

Data Address Mark
The DataAddressMarkbyte is located atthe beginning of each non-deleted
Data Field onthe diskette. Thebit configuration for thisAddressMark is
shown in Figure1-10.
'•* - ~ V ,-'* " " •_ * r -_ <
DeletedData Address Mark .
CRC Bytes:
The DeletedData Address Markbyte is located atthe beginning of each
deleted Datafield onthe diskette. Thebit configuration for this Address Mark
is shown in Figure 1-11.
Each field written onthe diskette is appended with two CyclicRedundancyCheck(CRC)bytes. These two
CRC bytes are generated from a cyclic'permutation ofthe databitsstarting with bit zero ofthe address mark
and ending with bit seven ofthe last byte within a field(excluding theCRC bytes).Thiscyclicpermutation
is the remainder from the division ofthe databits inthe field(represented asan algebraic polynomial) bya
generator polynomialG(X). Forall fieldsrecorded ona diskette,thisgeneratorpolynomial is:
t~* I \y \ \/1R i V 1 *? i V R i -1 —
b(X) - XID + X1^ + X° + 1 75.x,-
When a field is read back from a diskette, the data bits (from bit zero ofthe address mark tobit seven ofthe
second CRC byte) are divided bythe same generatorpolynomialG(X) anda non-zeroremainderindicates an
error within the data read back from the drivewhile a remainder of zeroindicates the data has been read back
correctly from the diskette oran undetectableerror has been read back.
THE NUMBER OF BYTES MAY VARY DUETOENDOF TRACKTOLERANCES
/— WRITE TURN ON COINCIDENT WITH LEADING EDGE OF INDEXHOLE DURING INITIALIZATION
/
' Sector
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28
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ID
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28
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Data
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Binary
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CRC CRC
0123456
7 Bytes
(56 Bits)
Data
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128 BYTES OF DATA
CRCCRC
0 1-128 129130
131 BYTES
(1048BITS)
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Figure 1-2 PHYSICAL DATA FORMAT
1-6

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Figure 1-3 BYTEREPRESENTATION
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BYTE
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BYTE
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4
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10 11
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16
BYTE
17
BIT CELL OOF BYTE 0 IS
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WRITING AND FROM THE
DRIVE WHENREADING
BIT CELL 7 OF BYTE 17IS
LASTDATA TOBE SENT TO
THE DRIVEWHENWRITING
AND FROM THE DRIVE
WHEN READING
Figure 1-4 DATA BYTES
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Figure 1-6BIT CELL
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Figure 1-8 INDEX ADDRESSMARK
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BINARY REPRESENTATION OF
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HEXADECIMAL
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Figure 1-9ID ADDRESS MARK
1-10

D
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BIT
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BIT
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n i
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rv AH
n n n n
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BIT
CELLO
BINARY REPRESENTATION OF
DATABITS
CLOCKBITS
HEXADECIMAL
REPRESENTATION OF:
DATA BITS
CLOCKBITS
1011
Figure 1-10 DATA ADDRESS MARK
D
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n TL
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n
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BIT
CELL 7
BIT
CELLO
BIT
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BIT
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BIT
CELL 3
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CELL4
BIT
CELL 5
DELETED DATA ADDRESS MARKBYTE-
BIT
CELL6
BIT
CELL?
BIT
CELLO
BINARY REPRESENTATION OF
DATABITS
CLOCKBITS
HEXADECIMAL
REPRESENTATION OF:
DATABITS
CLOCK BITS
1000
Figure 1-11 DELETED DATA ADDRESS MARK
1-11

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