Intel 82541PI Guide

82541PI(ER) and 82562GZ(GX) Dual
Footprint LOM Design Guide
Application Note (AP-468)
Revision 2.1
April 2005

ii Application Note (AP-468)
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Application Note (AP-468) iii
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Revision History
Revision Revision Date Description
0.6 Jun 2004 • Initial release
0.7 Jul 2004 • Distinguished 82562G Family from other products in line.
1.0 Aug 2004 • Added references to MDI/MDI-X feature.
1.1 Oct 2004 • Initial release White Cover Confidential (WCC).
• Corrected LED configuration modes.
• Replaced MagJack* references with magnetics modules.
1.2 Nov 2004 • Updated reference schematics.
• Added Appendix A “Measuring LAN Reference Frequency Using a Fre-
quency Counter.
1.3 Dec 2004 • Removed confidential status.
• Added reference schematics.
2.0 Feb 2005 • Added 82541PI(ER) board design and layout information to match reference
schematics.
• Removed 82562G(GT) Shrink Small Outline Package (SSOP) information.
This information now resides in the 82562ET/GT/G LAN on Motherboard
Design Guide.
2.1 Apr 2005 • Added internal/external pull-up/pull-down resistor values for hardware con-
figuration signals TESTEN, ISOL_EXEC, ISOL_TI, ISOL_TCK, and ADV10/
LAN_DISABLE#.
• Added a note on sheet 2 of reference schematics stating CLK_RUN# is not
applicable to the 82541ER.

iv Application Note (AP-468)
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
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Application Note (AP-468) v
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Contents
1.0 Introduction.............................................................................................. 1
1.1 Scope.......................................................................................................................1
1.2 Terms.......................................................................................................................1
1.3 Reference Documents .............................................................................................2
1.4 Product Codes .........................................................................................................2
1.5 82541PI(ER) Gigabit Ethernet Controllers...............................................................2
1.6 82562GZ(GX) Platform LAN Connect (PLC) Devices..............................................3
1.6.1 Usage Modes................................................................................................3
2.0 Frequency Control Device Design Considerations .............................. 5
2.1 Frequency Control Component Types.....................................................................5
2.2 Quartz Crystal ..........................................................................................................5
2.3 Fixed Crystal Oscillator............................................................................................6
2.4 Programmable Crystal Oscillators............................................................................6
2.5 Ceramic Resonator..................................................................................................6
3.0 Ethernet Component Design Guidelines............................................... 7
3.1 General Design Considerations for Ethernet Controllers.........................................7
3.1.1 Crystal Selection Parameters........................................................................7
3.1.2 Reference Crystal........................................................................................11
3.1.3 Reference Crystal Selection........................................................................11
3.1.4 Circuit Board................................................................................................11
3.1.5 Temperature Changes ................................................................................12
3.2 Analog References for 82562GZ(GX) Designs......................................................12
3.3 Integrated Magnetics Module.................................................................................13
3.4 Designing with the 82562GZ(GX) Platform LAN Connect Device .........................13
3.4.1 Power Supplies for 82562GZ(GX) PLC Implementations ...........................13
3.4.2 82562GZ(GX) Device Test Capability.........................................................13
3.4.3 82562GZ/GX PLC Device LAN Disable Guidelines ....................................13
3.4.4 Serial EEPROM for 82562GZ(GX) Implementations ..................................14
3.4.5 Magnetics Modules for 82562GZ(GX) PLC Devices...................................15

vi Application Note (AP-468)
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
3.5 Flash Interface .......................................................................................................15
3.6 Designing with 82541PI(ER) Gigabit Controllers...................................................15
3.6.1 82541PI(ER) Gigabit Controller LAN Disable Guidelines............................15
3.6.2 Power Supplies for 82541PI(ER) Gigabit Ethernet Controllers...................16
3.6.3 82541PI(ER) Controller Power Supply Filtering..........................................17
3.6.4 82541PI(ER) Controller Power Management and Wake Up.......................17
3.6.5 82541PI(ER) Controller Test Capability......................................................18
3.6.6 Serial EEPROM for 82541PI(ER) Controller Implementations....................18
3.6.7 EEPROM Map Information..........................................................................19
3.6.8 Magnetics Modules for 82541PI(ER) Controller Applications .....................19
3.6.9 Oscillators for 82541PI Controllers..............................................................21
3.6.10 82541PI(ER) Oscillator Solution..................................................................22
4.0 General Layout Considerations for Ethernet Controllers ..................25
4.1 Guidelines for Component Placement ...................................................................25
4.1.1 Crystals .......................................................................................................26
4.1.2 Board Stackup Recommendations..............................................................26
4.2 Critical Dimensions for Discrete Magnetics Module and RJ-45.............................27
4.2.1 Distance A: Magnetics to RJ45 (Priority 1)..................................................27
4.2.2 Distance B: PHY to Magnetics (Priority 2)...................................................28
4.2.3 Distance C: LAN Controller to Chipset (Priority 3) ......................................28
4.2.4 Distance D: The Overall
Length of Differential Traces from LAN to RJ-45 (Priority 4).......................28
4.2.5 Distance E: Ethernet Controller to PCB Edge.............................................28
4.3 Critical Dimensions for an Integrated Magnetics Module.......................................29
4.3.1 Distance A: The Overall Length of Differential Traces................................29
4.3.2 Distance B: Ethernet Controller to Chipset..................................................29
4.3.3 Distance C: LAN Controller to PCB Edge ...................................................29
4.4 Differential Pair Trace Routing...............................................................................29
4.4.1 Signal Trace Geometry ...............................................................................31
4.4.2 Impedance Discontinuities ..........................................................................32
4.4.3 Reducing Circuit Inductance .......................................................................32
4.4.4 Signal Isolation............................................................................................32
4.4.5 Power and Ground Planes..........................................................................33
4.4.6 Traces for Decoupling Capacitors...............................................................33
4.4.7 Ground Planes Under a Discrete Magnetics Module..................................34
4.4.8 Non-Integrated Magnetics Modules/RJ-45 Connectors ..............................36
4.4.9 82562GZ(GX) Layout
Guidelines (Routing LAN 3.3 V When Using a Copper Trace)....................37
4.5 82562GZ(GX) Signal Terminations........................................................................38
4.5.1 Termination Plane.......................................................................................39
4.5.2 Termination Plane Capacitance..................................................................39
4.6 Light Emitting Diodes for Designs Based on 82562GZ(GX) PLC..........................39
4.7 82541PI(ER) Signal Terminations..........................................................................40

Application Note (AP-468) vii
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
4.8 Light Emitting Diodes for Designs Based on 82541PI(ER)....................................40
4.9 Schematic for EEPROM Footprints and LCI Connection.......................................40
4.10 Termination of Unused
Differential Signals on Gigabit Magnetics for 10/100 LOM Design ........................41
4.10.1 Option 1: Board Level Stuffing ....................................................................41
4.10.2 Option 2: Rework of Gigabit Magnetics.......................................................43
4.10.3 Option 3: Integrated Magnetics Module for 10/100 Mbps and Gigabit........44
4.11 Physical Layer Conformance Testing ....................................................................45
4.12 Troubleshooting Common Physical Layout Issues................................................46
5.0 Pin Number to Signal Mapping with Population Options .................. 47
6.0 Self-Review Checklist for Combined Footprint LOM.......................... 55
7.0 Reference Schematics........................................................................... 57
A Measuring LAN Reference
Frequency Using a Frequency Counter............................................... 69
Figures
1 Crystal Circuit................................................................................................9
2 RBIAS10 and RBIAS100 Circuits................................................................12
3 82541PI(ER) LAN Disable Circuitry ............................................................16
4 General Placement Distances.....................................................................26
5 Critical Dimensions for
Component Placement (Discrete Magnetics Solution)................................27
6 Critical Dimensions for 82562GZ(GX) and
82541PI(ER) Component Placement with Integrated Magnetics Module ...29
7 Corner Trace Routing..................................................................................30
8 Ground Plane Separation............................................................................34
9 Ideal Ground Split Implementation (for Integrated RJ-45 without USB)......35
10 Termination Plane Example for
82562GZ/GX PLC Device and Discrete Magnetics.....................................36
11 Decoupled LAN Power Trace (Power Supplied by Trace) ..........................37
12 Using a Moat to Reduce Noise From Adjacent Traces and Power Fills......38
13 Termination Resistors Placement (Integrated Magnetics Solution) ............39
14 Common EEPROM Footprint for Both 82541PI(ER) and 82562GZ(GX)....40
15 Independent EEPROM Footprints for Individual LAN Controllers...............41
16 Typical Magnetics for Gigabit LAN
Controller with Optional Resistors Footprint................................................42
17 Replacement of Magnetics for
10/100 LAN Controller with Optional Resistors Populated..........................43
18 Rework of Gigabit Magnetics with Shorted
Pair Three and Four on Differential Traces for 10/100 LOM Design...........44
19 Indirect Probing Setup.................................................................................70
20 Direct Probing Method.................................................................................73

viii Application Note (AP-468)
82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Tables
1 Product Ordering Codes................................................................................2
2 Drop-in Replacement Mode ..........................................................................3
3 New Usage Modes........................................................................................4
4 Recommended Crystals................................................................................5
5 Crystal Parameters........................................................................................7
6 82562GZ(GX) Memory Layout (128B EEPROM)........................................14
7 82562GZ(GX) Memory Layout (512B EEPROM)........................................14
8 Recommended EEPROM Manufacturers ...................................................14
9 Recommended Magnetics Modules............................................................15
10 Microwire 64 x 16 Serial EEPROMs............................................................18
11 SPI* Serial EEPROMs for 82541PI(ER) Controller.....................................19
12 82541PI(ER) EEPROM Memory Layout .....................................................19
13 82541PI(ER) Recommended Magnetics Modules......................................19
14 Electrical Specifications at 25°C for 10/100 Magnetics...............................20
15 Electrical Specifications at 25° C for 1000 Gb Silicon.................................21
16 82541PI Clock Oscillator Specifications......................................................22
17 82541PI(ER) Recommended Oscillators ....................................................23
18 Ball Number to Signal Mapping...................................................................47

82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
Application Note (AP-468) 1
1.0 Introduction
82541PI(ER) Gigabit Ethernet controllers and 82562GZ(GX) Platform LAN Connect (PLC)
devices are all manufactured in a footprint-compatible 15 mm x 15 mm, 196-ball grid array
package. Many of the critical signal pin locations on the 82541PI(ER) are identical to signals on
the 82562GZ(GX) allowing designers to create a single design that accommodates these two parts.
Because the usage of some pins on the 82541PI(ER) differ from the usage on the 82562GZ(GX),
the two parts are not referred to as “pin compatible”. The term “footprint compatible” refers to the
fact that the parts share the same package size, same number and pattern of pins, and layout of
signals that allow for the flexible, cost effective, multipurpose design. Therefore, it is easy to
populate a single board design with any of the two parts to maximize value while matching your
customers' performance needs.
1.1 Scope
This application note identifies the design differences between the 82541PI(ER) and the
82562GZ(GX). The table in Section 5.0 lists the pinout assignments for each of the two parts.
For other necessary design collateral, please refer to “Reference Documents” (Section 1.3).
1.2 Terms
AFE Analog Front End.
BER Bit Error Rate.
DFD Dual Footprint Design — a design that uses an 82562GZ/GX device
with an Intel®82541PI(ER) Gigabit Ethernet controller.
DUT Device Under Test.
ICHx I/O ControllerHub (ICH)that supportsthe 82562GZ(GX) PLC interface
(x = 5, 6, or 7).
LCI LAN Connect Interface.
BGA Ball Grid Array.
PLC Platform LAN Connect.
USB Universal Serial Bus

82541PI(ER) and 82562GZ(GX) Dual Footprint LOM Design Guide
2Application Note (AP-468)
1.3 Reference Documents
This application note assumes that you have a working knowledge of high-speed design and layout
issues and the Advanced Configuration and Power Interface (ACPI) Specification. An
understanding of power management industry initiatives is valuable prior to beginning the
integration of an 82541PI(ER) controller or 82562GZ(GX) device into any platform. The
following reference list provides sufficient background material.
•82541ER Gigabit Ethernet Controller Datasheet. Intel Corporation.
•82541 Family of Gigabit Ethernet Controllers Datasheet. Intel Corporation.
•82562GZ 10/100 Mbps Platform LAN Connect (PLC) Datasheet. Intel Corporation.
•82562GX 10/100 Mbps Platform LAN Connect (PLC) Datasheet. Intel Corporation.
•I/O Control Hub 5, 6 and 7 EEPROM Map and Programming Information. Intel Corporation.
•Intel Packaging Databook, 1999. Intel Corporation (http://developer.intel.com/design/
packtech/)
Please contact your Intel representative for information related to EEPROM programming maps
and ASF 1.0 implementation.
1.4 Product Codes
Table 1 lists the product ordering codes for the 82541PI(ER) and the 82562GZ(GX).
1.5 82541PI(ER) Gigabit Ethernet Controllers
Intel®82541PI(ER) Gigabit Ethernet controllers are single, compact components with an
integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For
embedded communication and network devices such as web kiosks, and point-of-sale terminal
designs with critical space constraints, the 82541PI(ER) allows for a Gigabit Ethernet
implementation in a very small area that is footprint compatible with current generation 10/100
Mbps Fast Ethernet designs.
The Intel®82541PI(ER) integrates a gigabit MAC design with fully integrated, physical layer
circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE_TX, and
10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and
receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and
PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component
Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66 MHz.
Table 1. Product Ordering Codes
Device Product Code Product Code (Lead Free)
82562GZ GD82562GZ LU82562GZ
82562GX GD82562GX LU82562GX
82541PI GD82541PI LU82541PI
82541ER GD82541ER LU82541ER