Intel IXP45X User manual

Order Number: 306262-004US
Intel®IXP45X and Intel®IXP46X
Product Line of Network Processors
Developer’s Manual
August 2006

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
2Order Number: 306262-004US
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Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 3
Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Contents
1.0 Introduction.............................................................................................................38
1.1 About This Document.........................................................................................38
1.2 Intended Audience ............................................................................................38
1.3 How to Read This Document...............................................................................38
1.4 Other Relevant Documents.................................................................................38
1.5 Terminology and Conventions .............................................................................39
1.5.1 Number Representation...........................................................................42
1.5.2 Signal-Naming Convention ......................................................................42
1.5.3 Register Legend.....................................................................................43
2.0 Functional Overview ................................................................................................ 44
2.1 Key Functional Units..........................................................................................48
2.1.1 Network Processor Engines (NPEs)............................................................48
2.1.2 Internal Bus ..........................................................................................49
2.1.2.1 North AHB ...............................................................................49
2.1.2.2 South AHB...............................................................................50
2.1.2.3 Memory Port Interface...............................................................50
2.1.2.4 APB Bus ..................................................................................51
2.1.3 MII/SMII Interfaces................................................................................51
2.1.4 UTOPIA Level 2......................................................................................51
2.1.5 Universal Serial Bus (USB) Interfaces........................................................52
2.1.5.1 USB 1.1 Device Interface...........................................................52
2.1.5.2 USB 2.0 Host Interface..............................................................52
2.1.6 PCI Controller........................................................................................52
2.1.7 DDRI SDRAM Controller ..........................................................................53
2.1.8 Expansion Interface................................................................................54
2.1.9 High-Speed, Serial Interfaces...................................................................56
2.1.10 UARTs ..................................................................................................56
2.1.11 GPIO ....................................................................................................56
2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) .....................................57
2.1.13 Interrupt Controller ................................................................................57
2.1.14 Timers..................................................................................................58
2.1.15 IEEE-1588 Hardware Assist .....................................................................58
2.1.16 Synchronous Serial Protocol Interface .......................................................58
2.1.17 I2C Interface.........................................................................................59
2.1.18 AES/DES/SHA/MD-5 ............................................................................... 59
2.1.19 Cryptography Unit..................................................................................59
2.1.20 Queue Manager......................................................................................60
2.2 Intel XScale®Processor .....................................................................................60
2.2.1 Super Pipeline........................................................................................62
2.2.2 Branch Target Buffer ..............................................................................63
2.2.3 Instruction Memory Management Unit.......................................................63
2.2.4 Data Memory Management Unit ...............................................................64
2.2.5 Instruction Cache...................................................................................64
2.2.6 Data Cache ...........................................................................................65
2.2.7 Mini-Data Cache.....................................................................................65
2.2.8 Fill Buffer and Pend Buffer.......................................................................65
2.2.9 Write Buffer...........................................................................................66
2.2.10 Multiply-Accumulate Coprocessor .............................................................66
2.2.11 Performance Monitoring Unit....................................................................66
2.2.12 Debug Unit............................................................................................67
3.0 Intel XScale®Processor...........................................................................................69

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
4Order Number: 306262-004US
3.1 Memory Management Unit ..................................................................................69
3.1.1 Memory Attributes ..................................................................................70
3.1.1.1 Page (P) Attribute Bit.................................................................70
3.1.1.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits ....................70
3.1.2 Interaction of the MMU, Instruction Cache, and Data Cache..........................72
3.1.3 MMU Control ..........................................................................................73
3.1.3.1 Invalidate (Flush) Operation .......................................................73
3.1.3.2 Enabling/Disabling.....................................................................73
3.1.3.3 Locking Entries .........................................................................74
3.1.3.4 Round-Robin Replacement Algorithm ...........................................76
3.2 Instruction Cache ..............................................................................................77
3.2.1 Operation When Instruction Cache is Enabled.............................................77
3.2.1.1 Instruction-Cache ‘Miss’ .............................................................78
3.2.1.2 Instruction-Cache Line-Replacement Algorithm..............................79
3.2.1.3 Instruction-Cache Coherence ......................................................80
3.3 Branch Target Buffer..........................................................................................83
3.3.1 Branch Target Buffer (BTB) Operation .......................................................83
3.3.1.1 Reset.......................................................................................85
3.4 Data Cache.......................................................................................................85
3.4.1 Data Cache Overview ..............................................................................85
3.4.2 Cacheability...........................................................................................88
3.4.3 Reconfiguring the Data Cache as Data RAM................................................92
3.5 Configuration ....................................................................................................96
3.5.1 CP15 Registers.......................................................................................98
3.5.1.1 Register 0: ID & Cache Type Registers.........................................98
3.5.1.2 Register 1: Control and Auxiliary Control Registers ......................100
3.5.1.3 Register 2: Translation Table Base Register ................................102
3.5.1.4 Register 3: Domain Access Control Register................................102
3.5.1.5 Register 4: Reserved ...............................................................102
3.5.1.6 Register 5: Fault Status Register ...............................................102
3.5.1.7 Register 6: Fault Address Register.............................................103
3.5.1.8 Register 7: Cache Functions......................................................103
3.5.1.9 Register 8: TLB Operations.......................................................104
3.5.1.10 Register 9: Cache Lock Down....................................................105
3.5.1.11 Register 10: TLB Lock Down .....................................................106
3.5.1.12 Register 11-12: Reserved.........................................................106
3.5.1.13 Register 13: Process ID............................................................106
3.5.1.14 The PID Register Affect On Addresses ........................................107
3.5.1.15 Register 14: Breakpoint Registers..............................................107
3.5.1.16 Register 15: Coprocessor Access Register...................................107
3.5.2 CP14 Registers.....................................................................................108
3.5.2.1 Performance Monitoring Registers..............................................109
3.5.2.2 Clock and Power Management Registers.....................................109
3.5.2.3 Software Debug Registers ........................................................110
3.6 Software Debug...............................................................................................111
3.6.1 Definitions ...........................................................................................111
3.6.2 Debug Registers ...................................................................................111
3.6.3 Debug Modes .......................................................................................112
3.6.3.1 Halt Mode ..............................................................................112
3.6.3.2 Monitor Mode..........................................................................112
3.6.4 Debug Control and Status Register (DCSR) ..............................................112
3.6.4.1 Global Enable Bit (GE) .............................................................114
3.6.4.2 Halt Mode Bit (H) ....................................................................114
3.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR) ....................................114
3.6.4.4 Sticky Abort Bit (SA)................................................................114
3.6.4.5 Method of Entry Bits (MOE) ......................................................114
3.6.4.6 Trace Buffer Mode Bit (M).........................................................114

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 5
Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
3.6.4.7 Trace Buffer Enable Bit (E)....................................................... 114
3.6.5 Debug Exceptions................................................................................. 115
3.6.5.1 Halt Mode.............................................................................. 115
3.6.5.2 Monitor Mode ......................................................................... 117
3.6.6 HW Breakpoint Resources...................................................................... 117
3.6.6.1 Instruction Breakpoints............................................................ 118
3.6.6.2 Data Breakpoints.................................................................... 118
3.6.7 Software Breakpoints............................................................................ 120
3.6.8 Transmit/Receive Control Register.......................................................... 120
3.6.8.1 RX Register Ready Bit (RR) ...................................................... 121
3.6.8.2 Overflow Flag (OV) ................................................................. 122
3.6.8.3 Download Flag (D) .................................................................. 122
3.6.8.4 TX Register Ready Bit (TR)....................................................... 123
3.6.8.5 Conditional Execution Using TXRXCTRL...................................... 123
3.6.9 Transmit Register................................................................................. 124
3.6.10 Receive Register .................................................................................. 124
3.6.11 Debug JTAG Access .............................................................................. 124
3.6.11.1 SELDCSR JTAG Command........................................................ 125
3.6.11.2 SELDCSR JTAG Register........................................................... 125
3.6.11.3 DBGTX JTAG Command ........................................................... 127
3.6.11.4 DBGTX JTAG Register.............................................................. 127
3.6.11.5 DBGRX JTAG Command........................................................... 128
3.6.11.6 DBGRX JTAG Register.............................................................. 128
3.6.11.7 Debug JTAG Data Register Reset Values..................................... 132
3.6.12 Trace Buffer ........................................................................................ 132
3.6.12.1 Trace Buffer CP Registers......................................................... 132
3.6.13 Trace Buffer Entries.............................................................................. 134
3.6.13.1 Message Byte......................................................................... 134
3.6.13.2 Trace Buffer Usage.................................................................. 137
3.6.14 Downloading Code in ICache.................................................................. 139
3.6.14.1 LDIC JTAG Command .............................................................. 139
3.6.14.2 LDIC JTAG Data Register ......................................................... 140
3.6.14.3 LDIC Cache Functions.............................................................. 141
3.6.14.4 Loading IC During Reset .......................................................... 142
3.6.14.5 Dynamically Loading IC After Reset........................................... 147
3.6.14.6 Mini-Instruction Cache Overview............................................... 150
3.6.15 Halt Mode Software Protocol .................................................................. 150
3.6.15.1 Starting a Debug Session......................................................... 150
3.6.15.2 Implementing a Debug Handler ................................................ 152
3.6.15.3 Ending a Debug Session .......................................................... 155
3.6.16 Software Debug Notes and Errata........................................................... 156
3.7 Performance Monitoring ................................................................................... 157
3.7.1 Overview ............................................................................................ 157
3.7.2 Register Description.............................................................................. 158
3.7.2.1 Clock Counter (CCNT) ............................................................. 158
3.7.2.2 Performance Count Registers.................................................... 158
3.7.2.3 Performance Monitor Control Register........................................ 159
3.7.2.4 Interrupt Enable Register......................................................... 159
3.7.2.5 Overflow Flag Status Register................................................... 160
3.7.2.6 Event Select Register .............................................................. 161
3.7.3 Managing the Performance Monitor......................................................... 162
3.7.4 Performance Monitoring Events .............................................................. 162
3.7.4.1 Instruction Cache Efficiency Mode ............................................. 163
3.7.4.2 Data Cache Efficiency Mode...................................................... 163
3.7.4.3 Instruction Fetch Latency Mode ................................................ 164
3.7.4.4 Data/Bus Request Buffer Full Mode............................................ 164
3.7.4.5 Stall/Write-Back Statistics........................................................ 165

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
6Order Number: 306262-004US
3.7.4.6 Instruction TLB Efficiency Mode.................................................165
3.7.4.7 Data TLB Efficiency Mode .........................................................165
3.7.5 Multiple Performance Monitoring Run Statistics .........................................166
3.7.6 Examples.............................................................................................166
3.8 Programming Model .........................................................................................167
3.8.1 Intel®StrongARM*Architecture Compatibility...........................................167
3.8.2 Intel®StrongARM*Architecture Implementation Options ...........................168
3.8.2.1 Big-Endian versus Little-Endian.................................................168
3.8.2.2 26-Bit Architecture ..................................................................168
3.8.2.3 Thumb...................................................................................168
3.8.2.4 Intel®StrongARM*DSP-Enhanced Instruction Set .......................168
3.8.2.5 Base Register Update...............................................................169
3.8.3 Extensions to Intel®StrongARM*Architecture ..........................................169
3.8.3.1 DSP Coprocessor 0 (CP0) .........................................................169
3.8.3.2 New Page Attributes ................................................................175
3.8.3.3 Additions to CP15 Functionality .................................................176
3.8.3.4 Event Architecture...................................................................177
3.9 Performance Considerations..............................................................................181
3.9.1 Interrupt Latency..................................................................................181
3.9.2 Branch Prediction..................................................................................182
3.9.3 Addressing Modes.................................................................................182
3.9.4 Instruction Latencies.............................................................................182
3.9.4.1 Performance Terms .................................................................182
3.9.4.2 Branch Instruction Timings.......................................................184
3.9.4.3 Data Processing Instruction Timings...........................................184
3.9.4.4 Multiply Instruction Timings......................................................185
3.9.4.5 Saturated Arithmetic Instructions ..............................................187
3.9.4.6 Status Register Access Instructions............................................187
3.9.4.7 Load/Store Instructions............................................................187
3.9.4.8 Semaphore Instructions ...........................................................188
3.9.4.9 Coprocessor Instructions..........................................................188
3.9.4.10 Miscellaneous Instruction Timing ...............................................189
3.9.4.11 Thumb Instructions .................................................................189
3.10 Optimization Guide ..........................................................................................189
3.10.1 Introduction.........................................................................................189
3.10.1.1 About This Section ..................................................................190
3.10.2 Processor Pipeline.................................................................................190
3.10.2.1 General Pipeline Characteristics.................................................190
3.10.2.2 Instruction Flow Through the Pipeline.........................................192
3.10.2.3 Main Execution Pipeline............................................................193
3.10.2.4 Memory Pipeline......................................................................194
3.10.2.5 Multiply/Multiply Accumulate (MAC) Pipeline ...............................195
3.10.3 Basic Optimizations...............................................................................195
3.10.3.1 Conditional Instructions ...........................................................195
3.10.3.2 Bit Field Manipulation...............................................................199
3.10.3.3 Optimizing the Use of Immediate Values ....................................200
3.10.3.4 Optimizing Integer Multiply and Divide .......................................200
3.10.3.5 Effective Use of Addressing Modes.............................................201
3.10.4 Cache and Prefetch Optimizations ...........................................................201
3.10.4.1 Instruction Cache....................................................................201
3.10.4.2 Data and Mini Cache................................................................203
3.10.4.3 Cache Considerations...............................................................206
3.10.4.4 Prefetch Considerations............................................................207
3.10.5 Instruction Scheduling...........................................................................212
3.10.5.1 Scheduling Loads ....................................................................212
3.10.5.2 Scheduling Data Processing Instructions.....................................216
3.10.5.3 Scheduling Multiply Instructions ................................................217
3.10.5.4 Scheduling SWP and SWPB Instructions .....................................218

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
3.10.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)............. 218
3.10.5.6 Scheduling the MIA and MIAPH Instructions................................ 219
3.10.5.7 Scheduling MRS and MSR Instructions ....................................... 219
3.10.5.8 Scheduling CP15 Coprocessor Instructions ................................. 220
3.10.6 Optimizing C Libraries........................................................................... 220
3.10.7 Optimizations for Size........................................................................... 220
3.10.7.1 Space/Performance Trade Off................................................... 220
4.0 Network Processor Engines (NPE) .........................................................................222
5.0 Internal Buses ....................................................................................................... 224
5.1 Internal Bus Arbiters........................................................................................ 225
5.1.1 Priority Mechanism ............................................................................... 225
5.2 Memory Map................................................................................................... 226
6.0 Ethernet MACs .......................................................................................................229
6.1 Ethernet Coprocessor....................................................................................... 230
6.1.1 Ethernet Coprocessor APB Interface........................................................ 230
6.1.2 Ethernet Coprocessor NPE Interface........................................................ 230
6.1.3 Ethernet Coprocessor MDIO Interface ..................................................... 231
6.1.4 Transmitting Ethernet Frames with MII Interfaces..................................... 233
6.1.5 Receiving Ethernet Frames with MII Interfaces......................................... 236
6.1.6 General Ethernet Coprocessor Configuration ............................................ 238
6.2 Register Descriptions Ethernet MACs.................................................................. 239
6.2.1 Ethernet MAC 0 on NPE B...................................................................... 240
6.2.2 Ethernet MAC 1 on NPE B...................................................................... 241
6.2.3 Ethernet MAC 2 on NPE B...................................................................... 243
6.2.4 Ethernet MAC 2 on NPE B...................................................................... 244
6.2.5 Ethernet MAC on NPE A......................................................................... 246
6.2.6 Ethernet MAC on NPE C......................................................................... 247
6.2.7 Transmit Control 1 ............................................................................... 249
6.2.8 Transmit Control 2 ............................................................................... 249
6.2.9 Receive Control 1................................................................................. 250
6.2.10 Receive Control 2................................................................................. 251
6.2.11 Random Seed ...................................................................................... 251
6.2.12 Threshold For Partially Empty................................................................. 251
6.2.13 Threshold For Partially Full..................................................................... 252
6.2.14 Buffer Size For Transmit........................................................................ 252
6.2.15 Transmit Deferral Parameter.................................................................. 253
6.2.16 Receive Deferral Parameter ................................................................... 253
6.2.17 Transmit Two Part Deferral Parameters 1 ................................................ 253
6.2.18 Transmit Two Part Deferral Parameters 2 ................................................ 254
6.2.19 Slot Time ............................................................................................ 254
6.2.20 MDIO Commands Registers ................................................................... 254
6.2.21 MDIO Command 1................................................................................ 255
6.2.22 MDIO Command 2................................................................................ 255
6.2.23 MDIO Command 3................................................................................ 255
6.2.24 MDIO Command 4................................................................................ 256
6.2.25 MDIO Status Registers.......................................................................... 256
6.2.26 MDIO Status 1..................................................................................... 256
6.2.27 MDIO Status 2..................................................................................... 257
6.2.28 MDIO Status 3..................................................................................... 257
6.2.29 MDIO Status 4..................................................................................... 257
6.2.30 Address Mask Registers......................................................................... 257
6.2.31 Address Mask 1.................................................................................... 258
6.2.32 Address Mask 2.................................................................................... 258

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
8Order Number: 306262-004US
6.2.33 Address Mask 3 ....................................................................................259
6.2.34 Address Mask 4 ....................................................................................259
6.2.35 Address Mask 5 ....................................................................................259
6.2.36 Address Mask 6 ....................................................................................260
6.2.37 Address Registers.................................................................................260
6.2.38 Address 1............................................................................................261
6.2.39 Address 2............................................................................................261
6.2.40 Address 3............................................................................................261
6.2.41 Address 4............................................................................................262
6.2.42 Address 5............................................................................................262
6.2.43 Address 6............................................................................................262
6.2.44 Threshold for Internal Clock ...................................................................263
6.2.45 Unicast Address Registers......................................................................263
6.2.46 Unicast Address 1.................................................................................264
6.2.47 Unicast Address 2.................................................................................264
6.2.48 Unicast Address 3.................................................................................264
6.2.49 Unicast Address 4.................................................................................264
6.2.50 Unicast Address 5.................................................................................265
6.2.51 Unicast Address 6.................................................................................265
6.2.52 Core Control ........................................................................................265
7.0 UTOPIA Level 2 ......................................................................................................268
7.1 Introduction....................................................................................................268
7.2 UTOPIA Transmit Module ..................................................................................269
7.3 UTOPIA Receive Module....................................................................................272
7.4 UTOPIA Level 2 Coprocessor / NPE Coprocessor: Bus Interface ..............................275
7.5 MPHY Polling Routines ......................................................................................275
7.6 UTOPIA Level 2 Clocks......................................................................................276
8.0 USB 1.1 Device Controller.......................................................................................278
8.1 USB Overview .................................................................................................278
8.2 Device Configuration........................................................................................279
8.3 USB Operation ................................................................................................280
8.3.1 Signalling Levels...................................................................................280
8.3.2 Bit Encoding.........................................................................................281
8.3.3 Field Formats .......................................................................................282
8.3.4 Packet Formats ....................................................................................283
8.3.4.1 Token Packet Type ..................................................................284
8.3.4.2 Start-of-Frame Packet Type......................................................284
8.3.4.3 Data Packet Type ....................................................................284
8.3.4.4 Handshake Packet Type ...........................................................285
8.3.5 Transaction Formats..............................................................................285
8.3.5.1 Bulk Transaction Type..............................................................285
8.3.5.2 Isochronous Transaction Type...................................................286
8.3.5.3 Control Transaction Type..........................................................286
8.3.5.4 Interrupt Transaction Type .......................................................287
8.3.6 UDC Device Requests............................................................................287
8.3.7 UDC Configuration ................................................................................288
8.4 UDC Hardware Connections...............................................................................289
8.4.1 Self-Powered Device .............................................................................289
8.4.2 Bus-Powered Devices ............................................................................289
8.5 Register Descriptions........................................................................................289
8.5.1 UDC Control Register ............................................................................291
8.5.1.1 UDC Enable............................................................................291
8.5.1.2 UDC Active.............................................................................292
8.5.1.3 UDC Resume (RSM).................................................................292

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
8.5.1.4 Resume Interrupt Request (RESIR) ........................................... 292
8.5.1.5 Suspend Interrupt Request (SUSIR) .......................................... 292
8.5.1.6 Suspend/Resume Interrupt Mask (SRM)..................................... 292
8.5.1.7 Reset Interrupt Request (RSTIR)............................................... 292
8.5.1.8 Reset Interrupt Mask (REM) ..................................................... 292
8.5.2 UDC Endpoint 0 Control/Status Register .................................................. 293
8.5.2.1 OUT Packet Ready (OPR) ......................................................... 294
8.5.2.2 IN Packet Ready (IPR)............................................................. 294
8.5.2.3 Flush Tx FIFO (FTF)................................................................. 294
8.5.2.4 Device Remote Wake-Up Feature (DRWF) .................................. 294
8.5.2.5 Sent Stall (SST)...................................................................... 294
8.5.2.6 Force Stall (FST)..................................................................... 295
8.5.2.7 Receive FIFO Not Empty (RNE)................................................. 295
8.5.2.8 Setup Active (SA) ................................................................... 295
8.5.3 UDC Endpoint 1 Control/Status Register .................................................. 296
8.5.3.1 Transmit FIFO Service (TFS)..................................................... 296
8.5.3.2 Transmit Packet Complete (TPC)............................................... 296
8.5.3.3 Flush Tx FIFO (FTF)................................................................. 296
8.5.3.4 Transmit Underrun (TUR)......................................................... 296
8.5.3.5 Sent STALL (SST) ................................................................... 297
8.5.3.6 Force STALL (FST) .................................................................. 297
8.5.3.7 Bit 6 Reserved........................................................................ 297
8.5.3.8 Transmit Short Packet (TSP) .................................................... 297
8.5.4 UDC Endpoint 2 Control/Status Register .................................................. 298
8.5.4.1 Receive FIFO Service (RFS)...................................................... 298
8.5.4.2 Receive Packet Complete (RPC) ................................................ 298
8.5.4.3 Bit 2 Reserved........................................................................ 298
8.5.4.4 Bit 2 Reserved........................................................................ 298
8.5.4.5 Sent Stall (SST)...................................................................... 299
8.5.4.6 Force Stall (FST)..................................................................... 299
8.5.4.7 Receive FIFO Not Empty (RNE)................................................. 299
8.5.4.8 Receive Short Packet (RSP)...................................................... 299
8.5.5 UDC Endpoint 3 Control/Status Register .................................................. 300
8.5.5.1 Transmit FIFO Service (TFS)..................................................... 300
8.5.5.2 Transmit Packet Complete (TPC)............................................... 301
8.5.5.3 Flush Tx FIFO (FTF)................................................................. 301
8.5.5.4 Transmit Underrun (TUR)......................................................... 301
8.5.5.5 Bit 4 Reserved........................................................................ 301
8.5.5.6 Bit 5 Reserved........................................................................ 301
8.5.5.7 Bit 6 Reserved........................................................................ 301
8.5.5.8 Transmit Short Packet (TSP) .................................................... 301
8.5.6 UDC Endpoint 4 Control/Status Register .................................................. 302
8.5.6.1 Receive FIFO Service (RFS)...................................................... 302
8.5.6.2 Receive Packet Complete (RPC) ................................................ 303
8.5.6.3 Receive Overflow (ROF)........................................................... 303
8.5.6.4 Bit 3 Reserved........................................................................ 303
8.5.6.5 Bit 4 Reserved........................................................................ 303
8.5.6.6 Bit 5 Reserved........................................................................ 303
8.5.6.7 Receive FIFO Not Empty (RNE)................................................. 303
8.5.6.8 Receive Short Packet (RSP)...................................................... 303
8.5.7 UDC Endpoint 5 Control/Status Register .................................................. 304
8.5.7.1 Transmit FIFO Service (TFS)..................................................... 304
8.5.7.2 Transmit Packet Complete (TPC)............................................... 305
8.5.7.3 Flush Tx FIFO (FTF)................................................................. 305
8.5.7.4 Transmit Underrun (TUR)......................................................... 305
8.5.7.5 Sent STALL (SST) ................................................................... 305
8.5.7.6 Force STALL (FST) .................................................................. 305
8.5.7.7 Bit 6 Reserved........................................................................ 306
8.5.7.8 Transmit Short Packet (TSP) .................................................... 306

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
10 Order Number: 306262-004US
8.5.8 UDC Endpoint 6 Control/Status Register...................................................307
8.5.8.1 Transmit FIFO Service (TFS).....................................................307
8.5.8.2 Transmit Packet Complete (TPC) ...............................................307
8.5.8.3 Flush Tx FIFO (FTF).................................................................307
8.5.8.4 Transmit Underrun (TUR) .........................................................307
8.5.8.5 Sent STALL (SST)....................................................................307
8.5.8.6 Force STALL (FST)...................................................................308
8.5.8.7 Bit 6 Reserved........................................................................308
8.5.8.8 Transmit Short Packet (TSP).....................................................308
8.5.9 UDC Endpoint 7 Control/Status Register...................................................309
8.5.9.1 Receive FIFO Service (RFS) ......................................................309
8.5.9.2 Receive Packet Complete (RPC).................................................309
8.5.9.3 Bit 2 Reserved........................................................................309
8.5.9.4 Bit 3 Reserved........................................................................309
8.5.9.5 Sent Stall (SST)......................................................................309
8.5.9.6 Force Stall (FST) .....................................................................310
8.5.9.7 Receive FIFO Not Empty (RNE)..................................................310
8.5.9.8 Receive Short Packet (RSP) ......................................................310
8.5.10 UDC Endpoint 8 Control/Status Register...................................................311
8.5.10.1 Transmit FIFO Service (TFS).....................................................311
8.5.10.2 Transmit Packet Complete (TPC) ...............................................311
8.5.10.3 Flush Tx FIFO (FTF).................................................................312
8.5.10.4 Transmit Underrun (TUR) .........................................................312
8.5.10.5 Bit 4 Reserved ........................................................................312
8.5.10.6 Bit 5 Reserved ........................................................................312
8.5.10.7 Bit 6 Reserved ........................................................................312
8.5.10.8 Transmit Short Packet (TSP).....................................................312
8.5.11 UDC Endpoint 9 Control/Status Register...................................................313
8.5.11.1 Receive FIFO Service (RFS) ......................................................313
8.5.11.2 Receive Packet Complete (RPC).................................................313
8.5.11.3 Receive Overflow (ROF) ...........................................................313
8.5.11.4 Bit 3 Reserved ........................................................................313
8.5.11.5 Bit 4 Reserved ........................................................................314
8.5.11.6 Bit 5 Reserved ........................................................................314
8.5.11.7 Receive FIFO Not Empty (RNE)..................................................314
8.5.11.8 Receive Short Packet (RSP) ......................................................314
8.5.12 UDC Endpoint 10 Control/Status Register.................................................315
8.5.12.1 Transmit FIFO Service (TFS).....................................................315
8.5.12.2 Transmit Packet Complete (TPC) ...............................................315
8.5.12.3 Flush Tx FIFO (FTF).................................................................315
8.5.12.4 Transmit Underrun (TUR) .........................................................315
8.5.12.5 Sent STALL (SST)....................................................................316
8.5.12.6 Force STALL (FST)...................................................................316
8.5.12.7 Bit 6 Reserved ........................................................................316
8.5.12.8 Transmit Short Packet (TSP).....................................................316
8.5.13 UDC Endpoint 11 Control/Status Register.................................................317
8.5.13.1 Transmit FIFO Service (TFS).....................................................317
8.5.13.2 Transmit Packet Complete (TPC) ...............................................317
8.5.13.3 Flush Tx FIFO (FTF).................................................................318
8.5.13.4 Transmit Underrun (TUR) .........................................................318
8.5.13.5 Sent STALL (SST)....................................................................318
8.5.13.6 Force STALL (FST)...................................................................318
8.5.13.7 Bit 6 Reserved ........................................................................318
8.5.13.8 Transmit Short Packet (TSP).....................................................318
8.5.14 UDC Endpoint 12 Control/Status Register.................................................319
8.5.14.1 Receive FIFO Service (RFS) ......................................................319
8.5.14.2 Receive Packet Complete (RPC).................................................320
8.5.14.3 Bit 2 Reserved ........................................................................320
8.5.14.4 Bit 3 Reserved ........................................................................320