Intel IXP45X User manual

Order Number: 306262-004US
Intel®IXP45X and Intel®IXP46X
Product Line of Network Processors
Developer’s Manual
August 2006

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
2Order Number: 306262-004US
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Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 3
Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Contents
1.0 Introduction.............................................................................................................38
1.1 About This Document.........................................................................................38
1.2 Intended Audience ............................................................................................38
1.3 How to Read This Document...............................................................................38
1.4 Other Relevant Documents.................................................................................38
1.5 Terminology and Conventions .............................................................................39
1.5.1 Number Representation...........................................................................42
1.5.2 Signal-Naming Convention ......................................................................42
1.5.3 Register Legend.....................................................................................43
2.0 Functional Overview ................................................................................................ 44
2.1 Key Functional Units..........................................................................................48
2.1.1 Network Processor Engines (NPEs)............................................................48
2.1.2 Internal Bus ..........................................................................................49
2.1.2.1 North AHB ...............................................................................49
2.1.2.2 South AHB...............................................................................50
2.1.2.3 Memory Port Interface...............................................................50
2.1.2.4 APB Bus ..................................................................................51
2.1.3 MII/SMII Interfaces................................................................................51
2.1.4 UTOPIA Level 2......................................................................................51
2.1.5 Universal Serial Bus (USB) Interfaces........................................................52
2.1.5.1 USB 1.1 Device Interface...........................................................52
2.1.5.2 USB 2.0 Host Interface..............................................................52
2.1.6 PCI Controller........................................................................................52
2.1.7 DDRI SDRAM Controller ..........................................................................53
2.1.8 Expansion Interface................................................................................54
2.1.9 High-Speed, Serial Interfaces...................................................................56
2.1.10 UARTs ..................................................................................................56
2.1.11 GPIO ....................................................................................................56
2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) .....................................57
2.1.13 Interrupt Controller ................................................................................57
2.1.14 Timers..................................................................................................58
2.1.15 IEEE-1588 Hardware Assist .....................................................................58
2.1.16 Synchronous Serial Protocol Interface .......................................................58
2.1.17 I2C Interface.........................................................................................59
2.1.18 AES/DES/SHA/MD-5 ............................................................................... 59
2.1.19 Cryptography Unit..................................................................................59
2.1.20 Queue Manager......................................................................................60
2.2 Intel XScale®Processor .....................................................................................60
2.2.1 Super Pipeline........................................................................................62
2.2.2 Branch Target Buffer ..............................................................................63
2.2.3 Instruction Memory Management Unit.......................................................63
2.2.4 Data Memory Management Unit ...............................................................64
2.2.5 Instruction Cache...................................................................................64
2.2.6 Data Cache ...........................................................................................65
2.2.7 Mini-Data Cache.....................................................................................65
2.2.8 Fill Buffer and Pend Buffer.......................................................................65
2.2.9 Write Buffer...........................................................................................66
2.2.10 Multiply-Accumulate Coprocessor .............................................................66
2.2.11 Performance Monitoring Unit....................................................................66
2.2.12 Debug Unit............................................................................................67
3.0 Intel XScale®Processor...........................................................................................69

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
4Order Number: 306262-004US
3.1 Memory Management Unit ..................................................................................69
3.1.1 Memory Attributes ..................................................................................70
3.1.1.1 Page (P) Attribute Bit.................................................................70
3.1.1.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits ....................70
3.1.2 Interaction of the MMU, Instruction Cache, and Data Cache..........................72
3.1.3 MMU Control ..........................................................................................73
3.1.3.1 Invalidate (Flush) Operation .......................................................73
3.1.3.2 Enabling/Disabling.....................................................................73
3.1.3.3 Locking Entries .........................................................................74
3.1.3.4 Round-Robin Replacement Algorithm ...........................................76
3.2 Instruction Cache ..............................................................................................77
3.2.1 Operation When Instruction Cache is Enabled.............................................77
3.2.1.1 Instruction-Cache ‘Miss’ .............................................................78
3.2.1.2 Instruction-Cache Line-Replacement Algorithm..............................79
3.2.1.3 Instruction-Cache Coherence ......................................................80
3.3 Branch Target Buffer..........................................................................................83
3.3.1 Branch Target Buffer (BTB) Operation .......................................................83
3.3.1.1 Reset.......................................................................................85
3.4 Data Cache.......................................................................................................85
3.4.1 Data Cache Overview ..............................................................................85
3.4.2 Cacheability...........................................................................................88
3.4.3 Reconfiguring the Data Cache as Data RAM................................................92
3.5 Configuration ....................................................................................................96
3.5.1 CP15 Registers.......................................................................................98
3.5.1.1 Register 0: ID & Cache Type Registers.........................................98
3.5.1.2 Register 1: Control and Auxiliary Control Registers ......................100
3.5.1.3 Register 2: Translation Table Base Register ................................102
3.5.1.4 Register 3: Domain Access Control Register................................102
3.5.1.5 Register 4: Reserved ...............................................................102
3.5.1.6 Register 5: Fault Status Register ...............................................102
3.5.1.7 Register 6: Fault Address Register.............................................103
3.5.1.8 Register 7: Cache Functions......................................................103
3.5.1.9 Register 8: TLB Operations.......................................................104
3.5.1.10 Register 9: Cache Lock Down....................................................105
3.5.1.11 Register 10: TLB Lock Down .....................................................106
3.5.1.12 Register 11-12: Reserved.........................................................106
3.5.1.13 Register 13: Process ID............................................................106
3.5.1.14 The PID Register Affect On Addresses ........................................107
3.5.1.15 Register 14: Breakpoint Registers..............................................107
3.5.1.16 Register 15: Coprocessor Access Register...................................107
3.5.2 CP14 Registers.....................................................................................108
3.5.2.1 Performance Monitoring Registers..............................................109
3.5.2.2 Clock and Power Management Registers.....................................109
3.5.2.3 Software Debug Registers ........................................................110
3.6 Software Debug...............................................................................................111
3.6.1 Definitions ...........................................................................................111
3.6.2 Debug Registers ...................................................................................111
3.6.3 Debug Modes .......................................................................................112
3.6.3.1 Halt Mode ..............................................................................112
3.6.3.2 Monitor Mode..........................................................................112
3.6.4 Debug Control and Status Register (DCSR) ..............................................112
3.6.4.1 Global Enable Bit (GE) .............................................................114
3.6.4.2 Halt Mode Bit (H) ....................................................................114
3.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR) ....................................114
3.6.4.4 Sticky Abort Bit (SA)................................................................114
3.6.4.5 Method of Entry Bits (MOE) ......................................................114
3.6.4.6 Trace Buffer Mode Bit (M).........................................................114

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 5
Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
3.6.4.7 Trace Buffer Enable Bit (E)....................................................... 114
3.6.5 Debug Exceptions................................................................................. 115
3.6.5.1 Halt Mode.............................................................................. 115
3.6.5.2 Monitor Mode ......................................................................... 117
3.6.6 HW Breakpoint Resources...................................................................... 117
3.6.6.1 Instruction Breakpoints............................................................ 118
3.6.6.2 Data Breakpoints.................................................................... 118
3.6.7 Software Breakpoints............................................................................ 120
3.6.8 Transmit/Receive Control Register.......................................................... 120
3.6.8.1 RX Register Ready Bit (RR) ...................................................... 121
3.6.8.2 Overflow Flag (OV) ................................................................. 122
3.6.8.3 Download Flag (D) .................................................................. 122
3.6.8.4 TX Register Ready Bit (TR)....................................................... 123
3.6.8.5 Conditional Execution Using TXRXCTRL...................................... 123
3.6.9 Transmit Register................................................................................. 124
3.6.10 Receive Register .................................................................................. 124
3.6.11 Debug JTAG Access .............................................................................. 124
3.6.11.1 SELDCSR JTAG Command........................................................ 125
3.6.11.2 SELDCSR JTAG Register........................................................... 125
3.6.11.3 DBGTX JTAG Command ........................................................... 127
3.6.11.4 DBGTX JTAG Register.............................................................. 127
3.6.11.5 DBGRX JTAG Command........................................................... 128
3.6.11.6 DBGRX JTAG Register.............................................................. 128
3.6.11.7 Debug JTAG Data Register Reset Values..................................... 132
3.6.12 Trace Buffer ........................................................................................ 132
3.6.12.1 Trace Buffer CP Registers......................................................... 132
3.6.13 Trace Buffer Entries.............................................................................. 134
3.6.13.1 Message Byte......................................................................... 134
3.6.13.2 Trace Buffer Usage.................................................................. 137
3.6.14 Downloading Code in ICache.................................................................. 139
3.6.14.1 LDIC JTAG Command .............................................................. 139
3.6.14.2 LDIC JTAG Data Register ......................................................... 140
3.6.14.3 LDIC Cache Functions.............................................................. 141
3.6.14.4 Loading IC During Reset .......................................................... 142
3.6.14.5 Dynamically Loading IC After Reset........................................... 147
3.6.14.6 Mini-Instruction Cache Overview............................................... 150
3.6.15 Halt Mode Software Protocol .................................................................. 150
3.6.15.1 Starting a Debug Session......................................................... 150
3.6.15.2 Implementing a Debug Handler ................................................ 152
3.6.15.3 Ending a Debug Session .......................................................... 155
3.6.16 Software Debug Notes and Errata........................................................... 156
3.7 Performance Monitoring ................................................................................... 157
3.7.1 Overview ............................................................................................ 157
3.7.2 Register Description.............................................................................. 158
3.7.2.1 Clock Counter (CCNT) ............................................................. 158
3.7.2.2 Performance Count Registers.................................................... 158
3.7.2.3 Performance Monitor Control Register........................................ 159
3.7.2.4 Interrupt Enable Register......................................................... 159
3.7.2.5 Overflow Flag Status Register................................................... 160
3.7.2.6 Event Select Register .............................................................. 161
3.7.3 Managing the Performance Monitor......................................................... 162
3.7.4 Performance Monitoring Events .............................................................. 162
3.7.4.1 Instruction Cache Efficiency Mode ............................................. 163
3.7.4.2 Data Cache Efficiency Mode...................................................... 163
3.7.4.3 Instruction Fetch Latency Mode ................................................ 164
3.7.4.4 Data/Bus Request Buffer Full Mode............................................ 164
3.7.4.5 Stall/Write-Back Statistics........................................................ 165

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
6Order Number: 306262-004US
3.7.4.6 Instruction TLB Efficiency Mode.................................................165
3.7.4.7 Data TLB Efficiency Mode .........................................................165
3.7.5 Multiple Performance Monitoring Run Statistics .........................................166
3.7.6 Examples.............................................................................................166
3.8 Programming Model .........................................................................................167
3.8.1 Intel®StrongARM*Architecture Compatibility...........................................167
3.8.2 Intel®StrongARM*Architecture Implementation Options ...........................168
3.8.2.1 Big-Endian versus Little-Endian.................................................168
3.8.2.2 26-Bit Architecture ..................................................................168
3.8.2.3 Thumb...................................................................................168
3.8.2.4 Intel®StrongARM*DSP-Enhanced Instruction Set .......................168
3.8.2.5 Base Register Update...............................................................169
3.8.3 Extensions to Intel®StrongARM*Architecture ..........................................169
3.8.3.1 DSP Coprocessor 0 (CP0) .........................................................169
3.8.3.2 New Page Attributes ................................................................175
3.8.3.3 Additions to CP15 Functionality .................................................176
3.8.3.4 Event Architecture...................................................................177
3.9 Performance Considerations..............................................................................181
3.9.1 Interrupt Latency..................................................................................181
3.9.2 Branch Prediction..................................................................................182
3.9.3 Addressing Modes.................................................................................182
3.9.4 Instruction Latencies.............................................................................182
3.9.4.1 Performance Terms .................................................................182
3.9.4.2 Branch Instruction Timings.......................................................184
3.9.4.3 Data Processing Instruction Timings...........................................184
3.9.4.4 Multiply Instruction Timings......................................................185
3.9.4.5 Saturated Arithmetic Instructions ..............................................187
3.9.4.6 Status Register Access Instructions............................................187
3.9.4.7 Load/Store Instructions............................................................187
3.9.4.8 Semaphore Instructions ...........................................................188
3.9.4.9 Coprocessor Instructions..........................................................188
3.9.4.10 Miscellaneous Instruction Timing ...............................................189
3.9.4.11 Thumb Instructions .................................................................189
3.10 Optimization Guide ..........................................................................................189
3.10.1 Introduction.........................................................................................189
3.10.1.1 About This Section ..................................................................190
3.10.2 Processor Pipeline.................................................................................190
3.10.2.1 General Pipeline Characteristics.................................................190
3.10.2.2 Instruction Flow Through the Pipeline.........................................192
3.10.2.3 Main Execution Pipeline............................................................193
3.10.2.4 Memory Pipeline......................................................................194
3.10.2.5 Multiply/Multiply Accumulate (MAC) Pipeline ...............................195
3.10.3 Basic Optimizations...............................................................................195
3.10.3.1 Conditional Instructions ...........................................................195
3.10.3.2 Bit Field Manipulation...............................................................199
3.10.3.3 Optimizing the Use of Immediate Values ....................................200
3.10.3.4 Optimizing Integer Multiply and Divide .......................................200
3.10.3.5 Effective Use of Addressing Modes.............................................201
3.10.4 Cache and Prefetch Optimizations ...........................................................201
3.10.4.1 Instruction Cache....................................................................201
3.10.4.2 Data and Mini Cache................................................................203
3.10.4.3 Cache Considerations...............................................................206
3.10.4.4 Prefetch Considerations............................................................207
3.10.5 Instruction Scheduling...........................................................................212
3.10.5.1 Scheduling Loads ....................................................................212
3.10.5.2 Scheduling Data Processing Instructions.....................................216
3.10.5.3 Scheduling Multiply Instructions ................................................217
3.10.5.4 Scheduling SWP and SWPB Instructions .....................................218

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
3.10.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR)............. 218
3.10.5.6 Scheduling the MIA and MIAPH Instructions................................ 219
3.10.5.7 Scheduling MRS and MSR Instructions ....................................... 219
3.10.5.8 Scheduling CP15 Coprocessor Instructions ................................. 220
3.10.6 Optimizing C Libraries........................................................................... 220
3.10.7 Optimizations for Size........................................................................... 220
3.10.7.1 Space/Performance Trade Off................................................... 220
4.0 Network Processor Engines (NPE) .........................................................................222
5.0 Internal Buses ....................................................................................................... 224
5.1 Internal Bus Arbiters........................................................................................ 225
5.1.1 Priority Mechanism ............................................................................... 225
5.2 Memory Map................................................................................................... 226
6.0 Ethernet MACs .......................................................................................................229
6.1 Ethernet Coprocessor....................................................................................... 230
6.1.1 Ethernet Coprocessor APB Interface........................................................ 230
6.1.2 Ethernet Coprocessor NPE Interface........................................................ 230
6.1.3 Ethernet Coprocessor MDIO Interface ..................................................... 231
6.1.4 Transmitting Ethernet Frames with MII Interfaces..................................... 233
6.1.5 Receiving Ethernet Frames with MII Interfaces......................................... 236
6.1.6 General Ethernet Coprocessor Configuration ............................................ 238
6.2 Register Descriptions Ethernet MACs.................................................................. 239
6.2.1 Ethernet MAC 0 on NPE B...................................................................... 240
6.2.2 Ethernet MAC 1 on NPE B...................................................................... 241
6.2.3 Ethernet MAC 2 on NPE B...................................................................... 243
6.2.4 Ethernet MAC 2 on NPE B...................................................................... 244
6.2.5 Ethernet MAC on NPE A......................................................................... 246
6.2.6 Ethernet MAC on NPE C......................................................................... 247
6.2.7 Transmit Control 1 ............................................................................... 249
6.2.8 Transmit Control 2 ............................................................................... 249
6.2.9 Receive Control 1................................................................................. 250
6.2.10 Receive Control 2................................................................................. 251
6.2.11 Random Seed ...................................................................................... 251
6.2.12 Threshold For Partially Empty................................................................. 251
6.2.13 Threshold For Partially Full..................................................................... 252
6.2.14 Buffer Size For Transmit........................................................................ 252
6.2.15 Transmit Deferral Parameter.................................................................. 253
6.2.16 Receive Deferral Parameter ................................................................... 253
6.2.17 Transmit Two Part Deferral Parameters 1 ................................................ 253
6.2.18 Transmit Two Part Deferral Parameters 2 ................................................ 254
6.2.19 Slot Time ............................................................................................ 254
6.2.20 MDIO Commands Registers ................................................................... 254
6.2.21 MDIO Command 1................................................................................ 255
6.2.22 MDIO Command 2................................................................................ 255
6.2.23 MDIO Command 3................................................................................ 255
6.2.24 MDIO Command 4................................................................................ 256
6.2.25 MDIO Status Registers.......................................................................... 256
6.2.26 MDIO Status 1..................................................................................... 256
6.2.27 MDIO Status 2..................................................................................... 257
6.2.28 MDIO Status 3..................................................................................... 257
6.2.29 MDIO Status 4..................................................................................... 257
6.2.30 Address Mask Registers......................................................................... 257
6.2.31 Address Mask 1.................................................................................... 258
6.2.32 Address Mask 2.................................................................................... 258

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
8Order Number: 306262-004US
6.2.33 Address Mask 3 ....................................................................................259
6.2.34 Address Mask 4 ....................................................................................259
6.2.35 Address Mask 5 ....................................................................................259
6.2.36 Address Mask 6 ....................................................................................260
6.2.37 Address Registers.................................................................................260
6.2.38 Address 1............................................................................................261
6.2.39 Address 2............................................................................................261
6.2.40 Address 3............................................................................................261
6.2.41 Address 4............................................................................................262
6.2.42 Address 5............................................................................................262
6.2.43 Address 6............................................................................................262
6.2.44 Threshold for Internal Clock ...................................................................263
6.2.45 Unicast Address Registers......................................................................263
6.2.46 Unicast Address 1.................................................................................264
6.2.47 Unicast Address 2.................................................................................264
6.2.48 Unicast Address 3.................................................................................264
6.2.49 Unicast Address 4.................................................................................264
6.2.50 Unicast Address 5.................................................................................265
6.2.51 Unicast Address 6.................................................................................265
6.2.52 Core Control ........................................................................................265
7.0 UTOPIA Level 2 ......................................................................................................268
7.1 Introduction....................................................................................................268
7.2 UTOPIA Transmit Module ..................................................................................269
7.3 UTOPIA Receive Module....................................................................................272
7.4 UTOPIA Level 2 Coprocessor / NPE Coprocessor: Bus Interface ..............................275
7.5 MPHY Polling Routines ......................................................................................275
7.6 UTOPIA Level 2 Clocks......................................................................................276
8.0 USB 1.1 Device Controller.......................................................................................278
8.1 USB Overview .................................................................................................278
8.2 Device Configuration........................................................................................279
8.3 USB Operation ................................................................................................280
8.3.1 Signalling Levels...................................................................................280
8.3.2 Bit Encoding.........................................................................................281
8.3.3 Field Formats .......................................................................................282
8.3.4 Packet Formats ....................................................................................283
8.3.4.1 Token Packet Type ..................................................................284
8.3.4.2 Start-of-Frame Packet Type......................................................284
8.3.4.3 Data Packet Type ....................................................................284
8.3.4.4 Handshake Packet Type ...........................................................285
8.3.5 Transaction Formats..............................................................................285
8.3.5.1 Bulk Transaction Type..............................................................285
8.3.5.2 Isochronous Transaction Type...................................................286
8.3.5.3 Control Transaction Type..........................................................286
8.3.5.4 Interrupt Transaction Type .......................................................287
8.3.6 UDC Device Requests............................................................................287
8.3.7 UDC Configuration ................................................................................288
8.4 UDC Hardware Connections...............................................................................289
8.4.1 Self-Powered Device .............................................................................289
8.4.2 Bus-Powered Devices ............................................................................289
8.5 Register Descriptions........................................................................................289
8.5.1 UDC Control Register ............................................................................291
8.5.1.1 UDC Enable............................................................................291
8.5.1.2 UDC Active.............................................................................292
8.5.1.3 UDC Resume (RSM).................................................................292

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
8.5.1.4 Resume Interrupt Request (RESIR) ........................................... 292
8.5.1.5 Suspend Interrupt Request (SUSIR) .......................................... 292
8.5.1.6 Suspend/Resume Interrupt Mask (SRM)..................................... 292
8.5.1.7 Reset Interrupt Request (RSTIR)............................................... 292
8.5.1.8 Reset Interrupt Mask (REM) ..................................................... 292
8.5.2 UDC Endpoint 0 Control/Status Register .................................................. 293
8.5.2.1 OUT Packet Ready (OPR) ......................................................... 294
8.5.2.2 IN Packet Ready (IPR)............................................................. 294
8.5.2.3 Flush Tx FIFO (FTF)................................................................. 294
8.5.2.4 Device Remote Wake-Up Feature (DRWF) .................................. 294
8.5.2.5 Sent Stall (SST)...................................................................... 294
8.5.2.6 Force Stall (FST)..................................................................... 295
8.5.2.7 Receive FIFO Not Empty (RNE)................................................. 295
8.5.2.8 Setup Active (SA) ................................................................... 295
8.5.3 UDC Endpoint 1 Control/Status Register .................................................. 296
8.5.3.1 Transmit FIFO Service (TFS)..................................................... 296
8.5.3.2 Transmit Packet Complete (TPC)............................................... 296
8.5.3.3 Flush Tx FIFO (FTF)................................................................. 296
8.5.3.4 Transmit Underrun (TUR)......................................................... 296
8.5.3.5 Sent STALL (SST) ................................................................... 297
8.5.3.6 Force STALL (FST) .................................................................. 297
8.5.3.7 Bit 6 Reserved........................................................................ 297
8.5.3.8 Transmit Short Packet (TSP) .................................................... 297
8.5.4 UDC Endpoint 2 Control/Status Register .................................................. 298
8.5.4.1 Receive FIFO Service (RFS)...................................................... 298
8.5.4.2 Receive Packet Complete (RPC) ................................................ 298
8.5.4.3 Bit 2 Reserved........................................................................ 298
8.5.4.4 Bit 2 Reserved........................................................................ 298
8.5.4.5 Sent Stall (SST)...................................................................... 299
8.5.4.6 Force Stall (FST)..................................................................... 299
8.5.4.7 Receive FIFO Not Empty (RNE)................................................. 299
8.5.4.8 Receive Short Packet (RSP)...................................................... 299
8.5.5 UDC Endpoint 3 Control/Status Register .................................................. 300
8.5.5.1 Transmit FIFO Service (TFS)..................................................... 300
8.5.5.2 Transmit Packet Complete (TPC)............................................... 301
8.5.5.3 Flush Tx FIFO (FTF)................................................................. 301
8.5.5.4 Transmit Underrun (TUR)......................................................... 301
8.5.5.5 Bit 4 Reserved........................................................................ 301
8.5.5.6 Bit 5 Reserved........................................................................ 301
8.5.5.7 Bit 6 Reserved........................................................................ 301
8.5.5.8 Transmit Short Packet (TSP) .................................................... 301
8.5.6 UDC Endpoint 4 Control/Status Register .................................................. 302
8.5.6.1 Receive FIFO Service (RFS)...................................................... 302
8.5.6.2 Receive Packet Complete (RPC) ................................................ 303
8.5.6.3 Receive Overflow (ROF)........................................................... 303
8.5.6.4 Bit 3 Reserved........................................................................ 303
8.5.6.5 Bit 4 Reserved........................................................................ 303
8.5.6.6 Bit 5 Reserved........................................................................ 303
8.5.6.7 Receive FIFO Not Empty (RNE)................................................. 303
8.5.6.8 Receive Short Packet (RSP)...................................................... 303
8.5.7 UDC Endpoint 5 Control/Status Register .................................................. 304
8.5.7.1 Transmit FIFO Service (TFS)..................................................... 304
8.5.7.2 Transmit Packet Complete (TPC)............................................... 305
8.5.7.3 Flush Tx FIFO (FTF)................................................................. 305
8.5.7.4 Transmit Underrun (TUR)......................................................... 305
8.5.7.5 Sent STALL (SST) ................................................................... 305
8.5.7.6 Force STALL (FST) .................................................................. 305
8.5.7.7 Bit 6 Reserved........................................................................ 306
8.5.7.8 Transmit Short Packet (TSP) .................................................... 306

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
10 Order Number: 306262-004US
8.5.8 UDC Endpoint 6 Control/Status Register...................................................307
8.5.8.1 Transmit FIFO Service (TFS).....................................................307
8.5.8.2 Transmit Packet Complete (TPC) ...............................................307
8.5.8.3 Flush Tx FIFO (FTF).................................................................307
8.5.8.4 Transmit Underrun (TUR) .........................................................307
8.5.8.5 Sent STALL (SST)....................................................................307
8.5.8.6 Force STALL (FST)...................................................................308
8.5.8.7 Bit 6 Reserved........................................................................308
8.5.8.8 Transmit Short Packet (TSP).....................................................308
8.5.9 UDC Endpoint 7 Control/Status Register...................................................309
8.5.9.1 Receive FIFO Service (RFS) ......................................................309
8.5.9.2 Receive Packet Complete (RPC).................................................309
8.5.9.3 Bit 2 Reserved........................................................................309
8.5.9.4 Bit 3 Reserved........................................................................309
8.5.9.5 Sent Stall (SST)......................................................................309
8.5.9.6 Force Stall (FST) .....................................................................310
8.5.9.7 Receive FIFO Not Empty (RNE)..................................................310
8.5.9.8 Receive Short Packet (RSP) ......................................................310
8.5.10 UDC Endpoint 8 Control/Status Register...................................................311
8.5.10.1 Transmit FIFO Service (TFS).....................................................311
8.5.10.2 Transmit Packet Complete (TPC) ...............................................311
8.5.10.3 Flush Tx FIFO (FTF).................................................................312
8.5.10.4 Transmit Underrun (TUR) .........................................................312
8.5.10.5 Bit 4 Reserved ........................................................................312
8.5.10.6 Bit 5 Reserved ........................................................................312
8.5.10.7 Bit 6 Reserved ........................................................................312
8.5.10.8 Transmit Short Packet (TSP).....................................................312
8.5.11 UDC Endpoint 9 Control/Status Register...................................................313
8.5.11.1 Receive FIFO Service (RFS) ......................................................313
8.5.11.2 Receive Packet Complete (RPC).................................................313
8.5.11.3 Receive Overflow (ROF) ...........................................................313
8.5.11.4 Bit 3 Reserved ........................................................................313
8.5.11.5 Bit 4 Reserved ........................................................................314
8.5.11.6 Bit 5 Reserved ........................................................................314
8.5.11.7 Receive FIFO Not Empty (RNE)..................................................314
8.5.11.8 Receive Short Packet (RSP) ......................................................314
8.5.12 UDC Endpoint 10 Control/Status Register.................................................315
8.5.12.1 Transmit FIFO Service (TFS).....................................................315
8.5.12.2 Transmit Packet Complete (TPC) ...............................................315
8.5.12.3 Flush Tx FIFO (FTF).................................................................315
8.5.12.4 Transmit Underrun (TUR) .........................................................315
8.5.12.5 Sent STALL (SST)....................................................................316
8.5.12.6 Force STALL (FST)...................................................................316
8.5.12.7 Bit 6 Reserved ........................................................................316
8.5.12.8 Transmit Short Packet (TSP).....................................................316
8.5.13 UDC Endpoint 11 Control/Status Register.................................................317
8.5.13.1 Transmit FIFO Service (TFS).....................................................317
8.5.13.2 Transmit Packet Complete (TPC) ...............................................317
8.5.13.3 Flush Tx FIFO (FTF).................................................................318
8.5.13.4 Transmit Underrun (TUR) .........................................................318
8.5.13.5 Sent STALL (SST)....................................................................318
8.5.13.6 Force STALL (FST)...................................................................318
8.5.13.7 Bit 6 Reserved ........................................................................318
8.5.13.8 Transmit Short Packet (TSP).....................................................318
8.5.14 UDC Endpoint 12 Control/Status Register.................................................319
8.5.14.1 Receive FIFO Service (RFS) ......................................................319
8.5.14.2 Receive Packet Complete (RPC).................................................320
8.5.14.3 Bit 2 Reserved ........................................................................320
8.5.14.4 Bit 3 Reserved ........................................................................320

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
8.5.14.5 Sent Stall (SST)...................................................................... 320
8.5.14.6 Force Stall (FST)..................................................................... 320
8.5.14.7 Receive FIFO Not Empty (RNE)................................................. 320
8.5.14.8 Receive Short Packet (RSP)...................................................... 321
8.5.15 UDC Endpoint 13 Control/Status Register ................................................ 321
8.5.15.1 Transmit FIFO Service (TFS)..................................................... 322
8.5.15.2 Transmit Packet Complete (TPC)............................................... 322
8.5.15.3 Flush Tx FIFO (FTF)................................................................. 322
8.5.15.4 Transmit Underrun (TUR)......................................................... 322
8.5.15.5 Bit 4 Reserved........................................................................ 322
8.5.15.6 Bit 5 Reserved........................................................................ 322
8.5.15.7 Bit 6 Reserved........................................................................ 322
8.5.15.8 Transmit Short Packet (TSP) .................................................... 322
8.5.16 UDC Endpoint 14 Control/Status Register ................................................ 323
8.5.16.1 Receive FIFO Service (RFS)...................................................... 323
8.5.16.2 Receive Packet Complete (RPC) ................................................ 324
8.5.16.3 Receive Overflow (ROF)........................................................... 324
8.5.16.4 Bit 3 Reserved........................................................................ 324
8.5.16.5 Bit 4 Reserved........................................................................ 324
8.5.16.6 Bit 5 Reserved........................................................................ 324
8.5.16.7 Receive FIFO Not Empty (RNE)................................................. 324
8.5.16.8 Receive Short Packet (RSP)...................................................... 324
8.5.17 UDC Endpoint 15 Control/Status Register ................................................ 325
8.5.17.1 Transmit FIFO Service (TFS)..................................................... 325
8.5.17.2 Transmit Packet Complete (TPC)............................................... 326
8.5.17.3 Flush Tx FIFO (FTF)................................................................. 326
8.5.17.4 Transmit Underrun (TUR)......................................................... 326
8.5.17.5 Sent STALL (SST) ................................................................... 326
8.5.17.6 Force STALL (FST) .................................................................. 326
8.5.17.7 Bit 6 Reserved........................................................................ 327
8.5.17.8 Transmit Short Packet (TSP) .................................................... 327
8.5.18 UDC Interrupt Control Register 0............................................................ 328
8.5.18.1 Interrupt Mask Endpoint x (IMx), where x is 0 through 7.............. 328
8.5.19 UDC Interrupt Control Register 1............................................................ 329
8.5.19.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15............ 329
8.5.20 UDC Status/Interrupt Register 0............................................................. 330
8.5.20.1 Endpoint 0 Interrupt Request (IR0) ........................................... 330
8.5.20.2 Endpoint 1 Interrupt Request (IR1) ........................................... 331
8.5.20.3 Endpoint 2 Interrupt Request (IR2) ........................................... 331
8.5.20.4 Endpoint 3 Interrupt Request (IR3) ........................................... 331
8.5.20.5 Endpoint 4 Interrupt Request (IR4) ........................................... 331
8.5.20.6 Endpoint 5 Interrupt Request (IR5) ........................................... 331
8.5.20.7 Endpoint 6 Interrupt Request (IR6) ........................................... 331
8.5.20.8 Endpoint 7 Interrupt Request (IR7) ........................................... 331
8.5.21 UDC Status/Interrupt Register 1............................................................. 332
8.5.21.1 Endpoint 8 Interrupt Request (IR8) ........................................... 332
8.5.21.2 Endpoint 9 Interrupt Request (IR9) ........................................... 332
8.5.21.3 Endpoint 10 Interrupt Request (IR10)........................................ 333
8.5.21.4 Endpoint 11 Interrupt Request (IR11)........................................ 333
8.5.21.5 Endpoint 12 Interrupt Request (IR12)........................................ 333
8.5.21.6 Endpoint 13 Interrupt Request (IR13)........................................ 333
8.5.21.7 Endpoint 14 Interrupt Request (IR14)........................................ 333
8.5.21.8 Endpoint 15 Interrupt Request (IR15)........................................ 333
8.5.22 UDC Frame Number High Register.......................................................... 334
8.5.22.1 UDC Frame Number MSB (FNMSB)............................................ 334
8.5.22.2 Isochronous Packet Error Endpoint 4 (IPE4) ............................... 335
8.5.22.3 Isochronous Packet Error Endpoint 9 (IPE9) ............................... 335
8.5.22.4 Isochronous Packet Error Endpoint 14 (IPE14)............................ 335

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
12 Order Number: 306262-004US
8.5.22.5 Start of Frame Interrupt Mask (SIM)..........................................335
8.5.22.6 Start of Frame Interrupt Request (SIR) ......................................335
8.5.23 UDC Frame Number Low Register ...........................................................336
8.5.24 UDC Byte Count Register 2 ....................................................................337
8.5.24.1 Endpoint 2 Byte Count (BC[7:0])...............................................337
8.5.25 UDC Byte Count Register 4 ....................................................................338
8.5.25.1 Endpoint 4 Byte Count (BC[7:0])...............................................338
8.5.26 UDC Byte Count Register 7 ....................................................................338
8.5.26.1 Endpoint 7 Byte Count (BC[7:0])...............................................339
8.5.27 UDC Byte Count Register 9 ....................................................................339
8.5.27.1 Endpoint 9 Byte Count (BC[7:0])...............................................339
8.5.28 UDC Byte Count Register 12...................................................................340
8.5.28.1 Endpoint 12 Byte Count (BC[7:0]).............................................340
8.5.29 UDC Byte Count Register 14...................................................................341
8.5.29.1 Endpoint 14 Byte Count (BC[7:0]).............................................341
8.5.30 UDC Endpoint 0 Data Register ................................................................341
8.5.31 UDC Data Register 1 .............................................................................342
8.5.32 UDC Data Register 2 .............................................................................343
8.5.33 UDC Data Register 3 .............................................................................343
8.5.34 UDC Data Register 4 .............................................................................344
8.5.35 UDC Data Register 5 .............................................................................345
8.5.36 UDC Data Register 6 .............................................................................345
8.5.37 UDC Data Register 7 .............................................................................346
8.5.38 UDC Data Register 8 .............................................................................346
8.5.39 UDC Data Register 9 .............................................................................347
8.5.40 UDC Data Register 10 ...........................................................................348
8.5.41 UDC Data Register 11 ...........................................................................348
8.5.42 UDC Data Register 12 ...........................................................................349
8.5.43 UDC Data Register 13 ...........................................................................349
8.5.44 UDC Data Register 14 ...........................................................................350
8.5.45 UDC Data Register 15 ...........................................................................351
9.0 USB 2.0 Host Controller..........................................................................................352
9.1 Overview........................................................................................................352
9.2 USB...............................................................................................................352
9.3 USB 2.0..........................................................................................................353
9.4 Feature List ....................................................................................................354
9.5 Block Diagram.................................................................................................355
9.6 Theory of Operation.........................................................................................355
9.6.1 Software Model ....................................................................................355
9.6.2 Host Data Structure ..............................................................................355
9.6.3 Hardware Model ...................................................................................358
9.6.3.1 Block Diagram ........................................................................358
9.6.3.2 Microprocessor Interface ..........................................................359
9.6.3.3 DMA Engine............................................................................360
9.6.3.4 Dual Port RAM Controller..........................................................361
9.6.3.5 Protocol Engine.......................................................................361
9.6.3.6 Port Controller ........................................................................362
9.6.3.7 System Bus Interface...............................................................363
9.7 System Level Issues and Core Configuration........................................................363
9.7.1 Configuration Constants ........................................................................363
9.8 Detailed Register Descriptions ...........................................................................364
9.9 Configuration, Control and Status Register Set ....................................................366
9.10 Identification Registers.....................................................................................367
9.10.1 ID ......................................................................................................367
9.10.2 HWGENERAL........................................................................................367

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
9.10.3 HWHOST............................................................................................. 368
9.10.4 HWDEVICE.......................................................................................... 368
9.10.5 HWTXBUF ........................................................................................... 369
9.10.6 HWRXBUF ........................................................................................... 369
9.11 Host Capability Registers.................................................................................. 370
9.11.1 CAPLENGTH – EHCI Compliant ............................................................... 370
9.11.2 HCIVERSION – EHCI Compliant.............................................................. 370
9.11.3 HCSPARAMS – EHCI Compliant with Extensions........................................ 370
9.11.4 HCCPARAMS – EHCI Compliant .............................................................. 371
9.11.5 Reserved Register #1 ........................................................................... 372
9.11.6 DCCPARAMS (Non-EHCI)....................................................................... 372
9.12 Host Operational Registers ............................................................................... 373
9.12.1 USBCMD ............................................................................................. 373
9.12.2 USBSTS .............................................................................................. 375
9.12.3 USBINTR............................................................................................. 377
9.12.4 FRINDEX............................................................................................. 378
9.12.5 CTRLDSSEGMENT................................................................................. 379
9.12.6 PERIODICLISTBASE.............................................................................. 379
9.12.6.1 Host Controller (PERIODICLISTBASE) ........................................ 379
9.12.7 ASYNCLISTADDR; ENDPOINTLISTADDR .................................................. 380
9.12.7.1 Host Controller (ASYNCLISTADDR)............................................ 380
9.12.8 BURSTSIZE ......................................................................................... 380
9.12.9 TXFILLTUNING..................................................................................... 381
9.12.10CONFIGFLAG ....................................................................................... 381
9.12.11PORTSCx ............................................................................................ 382
9.12.11.1Host Controller....................................................................... 382
9.12.12USBMODE ........................................................................................... 387
9.13 Host Data Structures ....................................................................................... 387
9.13.1 Periodic Frame List ............................................................................... 388
9.13.2 Asynchronous List Queue Head Pointer.................................................... 390
9.13.3 Isochronous (High-Speed) Transfer Descriptor (iTD) ................................. 391
9.13.3.1 Next Link Pointer .................................................................... 392
9.13.3.2 iTD Transaction Status and Control List...................................... 393
9.13.3.3 iTD Buffer Page Pointer List (Plus)............................................. 394
9.13.4 Split Transaction Isochronous Transfer Descriptor (siTD) ........................... 395
9.13.4.1 Next Link Pointer .................................................................... 395
9.13.4.2 siTD Endpoint Capabilities/Characteristics .................................. 396
9.13.4.3 siTD Transfer State ................................................................. 397
9.13.4.4 siTD Buffer Pointer List (Plus)................................................... 398
9.13.4.5 siTD Back Link Pointer............................................................. 398
9.13.5 Queue Element Transfer Descriptor (qTD)................................................ 399
9.13.5.1 Next qTD Pointer .................................................................... 400
9.13.5.2 Alternate Next qTD Pointer....................................................... 400
9.13.5.3 qTD Token............................................................................. 400
9.13.5.4 qTD Buffer Page Pointer List..................................................... 403
9.13.6 Queue Head ........................................................................................ 404
9.13.6.1 Queue Head Horizontal Link Pointer........................................... 404
9.13.6.2 Endpoint Capabilities/Characteristics ......................................... 405
9.13.6.3 Transfer Overlay..................................................................... 407
9.13.7 Periodic Frame Span Traversal Node (FSTN) ............................................ 408
9.13.7.1 FSTN Normal Path Pointer........................................................ 408
9.13.7.2 FSTN Back Path Link Pointer..................................................... 409
9.14 Host Operational Model.................................................................................... 409
9.14.1 Host Controller Initialization................................................................... 410
9.14.2 Port Routing and Control....................................................................... 411
9.14.2.1 Port Routing Control via EHCI Configured (CF) Bit ....................... 412

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
14 Order Number: 306262-004US
9.14.2.2 Port Routing Control via PortOwner and Disconnect Event.............413
9.14.2.3 Example Port Routing State Machine..........................................414
9.14.2.4 Port Power .............................................................................415
9.14.2.5 Port Reporting Over-Current .....................................................415
9.14.3 Suspend/Resume..................................................................................416
9.14.3.1 Port Suspend/Resume..............................................................416
9.14.4 Schedule Traversal Rules.......................................................................418
9.14.4.1 Example: Preserving Micro-Frame Integrity.................................420
9.14.5 Periodic Schedule Frame Boundaries versus Bus Frame Boundaries .............423
9.14.6 Periodic Schedule .................................................................................425
9.14.7 Managing Isochronous Transfers Using iTDs .............................................426
9.14.7.1 Host Controller Operational Model for iTDs..................................426
9.14.7.2 Software Operational Model for iTDs ..........................................428
9.14.8 Asynchronous Schedule.........................................................................430
9.14.8.1 Adding Queue Heads to Asynchronous Schedule..........................431
9.14.8.2 Removing Queue Heads from Asynchronous Schedule..................432
9.14.8.3 Empty Asynchronous Schedule Detection....................................435
9.14.8.4 Restarting Asynchronous Schedule Before EOF............................435
9.14.8.5 Asynchronous Schedule Traversal: Start Event............................438
9.14.8.6 Reclamation Status Bit (USBSTS Register)..................................438
9.14.9 Operational Model for Nak Counter..........................................................439
9.14.9.1 Nak Count Reload Control.........................................................440
9.14.10Managing Control/Bulk/Interrupt Transfers via Queue Heads ......................441
9.14.10.1Fetch Queue Head...................................................................443
9.14.10.2Advance Queue.......................................................................443
9.14.10.3Execute Transaction ................................................................444
9.14.10.4Write Back qTD.......................................................................449
9.14.10.5Follow Queue Head Horizontal Pointer ........................................449
9.14.10.6Buffer Pointer List Use for Data Streaming with qTDs ...................449
9.14.10.7Adding Interrupt Queue Heads to the Periodic Schedule................451
9.14.10.8Managing Transfer Complete Interrupts from Queue Heads...........451
9.14.11Ping Control.........................................................................................452
9.14.12Split Transactions .................................................................................453
9.14.12.1Split Transactions for Asynchronous Transfers.............................453
9.14.12.2Split Transaction Interrupt........................................................455
9.14.12.3Split Transaction Isochronous ...................................................468
9.14.13Host Controller Pause............................................................................481
9.14.14Port Test Modes....................................................................................481
9.14.15Interrupts............................................................................................482
9.14.15.1Transfer/Transaction Based Interrupts .......................................483
9.14.15.2Host Controller Event Interrupts................................................485
9.15 EHCI Deviation................................................................................................486
9.15.1 Embedded Transaction Translator Function...............................................486
9.15.1.1 Capability Registers.................................................................487
9.15.1.2 Operational Registers...............................................................487
9.15.1.3 Discovery...............................................................................487
9.15.1.4 Data Structures ......................................................................488
9.15.1.5 Operational Model ...................................................................488
9.15.2 Device Operation..................................................................................490
9.15.2.1 USBMODE Register..................................................................490
9.15.2.2 EHCI Reserved Fields...............................................................490
9.15.2.3 SOF Interrupt .........................................................................491
9.15.3 Embedded Design Interface ...................................................................491
9.15.3.1 Frame Adjust Register..............................................................491
9.15.4 Miscellaneous Variations from EHCI.........................................................491
9.15.4.1 Programmable Physical Interface Behavior..................................491
9.15.4.2 Discovery...............................................................................491

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
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Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
9.15.4.3 Port Test Mode ....................................................................... 492
9.16 Compatibility .................................................................................................. 493
9.17 Power-Management Requirements..................................................................... 493
9.17.1 USB Power States ................................................................................ 493
9.17.2 Host Power States................................................................................ 493
9.18 Error/Abnormal Conditions ............................................................................... 493
10.0 PCI Controller ........................................................................................................ 495
10.1 Introduction ................................................................................................... 495
10.2 Overview ....................................................................................................... 495
10.2.1 List of Features.................................................................................... 500
10.2.2 PCI Controller Configured as Host........................................................... 501
10.2.2.1 Example: Generating a PCI Configuration Write and Read ............ 503
10.2.3 PCI Controller Configured as Option........................................................ 504
10.2.4 Initializing PCI Controller Configuration and Status Registers
for Data Transactions............................................................................ 505
10.2.4.1 Example: AHB Memory Base Address Register, AHB I/O Base
Address Register, and PCI Memory Base Address Register............ 507
10.2.4.2 Example: PCI Memory Base Address Register and
South-AHB Translation ............................................................ 508
10.2.5 Initializing the PCI Controller Configuration Registers ................................ 509
10.2.6 PCI Controller South AHB Transactions.................................................... 512
10.2.7 PCI Controller Functioning as Bus Initiator ............................................... 512
10.2.7.1 Initiated Type-0 Read Transaction............................................. 513
10.2.7.2 Initiated Type-0 Write Transaction ............................................ 513
10.2.7.3 Initiated Type-1 Read Transaction............................................. 514
10.2.7.4 Initiated Type-1 Write Transaction ............................................ 515
10.2.7.5 Initiated Memory Read Transaction ........................................... 516
10.2.7.6 Initiated Memory Write Transaction........................................... 517
10.2.7.7 Initiated I/O Read Transaction.................................................. 517
10.2.7.8 Initiated I/O Write Transaction ................................................. 518
10.2.7.9 Initiated Burst Memory Read Transaction ................................... 519
10.2.7.10Initiated Burst Memory Write Transaction................................... 520
10.2.8 PCI Controller Functioning as Bus Target ................................................. 521
10.2.9 PCI Controller Door Bell Register ............................................................ 521
10.3 Functional Description...................................................................................... 522
10.3.1 PCI Byte-Enable Generation................................................................... 522
10.3.2 PCI Core ............................................................................................. 522
10.3.2.1 PCI Target Interface................................................................ 523
10.3.2.2 PCI Initiator Interface.............................................................. 524
10.3.2.3 PCI Host Functions.................................................................. 526
10.3.2.4 PCI Controller Clock and Reset Generation ................................. 528
10.3.2.5 PCI Configuration Register Access ............................................. 528
10.3.2.6 PCI Pad Drive Strength Compensation Support ........................... 529
10.3.2.7 AHB Master Interface .............................................................. 530
10.3.2.8 AHB Master Writes.................................................................. 531
10.3.2.9 AHB Master Reads .................................................................. 532
10.3.2.10AHB Slave Interface................................................................ 532
10.3.2.11PCI Byte Enable Generation...................................................... 535
10.3.3 PCI Controller DMA............................................................................... 536
10.3.3.1 AHB-to-PCI DMA Channel Operation.......................................... 540
10.3.3.2 PCI-to-AHB DMA Channel Operation.......................................... 540
10.3.4 Data Byte Alignment and Addressing — PCI Endianness............................. 541
10.3.5 PCI Controller Interrupts ....................................................................... 547
10.3.5.1 PCI Interrupt Generation ......................................................... 547
10.3.5.2 Internal Interrupt Generation ................................................... 548
10.4 PCI RCOMP Circuitry ........................................................................................ 549

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
16 Order Number: 306262-004US
10.5 Register Descriptions........................................................................................549
10.5.1 PCI Configuration Registers....................................................................549
10.5.2 PCI Configuration Register Descriptions ...................................................550
10.5.2.1 Device ID/Vendor ID Register ...................................................550
10.5.2.2 Status Register/Control Register................................................551
10.5.2.3 Class Code/Revision ID Register................................................552
10.5.2.4 BIST/Header Type/Latency Timer/Cache Line Register..................553
10.5.2.5 Base Address 0 Register...........................................................553
10.5.2.6 Base Address 1 Register...........................................................554
10.5.2.7 Base Address 2 Register...........................................................554
10.5.2.8 Base Address 3 Register...........................................................555
10.5.2.9 Base Address 4 Register...........................................................555
10.5.2.10Base Address 5 Register...........................................................556
10.5.2.11Subsystem ID/Subsystem Vendor ID Register.............................556
10.5.2.12Max_Lat, Min_gnt, Interrupt Pin, and Interrupt Line Register.........557
10.5.2.13Retry Timeout/trdy Timeout Register .........................................557
10.5.3 PCI Controller Configuration and Status Registers (CSRs)...........................558
10.5.3.1 PCI Controller Non-Prefetch Address Register..............................559
10.5.3.2 PCI Controller Non-Prefetch Command/Byte Enables Register........559
10.5.3.3 PCI Controller Non-Prefetch Write Data Register..........................560
10.5.3.4 PCI Controller Non-Prefetch Read Data Register ..........................560
10.5.3.5 PCI Controller Configuration Port Address/Command/Byte
Enables Register .....................................................................561
10.5.3.6 PCI Controller Configuration Port Write Data Register...................562
10.5.3.7 PCI Controller Configuration Port Read Data Register ...................562
10.5.3.8 PCI Controller Control and Status Register..................................563
10.5.3.9 PCI Controller Interrupt Status Register .....................................564
10.5.3.10PCI Controller Interrupt Enable Register.....................................565
10.5.3.11DMA Control Register...............................................................565
10.5.3.12AHB Memory Base Address Register...........................................566
10.5.3.13AHB I/O Base Address Register .................................................567
10.5.3.14PCI Memory Base Address Register............................................567
10.5.3.15AHB Doorbell Register..............................................................568
10.5.3.16PCI Doorbell Register...............................................................569
10.5.3.17AHB-to-PCI DMA AHB Address Register 0 ...................................569
10.5.3.18AHB-to-PCI DMA PCI Address Register 0.....................................570
10.5.3.19AHB-to-PCI DMA Length Register 0............................................570
10.5.3.20AHB-to-PCI DMA AHB Address Register 1 ...................................571
10.5.3.21AHB-to-PCI DMA PCI Address Register 1.....................................571
10.5.3.22AHB-to-PCI DMA Length Register 1............................................572
10.5.3.23PCI-to-AHB DMA AHB Address Register 0 ...................................572
10.5.3.24PCI-to-AHB DMA PCI Address Register 0.....................................573
10.5.3.25PCI-to-AHB DMA Length Register 0............................................573
10.5.3.26PCI-to-AHB DMA AHB Address Register 1 ...................................574
10.5.3.27PCI-to-AHB DMA PCI Address Register 1.....................................574
10.5.3.28PCI-to-AHB DMA Length Register 1............................................575
10.6 Error/Abnormal Conditions................................................................................575
10.6.1 Error Handling as a PCI Target ...............................................................575
10.6.2 Error Handling as a PCI Initiator During PCI Direct Access
from the AHB Bus.................................................................................577
10.6.3 Error Handling as a PCI Initiator During Non-Prefetch Operations ................578
10.6.4 Error Handling During PCI-to-AHB DMA Channel Operations .......................578
10.6.5 Error Handling During AHB-to-PCI DMA Channel Operations .......................579
11.0 Memory Controller..................................................................................................581
11.1 Overview........................................................................................................581
11.2 Theory of Operation.........................................................................................582
11.2.1 Functional Blocks..................................................................................582
11.2.1.1 Transaction Ports ....................................................................584

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 17
Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
11.2.1.2 Address Decode Blocks............................................................ 585
11.2.1.3 Memory Transaction Queues .................................................... 586
11.2.1.4 Configuration Registers............................................................ 586
11.2.1.5 Refresh Counter ..................................................................... 586
11.2.1.6 DDRI SDRAM Control Block ...................................................... 587
11.2.1.7 DDRI SDRAM RCOMP Block ...................................................... 587
11.2.2 DDRI SDRAM Memory Support............................................................... 587
11.2.2.1 DDRI SDRAM Interface............................................................ 588
11.2.2.2 DDRI SDRAM Bank Sizes and Configurations .............................. 590
11.2.2.3 MTCTR Register Setup............................................................. 593
11.2.2.4 DDRI SDRAM Addressing ......................................................... 593
11.2.2.5 32-Bit Data Bus Width............................................................. 594
11.2.2.6 Page Hit/Miss Determination .................................................... 595
11.2.2.7 DDRI SDRAM Commands......................................................... 598
11.2.2.8 DDRI SDRAM Initialization........................................................ 598
11.2.2.9 DDRI SDRAM Mode Programming.............................................. 602
11.2.2.10DDRI SDRAM Read Cycle ......................................................... 606
11.2.2.11DDRI SDRAM Write Cycle......................................................... 609
11.2.2.12DDRI SDRAM Refresh Cycle...................................................... 612
11.2.3 Error Correction and Detection............................................................... 614
11.2.3.1 ECC Generation ...................................................................... 615
11.2.3.2 ECC Generation for Partial Writes.............................................. 617
11.2.3.3 ECC Checking......................................................................... 620
11.2.3.4 Scrubbing.............................................................................. 624
11.2.3.5 ECC Disabled.......................................................................... 625
11.2.3.6 ECC Testing ........................................................................... 625
11.2.4 Overlapping Memory Regions................................................................. 626
11.2.5 DDRI SDRAM Clocking .......................................................................... 626
11.2.6 Performance Monitoring ........................................................................ 626
11.3 Power Failure Mode ......................................................................................... 627
11.4 Interrupts/Error Conditions............................................................................... 627
11.4.1 Single-Bit Error Detection...................................................................... 628
11.4.2 Multi-Bit Error Detection........................................................................ 629
11.5 Reset Conditions ............................................................................................. 629
11.6 Register Definitions ......................................................................................... 630
11.6.1 DDRI SDRAM Initialization Register SDIR................................................. 632
11.6.2 DDRI SDRAM Control Register 0 SDCR0 .................................................. 633
11.6.3 DDRI SDRAM Control Register 1 SDCR1 .................................................. 635
11.6.4 DDRI SDRAM Base Register SDBR .......................................................... 637
11.6.5 DDRI SDRAM Boundary Register 0 SBR0 ................................................. 638
11.6.6 DDRI SDRAM Boundary Register 1 SBR1 ................................................. 639
11.6.7 ECC Control Register ECCR.................................................................... 640
11.6.8 ECC Log Registers ELOG0, ELOG1........................................................... 641
11.6.9 ECC Address Registers ECAR0, ECAR1..................................................... 642
11.6.10ECC Test Register ECTST....................................................................... 643
11.6.11Memory Controller Interrupt Status Register MCISR.................................. 644
11.6.12MCU Port Transaction Count Register MPTCR............................................ 645
11.6.13MCU Preemption Control Register MPCR .................................................. 645
11.6.14Refresh Frequency Register RFR............................................................. 646
11.6.15SDRAM Page Registers SDPR0-7............................................................. 647
12.0 Expansion Bus Controller ....................................................................................... 649
12.1 Overview ....................................................................................................... 649
12.2 Feature List.................................................................................................... 649
12.3 Block Diagram ................................................................................................ 650
12.4 Theory of Operation......................................................................................... 650
12.4.1 Outbound Transfers.............................................................................. 650

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
18 Order Number: 306262-004US
12.4.1.1 Expansion Bus Address Space...................................................653
12.4.1.2 Chip Select Address Allocation...................................................653
12.4.1.3 Address and Data Byte Steering................................................655
12.4.1.4 Expansion Bus Interface Configuration .......................................658
12.4.1.5 Using I/O Wait........................................................................661
12.4.1.6 Parity ....................................................................................663
12.4.1.7 Special Design Knowledge for Using HPI mode ............................664
12.4.1.8 Expansion Bus Outbound Timing Diagrams .................................665
12.4.2 Inbound Transfers ................................................................................681
12.4.2.1 Parity ....................................................................................686
12.4.3 Arbitration ...........................................................................................686
12.4.3.1 Internal Arbitration..................................................................687
12.4.3.2 External Arbiter.......................................................................688
12.4.4 Multiple Processors Connected by the Expansion Bus.................................688
12.4.5 Expansion Bus Inbound Timing Diagrams.................................................690
12.4.5.1 Back-to-Back 1-Word Inbound Write with EX_SLAVE_CS_N
Deasserted.............................................................................690
12.4.5.2 Back-to-Back 1-Word Writes without Deasserting
EX_SLAVE_CS_N.....................................................................690
12.4.5.3 Eight-Word Inbound Write........................................................691
12.4.5.4 Eight-Word Inbound Write with Master Wait States......................692
12.4.5.5 Eight-Word Inbound Write with NOPS.........................................693
12.4.5.6 Eight-Word Inbound Write with EX_SLAVE_CS_N Deassertion .......694
12.4.5.7 Back-to-Back 1-Word Inbound Reads with EX_SLAVE_CS_N..........695
12.4.5.8 Back-to-Back 1-Word Reads without EX_SLAVE_CS_N
Deasserted.............................................................................696
12.4.5.9 Eight-Word Inbound Read ........................................................696
12.4.5.10Eight-Word Inbound Read with Master Wait States ......................697
12.4.5.11Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N ....698
12.4.6 Expansion Bus Arbiter Timing Diagrams...................................................698
12.4.6.1 Arbitration When GrantRemove Bit In EXP_MST_CONTROL
is Set.....................................................................................698
12.4.6.2 Arbitration When GrantRemove Bit in EXP_MST_CONTROL
is Clear..................................................................................699
12.4.7 External Expansion Bus Timing Diagram ..................................................700
12.4.7.1 External Arbiter Timing Diagram................................................700
12.4.8 Configuration Straps .............................................................................700
12.4.8.1 Sampling EX_ADDR During Reset ..............................................701
12.4.8.2 Expansion Bus Controller Operation ...........................................701
12.5 Detailed Register Descriptions ...........................................................................701
12.5.1 Timing and Control Registers for Chip Select 0..........................................703
12.5.2 Timing and Control Registers for Chip Select 1..........................................703
12.5.3 Timing and Control Registers for Chip Select 2..........................................703
12.5.4 Timing and Control Registers for Chip Select 3..........................................704
12.5.5 Timing and Control Registers for Chip Select 4..........................................704
12.5.6 Timing and Control Registers for Chip Select 5..........................................704
12.5.7 Timing and Control Registers for Chip Select 6..........................................705
12.5.8 Timing and Control Registers for Chip Select 7..........................................705
12.5.9 Configuration Register 0 ........................................................................706
12.5.10Configuration Register 1 ........................................................................709
12.5.11EXP_UNIT_FUSE_RESET ........................................................................713
12.5.12EXP_SMIIDLL.......................................................................................716
12.5.13EXP_MST_CONTROL..............................................................................716
12.5.14EXP_INBOUND_ADDR............................................................................717
12.5.15EXP_LOCK0 .........................................................................................719
12.5.16EXP_LOCK1 .........................................................................................720
12.5.17EXP_PARITY_STATUS............................................................................721

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 19
Contents—Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
12.5.18EXP_SYNCINTEL_COUNT....................................................................... 722
13.0 HSS Coprocessor....................................................................................................723
13.1 Overview ....................................................................................................... 723
13.1.1 High-Speed Serial Interface Receive Operation......................................... 724
13.1.2 High-Speed Serial Interface Transmit Operation ....................................... 725
13.2 Feature List.................................................................................................... 725
13.3 Theory of Operation......................................................................................... 726
13.3.1 FIFOs and Lookup Tables....................................................................... 727
13.3.1.1 FIFOs.................................................................................... 727
13.3.1.2 Lookup Tables........................................................................ 727
13.3.2 Endianness.......................................................................................... 730
13.3.3 Programmable Frame Pulse Offset and Frame Synchronization ................... 730
13.3.4 Underflow/Overflow/Unexpected Frame Pulse........................................... 732
13.3.5 56K Mode............................................................................................ 733
13.3.6 Frameless Data Protocol Support............................................................ 733
13.3.7 Loopback ............................................................................................ 733
13.4 HSS Registers and Clock Configuration............................................................... 734
13.4.1 HSS Clock and Jitter ............................................................................. 734
13.4.2 Overview of HSS Clock Configuration ...................................................... 735
13.5 HSS Supported Framing Protocols ..................................................................... 736
13.5.1 T1...................................................................................................... 736
13.5.2 E1...................................................................................................... 738
13.5.3 GCI .................................................................................................... 740
13.5.3.1 Line-Card Mode ...................................................................... 740
13.5.3.2 Termination Mode................................................................... 741
13.5.4 MVIP .................................................................................................. 742
13.5.4.1 2.048-Mbps Backplane ............................................................ 743
13.5.4.2 4.096-Mbps Backplane ............................................................ 744
13.5.4.3 8.192-Mbps Backplane ............................................................ 746
14.0 Universal Asynchronous Receiver-Transmitter (UART) .......................................... 749
14.1 Overview ....................................................................................................... 749
14.2 Feature List.................................................................................................... 750
14.3 Block Diagram ................................................................................................ 751
14.4 Theory of Operation......................................................................................... 752
14.4.1 Setting the Baud Rate........................................................................... 753
14.4.2 Setting Data Bits/Stop Bits/Parity........................................................... 753
14.4.3 Using the Modem Control Signals ........................................................... 756
14.4.4 UART Interrupts................................................................................... 757
14.4.5 Transmitting and Receiving UART Data.................................................... 760
14.5 Register Descriptions....................................................................................... 761
14.5.1 Receive Buffer Register......................................................................... 762
14.5.2 Transmit Holding Register ..................................................................... 763
14.5.3 Divisor Latch Low Register..................................................................... 763
14.5.4 Divisor Latch High Register.................................................................... 764
14.5.5 Interrupt Enable Register ...................................................................... 764
14.5.6 Interrupt Identification Register ............................................................. 765
14.5.7 FIFO Control Register............................................................................ 767
14.5.8 Line Control Register ............................................................................ 768
14.5.9 Modem Control Register........................................................................ 770
14.5.10Line Status Register.............................................................................. 771
14.5.11Modem Status Register ......................................................................... 772
14.5.12Scratch-Pad Register ............................................................................ 773
14.5.13Infrared Selection Register .................................................................... 774

Intel®IXP45X and Intel®IXP46X Product Line of Network Processors—Contents
Intel®IXP45X and Intel®IXP46X Product Line of Network Processors
Developer’s Manual August 2006
20 Order Number: 306262-004US
15.0 GPIO Controller ......................................................................................................776
15.1 Overview........................................................................................................776
15.2 Feature List ....................................................................................................776
15.3 Block Diagram.................................................................................................776
15.4 Theory of Operation.........................................................................................777
15.4.1 Input Meta-Stability Protection, Edge Detect Logic, Pulse Discrimination.......778
15.4.2 Clock Generation ..................................................................................778
15.4.3 APB Interface.......................................................................................779
15.5 Detailed Register Descriptions ...........................................................................779
15.5.1 GPIO Output Register............................................................................779
15.5.2 GPIO Output Enable Register..................................................................780
15.5.3 GPIO Input Register..............................................................................781
15.5.4 GPIO Interrupt Status Register...............................................................781
15.5.5 GPIO Interrupt Type Register 1...............................................................782
15.5.6 GPIO Interrupt Type Register 2...............................................................783
15.5.7 GPIO Clock Register..............................................................................784
16.0 Performance Monitoring Unit (PMU).......................................................................787
16.1 Overview........................................................................................................787
16.2 Feature List ....................................................................................................787
16.3 Functional Description ......................................................................................787
16.3.1 Programmable Event Counters ...............................................................788
16.3.2 Occurrence Events................................................................................788
16.3.3 Duration Events....................................................................................789
16.3.4 Performance Monitoring.........................................................................791
16.3.4.1 Halt: Performance Monitoring Disabled.......................................791
16.3.4.2 Cycle Count............................................................................791
16.3.4.3 MCU: DRAM Transactions .........................................................791
16.3.4.4 Events...................................................................................792
16.4 Previous Master and Slave ................................................................................792
16.5 Miscellaneous..................................................................................................792
16.5.1 Interrupts............................................................................................792
16.5.2 Reset Conditions...................................................................................793
16.6 Detailed Register Descriptions ...........................................................................793
16.6.1 Event Select Registers...........................................................................794
16.6.2 PMU Status Register..............................................................................795
16.6.3 PMU Mode Register ...............................................................................795
16.6.4 Programmable Event Counters ...............................................................796
16.6.5 Previous Master/Slave Register...............................................................797
16.7 Event Mapping ................................................................................................798
17.0 Interrupt Controller................................................................................................803
17.1 Overview........................................................................................................803
17.2 Feature List ....................................................................................................805
17.3 Block Diagram.................................................................................................806
17.4 Theory of Operation.........................................................................................806
17.4.1 Interrupt Priority ..................................................................................807
17.4.2 Assigning FIQ or IRQ Interrupts..............................................................808
17.4.3 Enabling and Disabling Interrupts ...........................................................809
17.4.4 Reading Interrupt Status .......................................................................809
17.5 Error Enable Register .......................................................................................811
17.6 Interrupt Controller Register Descriptions............................................................811
17.6.1 Interrupt Status Register .......................................................................812
17.6.2 Interrupt Enable Register.......................................................................813
17.6.3 Interrupt Select Register........................................................................813
17.6.4 IRQ Status Register ..............................................................................814