Intersil ISL70040SEHEV2Z User manual

Evaluation Board Manual
UG147 Rev.1.01 Page 1
Jan 9, 2023 © 2017-2023 Renesas Electronics
The ISL70040SEHEV2Z evaluation platform is
evaluates the ISL70040SEH alongside the
ISL70023SEH. The same board can be used to
evaluate the ISL73040SEH alongside the
ISL73023SEH, which are the same die offered with
different radiation assurance screening. The
ISL70040SEH is designed to drive enhancement
mode Gallium Nitride (GaN) FETs in isolated
topologies and boost type configurations. It operates
across a supply range of 4.5V to 13.2V and offers
both non-inverting and inverting inputs to satisfy non-
inverting and inverting gate drive within a single
device. The ISL70040SEH has a 4.5V gate drive
voltage (VDRV) that is generated using an internal
regulator which prevents the gate voltage from
exceeding the maximum gate-source rating of
enhancement mode GaN FETs. The gate drive
voltage also features an undervoltage lockout (UVLO)
protection that ignores the inputs (IN/INB) and keeps
OUTL turned on to ensure the GaN FET is in an OFF
state whenever VDRV is below the UVLO threshold.
The ISL70040SEH inputs can withstand voltages up
to 14.7V regardless of the VDD voltage. This allows
the ISL70040SEH inputs to be connected directly to
most PWM controllers. The split outputs of the
ISL70040SEH offer the flexibility to adjust the turn-on
and turn-off speed independently by adding additional
impedance to the turn-on/off paths.
The ISL70023SEH is a 100V N-channel
enhancement mode GaN power transistor. GaN’s
exceptionally high electron mobility and low
temperature coefficient allows for very low rDS(ON),
while its lateral device structure and majority carrier
diode provide exceptionally low QGand zero QRR.
The end result is a device that can operate at a higher
switching frequency with more efficiency while
reducing the overall solution size.
Key Features
▪Wide VDD range single
• 4.5V to 13.2V
▪Location provided for load resistors to switch the
GaN FET with a load
▪SMA connector on the gate drive voltage to
analyze the gate waveforms.
▪Drain/source sense test points to analyze the drain
to source waveforms.
▪Banana jack connectors for power supplies and
drain/source connections.
Specifications
▪VDD range: 4.5V to 13.2V
Related Literature
For a full list of related documents, visit our website:
▪ISL70040SEH, ISL70023SEH, ISL73040SEH,
ISL73023SEH device pages
ISL70040SEHEV2Z

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ISL70040SEHEV2Z Evaluation Board Manual
Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Quick Start Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Gate Drive for N-Channel GaN FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Enable Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7 Driver Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. General PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 ISL70040SEHEV2Z Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 ISL70040SEHEV2Z Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

UG147 Rev.1.01 Page 3
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ISL70040SEHEV2Z Evaluation Board Manual
1. Functional Description
The ISL70040SEH is a single channel high speed enhanced mode GaN FET low side driver for isolated power
supplies and Synchronous Rectifier (SR) applications.
The inputs stage can handle inputs to the 14.7V independent of VDD and offers both inverting and non-inverting
inputs. The split output stage is capable of sourcing and sinking high currents and allows for independent tuning of
the turn-on and turn-off times. A typical propagation delay of 36ns enables high switching frequency operation.
1.1 Operating Range
The ISL70040SEH offers a wide operating supply range of 4.5V to 13.2V. The gate drive voltage is generated
from an internal linear regulator to keep the gate-source voltage below the absolute maximum level of 6V for the
ISL7002xSEH GaN FET devices.
1.2 Quick Start Guide
1. Apply 5.0V to VDD.
2. Drive the IN or INB driver inputs.
a. To drive INB, populate R1with a 0Ωresistor and remove the 0Ωresister on R2.
3. Monitor the gate transition waveforms using SP3.
a. Use a low capacitance SMA cable to reduce the rise and fall times.
b. Use a scope probe with a short ground loop soldered to the outside of the SMA connector.
4. Monitor the VDS voltage using TP10 and TP11 with a short ground loop connection on a scope probe.
5. Switch the FET with a load using R5, R6, and R7.
a. C3:C8 counter any cable inductance leading up the J3 and prevent drain-source voltage spikes that can
damage the GaN FET.
6. Use SP1 and SP2 to sense the current traveling through the FET.
1.3 Gate Drive for N-Channel GaN FETs
New technologies based on wide bandgap semiconductors produce High Electron Mobility Transistors (HEMT).
An example of a HEMT is the GaN based power transistors such as the ISL70023SEH, which offers very low
rDS(ON) and gate charge (Qg). These attributes make the devices capable of supporting very high switching
frequency operation while avoiding significant efficiency loss. However, GaN power FETs have special
requirements in terms of gate drive which the ISL70040SEH is designed to specifically address.
Key properties of a gate driver for GaN FETs are:
1. Gate drive signals need to be sufficiently higher than the VGS threshold specified in GaN FET datasheets for
proper operation.
2. A well regulated gate drive voltage to keep the VGS lower than specified absolute maximum level of 6V.
3. Split pull-up and pull-down gate connections to add series gate resistors to independently adjust turn on and
turn off speed, without the need of a series diode whose voltage drop may cause an insufficient gate drive
voltage.
4. Driver pull down resistance < 0.5Ωto eliminate undesired Miller turn-on.
5. High current source/sink capability and low propagation delay to achieve high switching frequency operation.

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1.4 Undervoltage Lockout
The VDD pin accepts a recommended supply voltage range of 4.5V to 13.2V and is the input to the internal linear
regulator. VDRV is the output of the regulator and is equal to 4.5V. VDRV provides the bias for all internal circuitry
and the gate drive voltage for the output stage.
UVLO circuitry monitors the voltage on VDRV and is designed to prevent unexpected glitches when VDD is being
turned on or turned off. When VDRV < ~1V, an internal 500Ωresistor connected between OUTL and ground helps
keep the gate voltage close to ground. When ~1.2V < VDRV < UV, OUTL is driven low while ignoring the logic
inputs and OUTH is in a high impedance state. This low state has the same current sinking capacity as during
normal operation. This ensures that the driven FETs are held off even if there is a switching voltage on the drains
that can inject charge into the gates from the Miller capacitance.
When VDRV > UVLO, the outputs now respond to the logic inputs. In the non-inverting operation (PWM signal
applied to IN pin) the output is in-phase with the input. In the inverting operation (PWM signal applied to INB pin)
the output is out-phase with the input.
For the negative transition of VDD through the UV lockout voltage, the OUTL is active low and OUTH is high
impedance when VDRV < ~3.7VDC regardless of the input logic states.
1.5 Input Stage
The input threshold of the ISL70040SEH is based on a TTL and CMOS compatible input threshold logic that is
independent of the supply voltage. With typical high threshold = 1.7V and typical low threshold = 1.4V, the logic
level thresholds can be conveniently driven with PWM control signals derived from 3.3V and 5V power controllers.
The ISL70040SEH offers both inverting and non-inverting inputs. The state of the output pin is dependent on the
bias on both input pins. Table 1 summarizes the inputs to output relation.
As a protection mechanism, if any of the input pins are left in a floating condition, OUTL is held in the low state and
OUTH is high impedance. This is achieved using a 300kΩpull-up resistor from INB to VDD and a 300kΩpull-
down resistor from the IN pin to VSS. For proper operation in non-inverting applications, INB should be connected
to VSS. For inverting applications, IN should be connected to VDD for proper operation.
1.6 Enable Function
An enable or disable function can be easily implemented in ISL70040SEH using the unused input pin. The
following tips describe how to implement an enable/disable function:
▪In a non-inverting configuration, the INB pin can be used to implement the enable/disable function. OUT is
enabled when INB is biased low, acting as an active low enable pin.
▪In an inverting configuration, the IN pin can be used to implement the enable and disable function. OUT is
enabled when IN is biased high, acting as an active high enable pin.
Table 1. Truth Table[1]
1. OUT is the combination of OUTH and OUTL connected together. Hi-Z represents a high impedance state.
IN INB OUT OUTH OUTL
000Hi-Z0
010Hi-Z0
1011Hi-Z
110Hi-Z0

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ISL70040SEHEV2Z Evaluation Board Manual
1.7 Driver Power Dissipation
The ISL70040SEH power dissipation is dominated by the losses associated with the gate charge of the driven
bridge FETs and the switching frequency. The internal bias current also contributes to the total dissipation but is
usually not significant compared to the gate charge losses.
For example, the ISL70023SEH has a total gate charge of 14nC when VDS = 50V and VGS = 4.5V. This is the
charge that a driver must source to turn on the GaN FET and must sink to turn off the GaN FET.
Equation 1 calculates the power dissipation of the driver:
where:
freq = switching frequency
VGS = VDRV bias of the ISL70040SEH
Qc= gate charge for VGS
IDD(freq) = bias current at the switching frequency
rDS(ON) = ON-resistance of the driver
Rgate = external gate resistance (if any)
Note: The gate power dissipation is proportionally shared with the external gate resistor. Do not overlook the
power dissipated by the external gate resistor.
2. General PCB Layout Guidelines
The AC performance of the ISL70040SEH depends significantly on the design of the Printed Circuit Board (PCB).
The following layout design guidelines are recommended to achieve optimum performance:
▪Place the driver as close as possible to the driven power FET
▪Understand where the switching power currents flow. The high amplitude di/dt currents of the driven power FET
will induce significant voltage transients on the associated traces
▪Keep power loops as short as possible by paralleling the source and return traces
▪Use planes where practical; they are usually more effective than parallel traces
▪Avoid paralleling high amplitude di/dt traces with low level signal lines. High di/dt will induce currents and
consequently, noise voltages in the low level signal lines
▪When practical, minimize impedances in low level signal circuits. The noise, magnetically induced on a 10kΩ
resistor, is 10 times larger than the noise on a 1kΩresistor
▪Be aware of magnetic fields emanating from transformers and inductors. Gaps in the magnetic cores of these
structures are especially bad for emitting flux
▪If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to
minimize coupling
▪The use of low inductance components such as chip resistors and chip capacitors is highly recommended
▪Use decoupling capacitors to reduce the influence of parasitic inductance in the VDRV, VDD, and GND leads. To
be effective, these capacitors must also have the shortest possible conduction paths. If vias are used, connect
several paralleled vias to reduce the inductance of the vias
▪It may be necessary to add resistance to dampen resonating parasitic circuits, especially on OUTH. If an
external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance
(EQ. 1)
PD2Q
cfreq VGS
Rgate
Rgate rDS ON +
--------------------------------------------- IDD freqVDD
+=

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ISL70040SEHEV2Z Evaluation Board Manual
▪Keep high dv/dt nodes away from low level circuits. Guard banding can be used to shunt away dv/dt injected
currents from sensitive circuits. This is especially true for control circuits that source the input signals to the
ISL70040SEH
▪Avoid having a signal ground plane under a high amplitude dv/dt circuit. This will inject di/dt currents into the
signal ground paths
▪Calculate power dissipation and voltage drop for the power traces. Many PCB/CAD programs have built in tools
for trace resistance calculation
▪Large power components (such as power FETs, electrolytic caps, and power resistors) have internal parasitic
inductance which cannot be eliminated. This must be accounted for in the PCB layout and circuit design
▪If you simulate your circuits, consider including parasitic components, especially parasitic inductance
▪The GaN FETs have a separate substrate connection which is internally tied to the source pin. Source and
substrate should be at the same potential. Limit the inductance in the OUTH/L to Gate trace by keeping it as
short and thick as possible
Figure 1. PCB Layout Recommendation
VDD
IN
INB
VSS
VDRV
OUTH
OUTL
VSSP
DRAIN
SOURCE SUB
ISL7002XSEH
GATE

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ISL70040SEHEV2Z Evaluation Board Manual
2.1 ISL70040SEHEV2Z Evaluation Board
Figure 2. ISL70040SEHEV2Z Evaluation Board, Top View
Figure 3. ISL70040SEHEV2Z Evaluation Board, Bottom View

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ISL70040SEHEV2Z Evaluation Board Manual
2.2 ISL70040SEHEV2Z Schematic Diagram
Figure 4. ISL70040SEHEV2Z Schematic
DRAIN_L
GND
GND
GND
SOURCE
DRAIN
GND/SRC
DRAIN
GND/SRC
DRAIN_L GATE
DRAIN
GND
P
P
P
P
P
P
P
P
P
TP3
SP1
0.22UF
C6
J2
571-0100
0.1UF
C2
C7
0.22UF
571-0500
J1
C9
4.7UF
C3
0.22UF
R1
DNP
SP2
C8
0.22UF
TP8
0
R3
J5
571-0500
0
R2
DNP
R5
TP2
0.22UF
C4
DNP
R6
TP1
0
R4 TP9
TP4
TP11
SP3
571-0100
J4
VDRV OUTL
VSS INB VDD
OUTHIN VSSP
U1
ISL70040SEHVL
1 2 3 4 5
6 7 8
TP10
D
SUB
G
S
Q1
ISL70023SEH
1 2 3
4
0.22UF
C5
TP6
J3
571-0500
4.7UF
C1
TP5
R7
DNP
IN
INB
OUT
OUTH OUTL
UNNAMED_3_BANANAJACK_I41_IN1A
UNNAMED_3_SCOPEPROBE_I34_IN1
VDD
VDRV

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ISL70040SEHEV2Z Evaluation Board Manual
2.3 Bill of Materials
Table 2. Components Parts List
Qty Reference Designator Description Mfr Mfr Part Number
2 SP1, SP2 Scope Probe Test Point PCB Mount Tektronix 131-4353-00
8 TP1-TP6, TP8, TP9 Miniature White Test Point, 100 Pad, 0.040 Thole Keystone 5002
2J2,J4
10A Black Banana Jack Socket
Terminal - Female - Horizontal - 4mm Plug Deltron 571-0100
3 J1, J3, J5 10A Black Banana Jack Socket
Terminal - Female - Horizontal - 4mm Plug Deltron 571-0500
1 SP3 Straight SMA PCB Mount Jack Amphenol 901-144-8RFX
6 C3-C8 Ceramic Chip Capacitor Kemet C1210C224J3GACTU
1 C1 Ceramic Chip Capacitor TDK CGA4J1X7R1E475K125AC
1 C2 Multilayer Cap Generic H1045-00104-25V10
1 C9 Multilayer Cap Generic H1045-00475-10V10-T
1 R1 Metal Film Chip Resistor (Do not populate) Generic H2505-DNP-DNP-R1
3 R2-R4 Thick Film Chip Resistor Generic H2511-00R00-1/10W1
3 R5-R7 Thick Film Chip Resistor (Do not populate) Generic H2515-DNP-DNP-1
1Q1
100V 60A Enhancement Mode GaN Power
Transistor Intersil ISL70023SEH
1U1
Radiation Tolerant Single Low Side GaN FET
Driver Intersil ISL70040SEHVL
2 TP10, TP11 0.086 Pad with 0.046 Plated Through Hole Generic PAD_86C_46P-DNP

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2.4 Board Layout
Figure 5. Top Silkscreen
Figure 6. Bottom Silkscreen

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Figure 7. Top Layer
Figure 8. Bottom Layer

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3. Typical Performance Curves
Figure 9. VDRV Short-Circuit Current vs Temperature Figure 10. Input Propagation Delay
Figure 11. Input Bar Propagation Delay Figure 12. Input Logic Threshold vs Temperature
Figure 13. Input Bar Propagation Delay vs Temperature Figure 14. VDRV Line Regulation vs Temperature
100
110
120
130
140
150
160
170
180
190
200
4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
‐55°C
+125°C
+25°C
VDRV Short-Circuit Current (mA)
VDD (V)
0 100 200 300 400 500
IN PUT
2V/Div
OUTH/L
2V/Div
tDO N
42.8ns
tDOF F
43.8ns
tRISE: 9.4ns
tFALL: 7.6ns
Time (ns)
0 100 200 300 400 500
INPUT
2V/Div
OUTH/L
2V/Div
tDON
44.0ns tDOFF
46.7ns
tRISE: 9.1ns
tFALL: 7.6ns
Time (ns)
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-75 -50 -25 0 25 50 75 100 125 150
V
IH
V
IL
Temperature (°C)
Propagation Delay (ns)
0
10
20
30
40
50
60
-75 -50 -25 0 25 50 75 100 125 150
t
DOFF
t
DON
Temperature (°C)
Propagation Delay (ns)
4.20
4.30
4.40
4.50
4.60
4.70
4.80
4567891011121314
‐55°C
+1 2 5 °C
+2 5 °C
VDRV (V)
VDD (V)

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ISL70040SEHEV2Z Evaluation Board Manual
4. Ordering Information
5. Revision History
Part Number Description
ISL70040SEHEV2Z ISL70040SEHEV2Z evaluation board
Revision Date Description
1.01 Jan 9, 2023
Applied new template.
Updated Page 1 description and related literature.
Updated Gate Drive for N-Channel GaN FETs section.
1.00 Oct 29, 2019
Updated links throughout.
Added x and y-axis labels to Figures.
Added disclaimer.
0.00 Nov 15, 2017 Initial release

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