Intersil ISL97682IRTZEVALZ User manual

1
Application Note 1662
ISL97682 LED Driver Evaluation Board User Manual
Introduction
The ISL97682IRTZEVALZ Evaluation Board provides a
complete testing platform for the ISL97682, a two channel
LED driver. Please refer to the product datasheet (ISL97682,
FN7689) for detailed information including pinout, pin function
description, electrical specifications, applications related
information, etc.
Instructions
Please follow the steps described below to start your
evaluation.
1. For both switch #1 and #2 (SW1 and SW2 shown on the
board), set them to position 3 (left side).
2. For enable control jumper JP1, put the shunt to the “ON”
position (right side) to connect EN pin to VIN. When the
shunt is set to the “OFF” position, it will disable the chip by
pulling the EN pin to ground.
3. Connect JP14 so the VIN pin is connected to PVIN.
4. For JP20, connect the shunt to the upper position.
5. Connect WR and JP2-JP6.
6. Apply 1.5V~5.5V PWM signal between PWMI pin and
AGND.
7. Apply 4V~26.5V between PVIN and PGND and the LEDs
should be lit, and you can start the evaluation.
NOTE: In step #1 above, the SW1, SW2 position can be adjusted to
different positions for different configurations, see Table 1 for details.
• The LED maximum DC current adjustment.
For each channel, the maximum DC current is set by
resistance connected to RSET pin. The current for each
channel can be calculated as shown in Equation 1:
On the board, a potentiometer R5 and a few other resistors
are provided for easily adjust the LED maximum DC current.
Please refer to the “ISL97682IRTZEVALZ Evaluation Board
Schematic” on page 2 for more details.
• LED dimming frequency and duty cycle.
- As mentioned in step #4 above, when the shunt on JP20
is connected to the upper position, FPWM/DPWM pin is
connected to VDC, the device enters direct PWM mode,
which means both the LED dimming frequency and the
duty cycle are synchronized with the external PWM signal
applied on the PWMI pin.
- When the shunt on JP20 is connected to the lower
position, the FPWM/DPWM pin is connected to a resistor.
Under such conditions, the LED dimming frequency of the
chip is programmed by the resistance connected on the
FPWM/DPWM pin as per Equation 2:
The duty cycle is still modulated by the external PWM
signal applied on PWMI pin. On board, potentiometer R11
and a few other resistors are provided for easily adjusting
the LED dimming frequency under such a configuration.
TABLE 1.
SW1
POSITION
SW2
POSITION DESCRIPTION
1 1 LX switching frequency = 600kHz, PFM
CH1 and CH3
3 3 LX switching frequency = 1MHz, PFM
CH1 and CH3
3 1 LX switching frequency = 600kHz, No PFM
CH1 and CH3
1 3 LX switching frequency = 1MHz, No PFM
CH1 and CH3
(EQ. 1)
I_LED mA() 402
RSET kΩ()
----------------------------
=
(EQ. 2)
FPWM Hz() 12.4 107
R_FPWM Ω()
-----------------------------------
•=
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved.
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
October 11, 2011
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Application Note 1662
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ISL97682IRTZEVALZ Evaluation Board Schematic
L1
15µH
D1
PMEG6030
1 3
2
SW1 1 3
2
SW2
R1
150k
R2 100k
When
SW1 = SW2 = 1: Fsw = 1.2MHz, WITH phase shift
SW1 = SW2 = 3: Fsw = 600kHz, WITH phase shift
SW1 = 1, SW2 = 3: Fsw = 1.2MHz, WITHOUT phase shift
SW1 = 3, SW2 = 1: Fsw = 600kHz, WITHOUT phase shift
C1
10µF/50V
C2
0.1µF/50V
P1
PVIN
C4
1µF/16V
P3
EN
P4
PWMI
VDC
C5
4.7µF/ C6 4.7µF/ C7
NC C8
NC
LED1 LED25
LED2 LED26
LED3 LED27
LED4 LED28
LED5 LED29
LED6 LED30
LED7 LED31
LED8 LED32
LED9 LED33
LED10 LED34
LED11 LED35
LED12 LED36
JP2
I_OUT
JP3 JP5
R410k R3
357k
C10
3.3nF/50V
C9
100pF/50V
JP7 JP9
JP11 JP12
C13
1nF/50V
C11
1nF/50V
R5 1M
R6
0
R7
Open
R8
5k
R9
10k C15
8.2nF
C3
33pF
TP1
LX
TP2
VOUT
TP3CH1
TP5CH3
VDC
P5
AGND
P6
AGND
P7
AGND
P8
AGND
P9
PGND
P10
PGND
2-layer board. Connect top layer PGND and bottom
layer AGND
F1
2A Fuse
JP14
R11
100k
R10
0
R13
Open
R12
27k
JP15 JP17
EN can be connected in the following ways to enable/disable
the device:
(1) Connected it to VIN directly on JP1 to enable
(2) Connected it to GND directly on JP1 to disable
(3) Directly apply external voltage on P3(EN) to enable/disable the
device without putting shunt on JP1.
JP2: For measuring total output current
JP3-JP6: For measuring current on CH1-CH4 respectively
JP7-JP10, JP13-JP16: For easy configuration of 8x LED or 10x LED per string
JP19
TP8RSET
TP9
FSW/PHS
P2
VIN
VDC
1 3
2
JP1
13
2
JP20
VDC
NC 16
AGND 1
COMP 2
RSET 3
FSW 4
PWMI
5
EN
6
VIN
7
FPWN/DPWM
8
LX
9
PGND
10
VDC
11
OVP
12
CH1 13
NC 14
CH3 15
ISL97682
U2
U1
XAL6060-153MEB
50V 50V

Application Note 1662
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PCB Layout
FIGURE 1. TOP SILKSCREEN LAYER + TOP LAYER

Application Note 1662
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FIGURE 2. BOTTOM LAYER
PCB Layout (Continued)

Application Note 1662
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Bill of Materials (BOM)
DESIGNATOR PART TYPE FOOTPRINT PART MANUFACTURER/NUMBER
R1 150k 603 1% SMD Resistor
General purpose
R2 100k 603
R3 357k 603
R4 10k 603
R5 1M VRES
R6 open
R7 38.3k 603
R8 5k 603
R9 10k 603
R10 0 603
R11 100k VRES
R12 0 603
R13 Open 603
L1 15µH CoilCraft (XAL6060-153MEB)
D1 PMEG6030
C1 10µF/35V 1210 General purpose
Ceramic X5R/X7R capacitors
C2 0.1µF/50V 603
C3 33pF 603
C4 1µF/16V 603
C5 4.7µF/50V 1210 Murata, GRM32ER71H475KA88L
C6 4.7µF/50V 1210
C7 Place Holder 1210 Not Populated
C8 Place Holder 1210
C9 100pF/50V 603 General purpose
Ceramic X5R/X7R capacitors
C10 3.3nF/50V 603
C11 1nF/50V 603
C12 Place Holder 603
C13 1nF/50V 603
C14 Place Holder 603
C15 8.2nF 603
F1 2A Fuse 1206 Bel Fuse Inc, C1Q 2
U1 QFN16 3MM Intersil, ISL97682/3/4
JP2-JP19 JUMPER-2PIN JUMPER-2PIN FCI
68000-236HLF-1x2
WR JUMPER-2PIN JUMPER-2PIN
JP1 JUMPER-3PIN JUMPER-3PIN FCI
68000-236HLF-1x3
JP20 JUMPER-3PIN JUMPER-3PIN
LED1-12 LED25-36 LED-SMT LW_Y87C 

Application Note 1662
6
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is
cautioned to verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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October 11, 2011
TP1 LX TEST POINT Keystone Electronics
5010
TP2 VOUT TEST POINT
TP3 CH1 TEST POINT
TP4 CH2 TEST POINT
TP5 CH3 TEST POINT
TP6 CH4 TEST POINT
TP7 VDC TEST POINT
TP8 RSET TEST POINT
TP9 FSW/PHS TEST POINT
P5 AGND TEST POINT Keystone Electronics
5011
P6 AGND TEST POINT
P9 PGND TEST POINT
P1 PVIN POWERPOST Mill Max
3156-1-00-00-00-00-08-0
P2 VIN POWERPOST
P3 EN POWERPOST
P4 PWMI POWERPOST
P7 AGND POWERPOST
P8 AGND POWERPOST
P10 PGND POWERPOST
SW2 SPDT SWITCH-SLIDE-SPDT EAO
09.03201.02
SW1 SPDT SWITCH-SLIDE-SPDT
Bill of Materials (BOM) (Continued)
DESIGNATOR PART TYPE FOOTPRINT PART MANUFACTURER/NUMBER