Intersil ISL8105BEVAL1Z User manual

1
®
AN1288.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Using the ISL8105BEVAL1Z, ISL8105BEVAL2Z
PWM Controller Evaluation Board
Introduction
The ISL8105B is a simple single-phase PWM controller for a
synchronous buck converter that operates from +5V or +12V
bias supply voltage. With integrated linear regulator, boot diode,
and gate drivers, the ISL8105B reduces external component
count and board space requirements.
The ISL8105BEVAL1Z, ISL8105BEVAL2Z evaluation board
highlights the operations of the controller in a DC/DC
application.
ISL8105BEVAL1Z , ISL8105BEVAL2Z
Reference Design
The ISL8105BEVAL1Z, ISL8105BEVAL2Z evaluation board
is designed to optimize for the output voltage and current
specifications shown in Table 1.
Two versions of the evaluation board, based on the package
type, are listed in Table 2.
Design Procedure
The following sections illustrate simple design steps and
component selections for a converter using the
ISL8105BEVAL1Z, ISL8105BEVAL2Z.
Output Inductor Selection
The output inductor is chosen by the desired inductor ripple
current, which is typically set to be approximately 40% of the
rated output current. The desired output inductor can be
calculated using Equation 1:
In the evaluation board, a 1µH inductor with 1.87mΩDCR
(Cooper Bussmmann’s HC9-1R0-R) is employed. This yields
approximately 0.44W conduction loss in the inductor.
Output Capacitor Selection
The output capacitors are generally selected by the output
voltage ripple and load transient response requirements.
ESR and capacitor charge are major contributions to the
output voltage ripple. Assuming that the total output
capacitance is sufficient, then the output voltage ripple is
dominated by the ESR, which can be calculated using
Equation 2.
To meet the 30mVP-P output voltage ripple requirement, the
effective ESR should be less than 5mΩ.
The output voltage response to a transient load is
contributed from ESL, ESR and the amount of output
capacitance. With VIN>>VOUT, the amplitude of the voltage
excursions can be approximated using Equation 3:
With 1µH inductor and 0A to 15A step load, the total output
capacitance of 1560µF is required for 80mV output voltage
transient. In the ISL8105BEVAL1Z, ISL8105BEVAL2Z
evaluation board, four of Sanyo’s 2R5TPF470ML are
employed.
Input Capacitor Selection
The input bulk capacitors selection criteria are based on the
capacitance and RMS current capability. The RMS current
rating requirement for the input capacitor is approximated in
Equation 4:
In this application, the RMS current for the input capacitors is
5.4A; therefore, three of Sanyo’s 35ME330AX are used.
Small ceramic capacitors for high frequency decoupling are
also required to control the voltage overshoot across the
MOSFETs.
MOSFET Selection
The ISL8105B requires two N-Channel power MOSFETs as
the main and the synchronous switches. These should be
selected based in rDS(ON), gate supply requirements and
thermal management requirements.
TABLE 1. ISL8105BEVAL1Z, ISL8105BEVAL2Z EVALUATION
BOARD DESIGN PARAMETERS
PARAMETER MIN TYP MAX
Input Voltage (VIN) 9.6V 12V 14.4V
Output Voltage (VOUT)1.8V
Output Voltage Ripple (VRIPPLE) 30mVP-P
Continuous Load Current 15A
Efficiency 90
TABLE 2. EVALUATION BOARDS
BOARD NAME IC PACKAGE
ISL8105BEVAL1Z ISL8105BIBZ 8 Ld SOIC
ISL8105BEVAL2Z ISL8105BIRZ 10 Ld DFN
LVIN VOUT
–
ΔI
--------------------------------VOUT
VIN
----------------
×1
FSW
------------
×=
14.4 1.8–
0.4 15⋅
--------------------------1.8
14.4
-----------
×1
300 3
×10
----------------------
×=
0.875μH=
(EQ. 1)
VRIPPLE ΔILESR⋅=(EQ. 2)
ΔVLI
tran
2
⋅
COUT VOUT
⋅
-------------------------------------
=(EQ. 3)
IIN RMS,IO2DD
2
–()
IΔ2
12
-------- D+= DVO
VIN
----------
=(EQ. 4)
Application Note October 30, 2008

2AN1288.1
October 30, 2008
The total power loss in MOSFET consists of conduction loss
and switching loss, as shown in Equation 5:
In this relatively small duty cycle design, the low-side
MOSFET conducts current most of the time. To optimize the
converter efficiency, select the high-side MOSFET with low
gate charge for fast switching transition and low-side
MOSFET with low rDS(ON).
To achieve the target efficiency, the budget power losses in
high-side and low-side MOSFETs are 0.5W and 1W,
respectively.
LOW-SIDE MOSFET SELECTION
The low-side MOSFET’s RMS current is approximated in
Equation 6:
Therefore, the ON-resistance of the low-side MOSFET must
be less than 5mΩ. Infineon’s BSC030N03LS is employed in
the ISL8105BEVAL1Z, ISL8105BEVAL2Z evaluation board.
The conduction loss in the low-side MOSFET is calculated
using Equation 7:
The switching loss in the low-side MOSFET is dominated by
the loss in body diode which can be calculated using
Equation 8:
Where tDis the total dead time in each switching period
(~60µs) and VFis the forward voltage drop of MOSFET’s
body diode.
The total power dissipation in the low-side MOSFET is
calculated using Equation 9:
HIGH-SIDE MOSFET SELECTION
For the high-side MOSFET selection, first we assume that
the conduction loss and the switching loss contribute evenly
to the total power dissipation.
The high-side MOSFET’s RMS current is approximated
using Equation 10:
Hence, the required ON-resistance of the high-side MOSFET is
7.3mΩ. Infineon’s BSC080N03LS is selected. The conduction
loss in the high-side MOSFET is calculated using Equation 11:
The switching loss in the high-side MOSFET can be
approximated using Equation 12:
where ttr is the combined ON and OFF MOSFET transition
times.
The total power dissipation in high-side MOSFET is shown in
Equation 13:
Overcurrent Protection Setting
The overcurrent function protects the converter from a shorted
output by using the low-side MOSFET’s rDS(ON) to monitor
the current. A resistor, RBSOC, programs the overcurrent trip
level. If overcurrent is detected, the output immediately shuts
off, it cycles the soft-start function in a hiccup mode (2 dummy
soft-start time-outs, then up to one real one) to provide fault
protection. If the shorted condition is not removed, this cycle
will continue indefinitely.
The overcurrent function will trip at a inductor current (Itrip) is
determined using Equation 14:
where IOCSET is the internal 21.5µA (typ.) OCSET current
source.
The OC trip point varies mainly due to the MOSFET’s rDS(ON)
variations. To avoid overcurrent tripping in the normal operating
load range, calculate the RBSOC resistor from Equation 14
using:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table of the
datasheet.
Determine Itrip for Itrip > IOUT(MAX) + (ΔI)/2, where ΔI is the
output inductor ripple current.
PMOSFET TOT() Pcond Psw += (EQ. 5)
ILRMS()
IOUT 1D–11
12
------ ΔIL
IOUT
-------------
⎝⎠
⎜⎟
⎛⎞
2
⋅+⋅⋅ 13.9A≈=(EQ. 6)
PLFET cond()
ILRMS()
2rDS ON()
LFET
⋅0.58W==
(EQ. 7)
Pdiode IOtDVFFSW
⋅⋅ ⋅ 0.3W== (EQ. 8)
PLFET TOT()
0.88W=(EQ. 9)
IH rms()
IOUT D11
12
------ ΔIL
IOUT
-------------
⎝⎠
⎜⎟
⎛⎞
2
⋅+⋅⋅ 5.85A≈=(EQ. 10)
PHFET cond()
IHRMS()
2rDS ON()
HFET
⋅0.27W==
(EQ. 11)
PHFET SW()1
2
---IOVIN ttr FSW
⋅⋅ ⋅⋅ 1
2
---COSS VIN
2FSW
⋅⋅⋅+=
0.17W=(EQ. 12)
PHFET TOT()
0.44W=(EQ. 13)
Itrip 2I•OCSET RBSOC
•
rDS ON()
---------------------------------------------------------
=(EQ. 14)
Application Note 1288

3AN1288.1
October 30, 2008
With Infineon’s BSC030N03LS as the low-side MOSFET and
RBSOC of 1.74kΩ. The overcurrent trip point on the evaluation
board has been set to 21A for 12VBIAS (17A for 5VBIAS).
Feedback Compensator
Type-III network is recommended for compensating the
feedback loop. Figure 1 shows Type-III compensation
configuration for ISL8105B.
With the inductor and output capacitor selected as described
in the previous sections, the poles and zero of the power
stage can be summarized in Equation 15:
1. With a value of 11.8kΩfor R1, select R4for the target
output voltage of 1.8V using Equation 16:
2. With the desired feedback loop bandwidth of 30kHz, R2
can be calculated using Equation 17:
3. Select C1such that FZ1 is located at 1.5kHz (~50% of
FLC):
4. Select C2such that FP1 is located at FESR:
5. Select R3such that FZ2 is located at FLC:
A more detailed explanation of designing compensation
networks for buck converters with voltage mode control can
be found in TB417 entitled “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck Regulators”.
Evaluation Board Performance
Figure 2 shows a photograph of the ISL8105BEVAL1Z.
Power and Load Connections
Terminals J1 and J2 are connected to the input of the power
stage. The IC bias supply and the converter input supply can
be together through pin 2 and 3 of the Jumper J7 to provide
single rail supply application. When using separate supplies,
provide the IC bias voltage to terminal J2 with pin 2 and pin 1
of J7 connected together. The load can be connected to
terminal J4 and J5. TP6 and TP3 can be used for DMM to
measure output voltage. The scope probe terminal (TPV01)
can be used to monitor VOUT with an oscilloscope. The push
switch, SW1, can be used to disable the controller.
FIGURE 1. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP C1
R2
R1
FB
C2R3C3
L
C
VIN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
ESR
EXTERNAL CIRCUITISL8105B
VOUT
VOSC
DCR
TGATE
LX
BGATE
R4
F01
2π× LC××
-------------------------------------3.7kHz==
FESR 1
2π× C ESR××
-------------------------------------------33.9kHz== (EQ. 15)
R4R1Vref
VOUT Vref –
---------------------------------
×=
5.9kΩ=
(EQ. 16)
R2VOSC R1F0
⋅⋅
dmax VIN FLC
⋅⋅
--------------------------------------------
=
12kΩ=
(EQ. 17)
C11
2πR21.5 3
×10⋅⋅
--------------------------------------------
=
10nF≈
(EQ. 18)
C2C1
2πR2C1FESR ⋅⋅⋅ 1–
------------------------------------------------------------
=
390pF≈
(EQ. 19)
R3R1
150 3 ×10
FLC
---------------------- 1–
--------------------------------301Ω≈=
C31
2πR3150 3
×10⋅⋅
----------------------------------------------3.3nF≈=
(EQ. 20)
FIGURE 2. ISL8105BEVAL1Z
Application Note 1288

4AN1288.1
October 30, 2008
Start-up
The ISL8105B starts up when VBIAS rises above POR
threshold and the COMP/EN rises above VDISABLE level. The
entire start-up time sequence from POR typically takes up to
23.8ms; up to 10.2ms for the delay and the Overcurrent
Protection (OCP) sample and hold operation. The initial delay
is added to allow the bias voltage to rise/exceed 6.5V, so that
the internal bias regulator can turn on cleanly. When the OCP
sampling and hold operations are done, the soft-start function
internally ramps the reference on the non-inverting terminal of
the error amp from 0V to 0.6V in 13.6ms (typ).
Figure 3 shows the start-up profile of the ISL8105BEVAL1Z,
ISL8105BEVAL2Z in relation to the start-up of the 12V input
supply and the bias supply.
Soft-Start with Pre-Biased Output
If the output is pre-biased to a voltage less than the expected
value, the ISL8105BEVAL1Z, ISL8105BEVAL2Z will detect
that condition. Neither MOSFETs will turn on until the
soft-start ramp voltage exceeds the FB voltage; VOUT starts
seamlessly ramping from there.
Output Ripple
Figure 5 shows the ripple voltage on the output of the
regulator.
Verifying Loop Gain
Figure 6 shows the measurement of loop gain of the
converter with feedback network design in the previous
sections.
FIGURE 3. SOFT-START
V
IN
= 12V, V
OUT
= 1.8V, I
OUT
= 15A
COMP
VOUT
IL
LX
FIGURE 4. SOFT-START WITH PRE-BIASED OUTPUT
V
IN
= 12V, V
OUT
= 1.8V, I
OUT
= 1A
Vout
COMP
Lx
FIGURE 5. OUTPUT RIPPLE (20MHz BW)
FIGURE 6. LOOP GAIN MEASUREMENT AT +25°C
Application Note 1288

5AN1288.1
October 30, 2008
Transient Performance
Figures 7, 8, and 9 show the response of the output when
subjected to transient loading from 0A to 15A at 1A/µs.
Efficiency
ISL8105BEVAL1Z, ISL8105BEVAL2Z based regulators
enable the design of highly efficient systems. The efficiency
of the evaluation board using a 12V input supply is shown in
Figure 10.
References
For Intersil documents available on the web, go to
http://www.intersil.com/.
1. ISL8105, ISL8105B Data Sheet, FN6306, “+5V or +12V
Single-Phase Synchronous Buck Converter PWM
ControllerwithIntegratedMOSFETGateDrivers”,Intersil
Corporation
2. Tech Brief TB417, “Designing Stable Compensation
Networks for Single Phase Voltage Mode Buck
Regulators”, Intersil Corporation
FIGURE 7. TRANSIENT RESPONSE
IL
VOUT
FIGURE 8. TRANSIENT RESPONSE
FIGURE 9. TRANSIENT RESPONSE
FIGURE 10. EVALUATION BOARD EFFICIENCY (VOUT = 1.8V)
50
55
60
65
70
75
80
85
90
95
10 11 12 13 14 15
LOAD CURRENT (A)
EFFICIENCY (%)
0123456789
FIGURE 11. EVALUATION BOARD LINE REGUALTION
1.790
1.792
1.794
1.796
1.798
1.800
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
10 11 12 13 14 150123456789
Application Note 1288

6AN1288.1
October 30, 2008
ISL8105BEVAL1Z Schematic
BOOT
BGATE
VBIAS
FB
COMP/EN
VIN
TGATE
LX VOUT
TitleSize Rev
Date: Sheet of
A
ISL8105BEVAL1Z
11Thursday, January 31, 2008
1001 Murphy Ranch Rd.
Milpitas, CA, 95035
Intersil Corporation
TitleSize Rev
Date: Sheet of
A
ISL8105BEVAL1Z
11Thursday, January 31, 2008
1001 Murphy Ranch Rd.
Milpitas, CA, 95035
Intersil Corporation
TitleSize Rev
Date: Sheet of
A
ISL8105BEVAL1Z
11Thursday, January 31, 2008
1001 Murphy Ranch Rd.
Milpitas, CA, 95035
Intersil Corporation
TP3TP3
C24
DNP
C24
DNP
TP7TP7
TP10TP10
J7J7
1
2
3
R8
DNP
R8
DNP
+
C13
330uF
+
C13
330uF
J1
VIN
J1
VIN
+
C21
470uF
+
C21
470uF
TP6TP6
R7
DNP
R7
DNP
+
C19
470uF
+
C19
470uF
J6
GND
J6
GND
+
C17
DNP
+
C17
DNP
+
C11
330uF
+
C11
330uF
C8
680pF
C8
680pF
J2
VBIAS
J2
VBIAS
Q6
DNP
Q6
DNP
+
C18
470uF
+
C18
470uF
U1
ISL8105B
U1
ISL8105B
TGATE 2
BGATE/BSOC 4
VBIAS
5
FB
6
COMP/EN
7
GND
3
BOOT 1
LX 8
C7
DNP
C7
DNP
TP8TP8
R1
11.8k
R1
11.8k
C28
0.1uF
C28
0.1uF
Q5
DNP
Q5
DNP
+
C20
470uF
+
C20
470uF
C25
DNP
C25
DNP
L1
1uH
L1
1uH
2 1
J5
GND
J5
GND
R3
301
R3
301
C23
DNP
C23
DNP
C3
3.3nF
C3
3.3nF
J3
GND
J3
GND
Q4
DNP
Q4
DNP
R5
1.74k
R5
1.74k
+
C14
DNP
+
C14
DNP
Q2
DNP
Q2
DNP
4
1 2 35
C4
1.0uF
C4
1.0uF
+
C16
DNP
+
C16
DNP
C10
1uF
C10
1uF
C6
DNP
C6
DNP
C26
DNP
C26
DNP
C5
0.1uF
C5
0.1uF
Q3Q3
4
1 2 35
R4
5.9k
R4
5.9k
R2
12k
R2
12k
C27
0.1uF
C27
0.1uF
Probe Socket
TPVO1
Probe Socket
TPVO1
1
4
3
2
C9
1uF
C9
1uF
TP4TP4
R6
4.7
R6
4.7
C1
10nF
C1
10nF
SW1SW1
1
2
4
3
+
C15
DNP
+
C15
DNP
TP9TP9
Q1Q1
4
1 2 35
+
C12
330uF
+
C12
330uF
C2
390pF
C2
390pF
J4
VOUT
J4
VOUT
TP2TP2 C22
DNP
C22
DNP
Application Note 1288

7AN1288.1
October 30, 2008
ISL8105BEVAL1Z Bill of Materials
ID REFERENCE QTY PART NUMBER PART TYPE DESCRIPTION PACKAGE VENDOR
1 U1 1 ISL8105BIBZ IC, Linear IC, Single PWM Controller 8 LD SOIC Intersil
2 Q1 1 BSC080N30LS G MOSFET 30V N-Channel MOSFET TDSON-08 Infineon
3 Q3 1 BSC030N03LS G MOSFET 30V N-Channel MOSFET TDSON-08 Infineon
4 Q2, Q4, Q5, Q6 DNP MOSFET
5 L1 1 HC9-1R0-R Inductor 1.0µH, high current inductor SMD Cooper Bussmann
6 SW1 1 EVQ-PAD04M Push Switch SWITCH-PUSH, TH, 6mm,
1P, PUSHB MOM-SPST PANASONIC
CAPACITORS
7 C1 1 Capacitor, Ceramic,
X7R 10nF, 50V, 10%, ROHS SM_0603 TDK/Generic
8 C2 1 Capacitor, Ceramic,
X7R 390pF, 50V, 10%, ROHS SM_0603 TDK/Generic
9 C3 1 Capacitor, Ceramic,
X7R 3.3nF, 50V, 10%, ROHS SM_0603 TDK/Generic
10 C4, C9, C10 3 Capacitor, Ceramic,
X7R 1µF, 25V, 10%, X7R, ROHS SM_0805 TDK/Generic
11 C5, C27, C28 3 Capacitor, Ceramic,
X7R 0.1µF, 16V, 10%, ROHS SM_0603 TDK/Generic
12 C8 1 Capacitor, Ceramic,
X7R 680pF, 50V, 10%, ROHS SM_0603 TDK/Generic
13 C11, C12, C13 3 35ME330AX Aluminum Capacitor 330µF, 35V RAD 10x20 Sanyo
14 C18, C19, C20, C21 4 2R5TPF470ML Organic Alumium
Capacitor 470µF, 2.5V, 20%, ROHS Case D3L Sanyo
15 C6, C7, C14, C15, C16,C17,
C22, C23, C24, C25, C26 DNP
RESISTORS
16 R1 1 Resistor, Film 11.8kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
17 R2 1 Resistor, Film 12kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
18 R3 1 Resistor, Film 301Ω, 1%, 1/16W SM_0603 Panasonic/Generic
19 R4 1 Resistor, Film 5.9kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
20 R5 1 Resistor, Film 1.74kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
21 R6 1 Resistor, Film 4.7Ω, 1%, 1/16W SM_0603 Panasonic/Generic
22 R7, R8 DNP SM_0603
OTHERS
23 TPVO1 DNP Terminal, Scope
Probe CONN-PIN RECEPTACLE, 0.086 DIA, 0.200 L, ROHS MILL-MAX
24 J1, J4 2 111-0702-001 Blinding Post CONN-GEN, BIND. POST,
RED, THMBNUT-GND JOHNSON COMPONENTS
25 J3, J5 2 111-0703-001 Blinding Post CONN-GEN, BIND. POST,
BLACK, THMBNUT-GND JOHNSON COMPONENTS
26 J2, J6 2 1514-2 Turrett Post CONN-TURRET, TERMINAL
POST, TH, ROHS Keystone
27 J7 1 68000-236-1X3 3-pin Jumper Berg/FCI
28 TP3, TP6, TP9, TP10 4 5002 Test Point CONN-MINI TEST POINT,
VERTICAL, WHITE, ROHS Keystone
29 TP2, TP4, TP7, TP8 DNP 5002 Test Point CONN-MINI TEST POINT,
VERTICAL, WHITE, ROHS Keystone
Application Note 1288

8AN1288.1
October 30, 2008
ISL8105BEVAL1Z Printed Circuit Board Layers
FIGURE 12. ISL8105BEVAL1Z - TOP LAYER (SILKSCREEN) FIGURE 13. ISL8105BEVAL1Z - TOP LAYER
(COMPONENT SIDE)
FIGURE 14. ISL8105BEVAL1Z - LAYER 2 FIGURE 15. ISL8105BEVAL1Z - LAYER 3
FIGURE 16. ISL8105BEVAL1Z - BOTTOM LAYER FIGURE 17. ISL8105BEVAL1Z - BOTTOM LAYER
(SOLDER SIDE)
Application Note 1288

9AN1288.1
October 30, 2008
Application Note 1288
ISL8105BEVAL2Z Schematic
LX
VBIAS
FB
COMP/EN
VIN
TGATE
VOUT
BGATE
BOOT
TitleSize Rev
Date: Sheet of
A
ISL8105BEVAL2Z
11Friday, July 11, 2008
1001 Murphy Ranch Rd.
Milpitas, CA, 95035
Intersil Corporation
TitleSize Rev
Date: Sheet of
A
ISL8105BEVAL2Z
11Friday, July 11, 2008
1001 Murphy Ranch Rd.
Milpitas, CA, 95035
Intersil Corporation
TitleSize Rev
Date: Sheet of
A
ISL8105BEVAL2Z
11Friday, July 11, 2008
1001 Murphy Ranch Rd.
Milpitas, CA, 95035
Intersil Corporation
C7
DNP
C7
DNP
C22
DNP
C22
DNP
C10
1uF
C10
1uF
TP2TP2
J4
VOUT
J4
VOUT
R2
12k
R2
12k R4 5.9k
R4
5.9k
J6
GND
J6
GND
R1
11.8k
R1
11.8k
+
C13
330uF
+
C13
330uF
+
C14
DNP
+
C14
DNP
+
C19
470uF
+
C19
470uF
R5
1.74k
R5
1.74k
Q1Q1
4
1 2 35
R8
DNP
R8
DNP
TP9TP9
TP8TP8
Q6
DNP
Q6
DNP
TP10TP10
Q3Q3
4
1 2 35
+
C20
470uF
+
C20
470uF
SW1SW1
1
2
4
3
Q4
DNP
Q4
DNP
L1
1uH
L1
1uH
2 1
C1
10nF
C1
10nF
R7
DNP
R7
DNP
C23
DNP
C23
DNP
+
C16
DNP
+
C16
DNP
U1
ISL8105B DFN
U1
ISL8105B DFN
TGATE 2
BGATE/BSOC 5
VBIAS
6
FB
8
COMP/EN
9
GND
4
BOOT 1
LX 10
NC1 3 NC2
7
EP
11
R3
301
R3
301
J2
VBIAS
J2
VBIAS TP7TP7
C4
1.0uF
C4
1.0uF
Q2
DNP
Q2
DNP
4
1 2 35
J3
GND
J3
GND
Probe Socket
TPVO1
Probe Socket
TPVO1
1
4
3
2
C8
680pF
C8
680pF
C5
0.1uF
C5
0.1uF
+
C18
470uF
+
C18
470uF
C26
DNP
C26
DNP
R6
4.7
R6
4.7
+
C21
470uF
+
C21
470uF C24
DNP
C24
DNP
Q5
DNP
Q5
DNP
J1
VIN
J1
VIN
C2
390pF
C2
390pF
J5
GND
J5
GND
+
C12
330uF
+
C12
330uF
TP4TP4
+
C15
DNP
+
C15
DNP
J7J7
1
2
3
C28
0.1uF
C28
0.1uF
+
C11
330uF
+
C11
330uF
+
C17
DNP
+
C17
DNP
C9
1uF
C9
1uF
C6
DNP
C6
DNP
TP3TP3
C3
3.3nF
C3
3.3nF
C25
DNP
C25
DNP
TP6TP6
C27
0.1uF
C27
0.1uF

10 AN1288.1
October 30, 2008
Application Note 1288
ISL8105BEVAL2Z Bill of Materials
ID REFERENCE QTY PART NUMBER PART TYPE DESCRIPTION PACKAGE VENDOR
1 U1 1 ISL8105BIRZ IC, Linear IC, Single PWM Controller 10 LD DFN Intersil
2 Q1 1 BSC080N30LS G MOSFET 30V N-Channel MOSFET TDSON-08 Infineon
3 Q3 1 BSC030N03LS G MOSFET 30V N-Channel MOSFET TDSON-08 Infineon
4 Q2, Q4, Q5, Q6 DNP MOSFET
5 L1 1 HC9-1R0-R Inductor 1.0µH, high current inductor SMD Cooper Bussmann
6 SW1 1 EVQ-PAD04M Push Switch SWITCH-PUSH, TH, 6mm,
1P, PUSHB MOM-SPST PANASONIC
CAPACITORS
7 C1 1 Capacitor, Ceramic,
X7R 10nF, 50V, 10%, ROHS SM_0603 TDK/Generic
8 C2 1 Capacitor, Ceramic,
X7R 390pF, 50V, 10%, ROHS SM_0603 TDK/Generic
9 C3 1 Capacitor, Ceramic,
X7R 3.3nF, 50V, 10%, ROHS SM_0603 TDK/Generic
10 C4, C9, C10 3 Capacitor, Ceramic,
X7R 1µF, 25V, 10%, X7R, ROHS SM_0805 TDK/Generic
11 C5, C27, C28 3 Capacitor, Ceramic,
X7R 0.1µF, 16V, 10%, ROHS SM_0603 TDK/Generic
12 C8 1 Capacitor, Ceramic,
X7R 680pF, 50V, 10%, ROHS SM_0603 TDK/Generic
13 C11, C12, C13 3 35ME330AX Aluminum Capacitor 330µF, 35V RAD 10x20 Sanyo
14 C18, C19, C20, C21 4 2R5TPF470ML Organic Alumium
Capacitor 470µF, 2.5V, 20%, ROHS Case D3L Sanyo
15 C6, C7, C14, C15, C16, C17,
C22, C23, C24, C25, C26 DNP
RESISTORS
16 R1 1 Resistor, Film 11.8kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
17 R2 1 Resistor, Film 12kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
18 R3 1 Resistor, Film 301Ω, 1%, 1/16W SM_0603 Panasonic/Generic
19 R4 1 Resistor, Film 5.9kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
20 R5 1 Resistor, Film 1.74kΩ, 1%, 1/16W SM_0603 Panasonic/Generic
21 R6 1 Resistor, Film 4.7Ω, 1%, 1/16W SM_0603 Panasonic/Generic
22 R7, R8 DNP SM_0603
OTHERS
23 TPVO1 DNP Terminal, Scope
Probe CONN-PIN RECEPTACLE, 0.086 DIA, 0.200 L, ROHS MILL-MAX
24 J1, J4 2 111-0702-001 Blinding Post CONN-GEN, BIND. POST,
RED, THMBNUT-GND JOHNSON COMPONENTS
25 J3, J5 2 111-0703-001 Blinding Post CONN-GEN, BIND. POST,
BLACK, THMBNUT-GND JOHNSON COMPONENTS
26 J2, J6 2 1514-2 Turrett Post CONN-TURRET, TERMINAL
POST, TH, ROHS Keystone
27 J7 1 68000-236-1X3 3-pin Jumper Berg/FCI
28 TP3, TP6, TP9, TP10 4 5002 Test Point CONN-MINI TEST POINT,
VERTICAL, WHITE, ROHS Keystone
29 TP2, TP4, TP7, TP8 DNP 5002 Test Point CONN-MINI TEST POINT,
VERTICAL, WHITE, ROHS Keystone

11
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
AN1288.1
October 30, 2008
Application Note 1288
ISL8105BEVAL2Z Printed Circuit Board Layers
FIGURE 18. ISL8105BEVAL2Z - TOP LAYER (SILKSCREEN) FIGURE 19. ISL8105BEVAL2Z - TOP LAYER
(COMPONENT SIDE)
FIGURE 20. ISL8105BEVAL2Z - LAYER 2 FIGURE 21. ISL8105BEVAL2Z - LAYER 3
FIGURE 22. ISL8105BEVAL2Z - BOTTOM LAYER FIGURE 23. ISL8105BEVAL2Z - BOTTOM LAYER
(SOLDER SIDE)

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