Intersil ISL98001 Owner's manual

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 1/16 Ver. 1.1, 12/19/05
Installation and Operation of Intersil’s ISL98001
Analog Front End Evaluation System

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 2/16 Ver. 1.1, 12/19/05
Note
To simplify installation and prevent unnecessary Windows messages during installation, do
not connect the USB cable to the ISL98001 Evaluation Board until the software installation is
complete.
PC Requirements
Operating System: Tested under Windows XP (service pack 2) and Windows 2000. Windows 98 and
ME not currently supported.
Hardware Requirements: USB Port, CD-ROM drive for install files, minimum 10MB free hard disk
space.
Software Installation
Launch the “ISL98001 Installer.exe” file on the CD ROM and follow the instructions. The default
installation will add an “Intersil” directory to the “Start Menu/Programs” tree. That directory will contain
a shortcut to the ISL98001 executable and an uninstaller. The main program files will be installed in
the Program Files/ISL98001 directory. The USB driver file windrvr6.sys will be placed into
C:\WINDOWS\system32\drivers and ISL98001.inf will be installed under C:\WINDOWS\INF.
Press “Next” to continue.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 3/16 Ver. 1.1, 12/19/05
By default, the installer will put the evaluation software under c:\Program Files\ISL98001 directory.
To us a different directory, select the “Browse” button.
Press “Next” to continue.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 4/16 Ver. 1.1, 12/19/05
Press “Next” to create the Intersil folder in the Start Menu.
Press the “Install” button to copy all the necessary files onto the PC.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 5/16 Ver. 1.1, 12/19/05
Connecting the Evaluation Board
After installation of the ISL98001 software, re-boot the PC if requested. Apply power to the ISL98001
Evaluation Board with the provided 5V power supply. Connect the USB cable to the ISL98001
Evaluation Board. The Microsoft windows operating system will see the ISL98001 Evaluation Board
as a new device, and will try to load appropriate driver for it.
Windows XP may pop up this message:
If you see this box, select “Yes, now and every time I connect a device” and click on “Next”. If you
elect not to select “Yes, now and every time I connect a device”, you may see this requester
whenever the device is reconnected after being disconnected.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 6/16 Ver. 1.1, 12/19/05
The following screen will then appear:
Press Next (“Install the software automatically”).
The Hardware Wizard will try to locate and install the driver for the ISL98001:

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 7/16 Ver. 1.1, 12/19/05
Click Finish to complete the installation.
On XP systems, a pop-up message may display the status of the ISL98001 hardware.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 8/16 Ver. 1.1, 12/19/05
Hardware Setup
By default, the ISL98001 Evaluation board is configured for an input video resolution of
1280x1024@60Hz on the VGA1 connector. The quickest way to verify operation is this:
•Connect a monitor with a DVI input to the DVI output connector
•Connect a 1280x1024@60Hz RGB video source to VGA1
•Connect the 5V power supply to the power connector
At this point, the evaluation board’s FPGA will format the data from the ISL98001 and generate SXGA
video timing on the DVI output connector. The incoming SXGA image should appear on the DVI
monitor.
Additional video modes and AFE configuration options are available using the ISL98001 evaluation
software through the USB interface.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 9/16 Ver. 1.1, 12/19/05
Starting the Software
Launch the software (default location is Start/Programs/Intersil/ISL98001).
After the program has launched, you should see the following screen:
Click on the “Read All Registers” button in the lower left screen. All of the register values from the
ISL98001 on the evaluation board should appear as shown in the next image. If the register values
are not read correctly, proceed to the Troubleshooting section of this document.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 10/16 Ver. 1.1, 12/19/05
To change a register value, simply change the hexadecimal number in the appropriate box. To
change both digits of the 8 bit hex number, select both digits with the mouse (or double click inside
the text box) , then quickly type both digits of the desired value. If you type too
slowly (more than 1 second between the first and second digit), the first digit typed will become the
lower nibble, and the higher nibble will be 0. To only change one nibble using the keyboard, select
the high nibble or the low nibble and type the new hexadecimal
value.
You can also change the register values using the keyboard:
•Increment by 1: Up Arrow
•Decrement by 1: Down Arrow
•Increment by 16 (increment high nibble by 1): Page Up
•Decrement by 16 (decrement high nibble by 1): Page Up

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 11/16 Ver. 1.1, 12/19/05
This version of the software adds “GangGain” and ‘GangOffset” checkboxes. When one or both of
these boxes are checked, changing the gain (or offset) of one color will simultaneously change the
gain (or offset) of the other 2 colors.
There is also a “YPbPr to RGB CSC…” button. This button displays the status of a YPbPr to RGB
color space converter in the evaluation board’s FPGA. Clicking on the button toggles the state.
There is more information about the color space converter in the next section.
Video Input Configuration
The ISL98001 evaluation platform does not automatically detect the video mode of the incoming
video signal. To obtain the correct image on the DVI monitor, the software needs to be told the format
of the incoming video signal. This is done using the Video Mode box, which is opened by selecting
“Select Input Video Mode” from the options menu.
Using the drop down menu, select the resolution and refresh rate that matches the resolution and
refresh rate of the video signal to be digitized. The input connector can also be selected at this time.
The ISL98001 evaluation board has a YPbPr to RGB color space converter (CSC) inside the FPGA.
The CSC allows YPbPr/component video signals to be displayed on TVs that expect RGB format. If
you are using such a TV, checking the “Auto Enable YPbPr to RGB Color Space Converter for Comp.
Inputs” will automatically turn on the CSC when using a component or composite input.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 12/16 Ver. 1.1, 12/19/05
Note that while there is a “composite” video connection, the ISL98001 AFE does not support
composite video decoding. It will simply digitize the composite video signal through the AFE’s video
channel. It is possible to take that digitized composite signal and perform digital decoding of the
composite signal after it is digitized, but that is beyond the function of this evaluation system.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 13/16 Ver. 1.1, 12/19/05
Operation
The DVI monitor should now be displaying the image being received by the AFE.
At this point, all the registers of the ISL98001 can be adjusted. For example, the PLL Phase register
(0x10) can be adjusted to find the optimum sampling phases for the signal.
The gain control registers (0x06 – 0x08) and the offset control registers (0x09 – 0x0B) can be
adjusted for contrast and brightness control.
The Automatic Black Level Compensation (ABLC, register 0x17) function can be disabled to compare
the image with and without ABLC
Please refer to the ISL98001 datasheet for more information on the ISL98001 and its configuration
options.
Notes
•All registers can be read by pressing the “Read All Registers” button.
•Registers 0x00 – 0x02 are read-only.
•The HTOTAL value is not latched by the ISL98001 until the LSB (0x0F) is written (i.e. writes to
the MSB only will not change the HTOTAL used by the ISL98001).
•The box at the bottom of the display can be used to read or write any register, including some
production test registers. These registers are not needed in normal operation of the Analog
Front End and are therefore not documented.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 14/16 Ver. 1.1, 12/19/05
DE Adjust
If the image on the DVI monitor is clipped, the following window allows the Data Enable (DE) signal to
be adjusted to change the position of the frame:

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 15/16 Ver. 1.1, 12/19/05
Troubleshooting
USB Driver Installation
After rebooting the PC, please verify that the following files are in the following locations:
•windrvr6.sys in C:\WINDOWS\system32\Driver
•ISL98001.inf in C:\WINDOWS\INF
•ISL98001.exe in C:\Program Files\ISL98001
USB Port
The software should be able to communicate with the evaluation board as soon as it is launched. If
there is a communication problem, the following dialog box will be displayed:
•If you see this dialog, open the Windows Control Panel. Double-click on the “System” icon and
select the “Hardware” tab, then click on Device Manager:
•
There should be a “Jungo” entry, with an ISL98001 sub category. This indicates the driver is
properly installed and is communicating with the evaluation board. If this is not visible, or there
are any error messages, take the following actions until the problem is resolved:
•Verify that the evaluation board has power and that the USB cable is connected between the
evaluation board and the PC.

Intersil Corporation
1001 Murphy Ranch Rd
Milpitas, CA 95035
Tel: [phone]
http://www.intersil.com
©2005, Intersil Corp. Page 16/16 Ver. 1.1, 12/19/05
•Power off then power on the evaluation board. You should hear 2 tones from the PC’s
speakers when the USB device is enumerated.
•Close all instances of the ISL98001 application, reset the microcontroller (the switch is next to
the USB connector), and restart the software.
•If none of this works, try installing the software on a different PC to verify correction operation
of the evaluation board and software.
•Note: The ISL98001 Evaluation Board has a Vendor ID (VID) of 0x09AA and Product ID (PID)
of 0x1004.
If the USB connection is functioning, but no image is displayed on the DVI monitor, take the following
steps:
•Make sure the input video mode (resolution, refresh rate) matches the Input Video Mode
selection in the software.
•Close the software, reset the ISL98001, reset the microcontroller, and restart the software.
•Try a different video resolution
•The Sil164 DVI transmitter used in the evaluation system is compatible with most DVI input
monitors. However there some monitors have non-standard DVI receiver implementations that
can cause incompatibilities in the DVI link. To rule this scenario out, try a different model
monitor.

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ISL98001
Test Points
From Page 2
of
schematics
Note: R156,R157,R158 Do not stuff
Default stuffing R28,R33
ISL98001 1.0
ISL98001 Evaluation Board
B
17Tuesday, March 29, 2005
Title
Size Document Number Rev
Date: Sheet of
VSYNCOUT
DATACLK_S
DATACLKB_S
HSOUT_S
VSOUT_S
HSYNCOUT_S
VSYNCOUT_S
RS0
RS_D6
RS_D4
RS7
RS_D0
RS3
RS_D1
RS_D3
RS6
RS_D2
RS5
RS4 RS_D5
RS1
RS_D7
RS2
GP0
GP_D6
GP_D4
GP7
GP_D0
GP3
GP_D1
GP_D3
GP6
GP_D2
GP5
GP4 GP_D5
GP1
GP_D7
GP_D[7..0]
GP2
GS0
GS_D6
GS_D4
GS7
GS_D0
GS3
GS_D1
GS_D3
GS6
GS_D2
GS5
GS4 GS_D5
GS1
GS_D7
GS2
BP0
BP_D6
BP_D4
BP7
BP_D0
BP3
BP_D1
BP_D3
BP6
BP_D2
BP5
BP4 BP_D5
BP1
BP_D7
BP_D[7..0]
BP2
BS0
BS_D6
BS_D4
BS7
BS_D0
BS3
BS_D1
BS_D3
BS6
BS_D2
BS5
BS4 BS_D5
BS1
BS_D7
BS_D[7..0]
BS2
HSYNCOUT
VSOUT
HSOUT
DATACLKB
DATACLK
RP3
RP4
RP7
RP_D3
RP0
RP_D6
RP1 RP_D0
RP_D5RP5
RP_D1
RP_D7
RP2
RP_D4
RP6
RP_D2
VREGout
DVdd
BLUE1
VSYNC1
DDC_SCL1
RED1
GREEN1
DDC_SDA1
HSYNC1
RP_D[7..0]
RS_D[7..0]
GS_D[7..0]
GNDx
Vb16
RS4
RS6
GS3
BS2
RP7
RS7
GS0
BP7
BS5
HSYNCOUT
RP3
GP6
BP6
BP4
BP0
GS1
BS4
VS1
GP2
XRESET
GNDx
AVss
DATACLK
DVss
GP7
BP3
BS3 BS7
RP1
RGBgnd1
DATACLKB
GP5
HS2
VREGout
HSOUT
RP6
RS3
RS5
BS1
Vb9 RS0
GP3
RP4
GP4
GS7
DVdd
RP0
GP1
BP2
BP1
BS6
SCL
RP5
GS6
GS4
SDA
Vb4
VSYNCOUT
VSOUT
BP5
BS0
VS2
RP2
RS1
RS2
GP0
GS5
GS2
HS1
VSYNC2
DATACLK RGBgnd1 VS1
HSOUT
VS2 DATACLKB
VSYNC1 HSYNC1VSYNCOUT
HSYNCOUT VSOUT
HSYNC2
RED1
RGBgnd2
BLUE1
GREEN1
GNDx
DVss
A_GND
3.3REG(4)
DDC_SDA1 (3)
HSYNC1
VSYNC1
DDC_SCL1 (3)
R_IN_2(2)
RGBgnd2(2)
G_IN_2(2)
SOG_IN_2(2)
XTALCLKOUT (5)
SDA (7)
SCL (7)
RS_D[7..0] (3,5)
GP_D[7..0] (3,5)
BP_D[7..0] (3,5)
BS_D[7..0] (3,5)
RP_D[7..0] (3,5)
GS_D[7..0] (3,5)
HSYNCOUT_S (3,5)
VSYNCOUT_S (3,5)
VSOUT_S (3,5)
HSOUT_S (3,5)
DATACLKB_S (3,5)
DATACLK_S (3,5)
PLL_COAST_EXT(2)
VIDEO_CLAMP_EXT(2)
B_IN_2(2)
HSYNC1
VSYNC2(2)
VSYNC1
HSYNC2(2)
DVdd_3.3V
5V_VGA1
AVdd_3.3V
XVdd_3.3V
DVdd_3.3V
TP10
1
R33
0 Ohm
R6
22
R19
4.7K
SW1
KN11B
R2
75
C13
0.01uF
VSin2
1
Y1
25 Mhz
RP13
33 Ohm
1
2
3
4 5
6
7
8
C9
22pF
R156
0 Ohm
R5
4.7K
C15
0.01uF
HSin2
1
RP14
33 Ohm
1
2
3
4 5
6
7
8
JP24
1
2
C10
22pF
VS2
1
RP5
33 Ohm
1
2
3
4 5
6
7
8
C17
0.01uF
U1
X98001LC
7
12
14
19
13
22
24
26
28
25
33
44
34
45
41 46 55 56 57 58 59 60 61 62
75
74
73
72
71
70
69
68
87
86
85
84
83
81
82
80
90
91
92
93
94
95
96
97
100
101
102
103
104
105
106
107
112 113 114 115 116 117 118 119 125 126 128
48 50 49
67
77
89
99
111
6
11
18
39 40
98
108
110
120
123
121 122
47
37
88
64 79 109
4
9
16
1
3
5
10
15
17
21
23
27
36
30
65
29
63
31 42
78
52 127
2
8
20
38
124
54
43
51
53
66
76
35
32
R_IN_1
G_IN_1
SOG_IN_1
B_IN_1
RGBgnd1
R_IN_2
G_IN_2
SOG_IN_2
B_IN_2
RGBgnd2
HSYNC_IN_1
VSYNC_IN_1
HSYNC_IN_2
VSYNC_IN_2
CLOCKINVin RESETb Bs7 Bs6 Bs5 Bs4 Bs3 Bs2 Bs1 Bs0
Bp0
Bp1
Bp2
Bp3
Bp4
Bp5
Bp6
Bp7
Gs0
Gs1
Gs2
Gs3
Gs4
Gs6
Gs5
Gs7
Gp7
Gp6
Gp5
Gp4
Gp3
Gp2
Gp1
Gp0
Rs7
Rs6
Rs5
Rs4
Rs3
Rs2
Rs1
Rs0
Rp7 Rp6 Rp5 Rp4 Rp3 Rp2 Rp1 Rp0
HSOUT
VSOUT
VSYNCOUT
SADDR SCL SDA
Vd
Vd
Vd
Vd
Vd
Va
Va
Va
XTALin XTALout
GNDd
GNDd
GNDd
GNDd
GNDd
DATACLK
DATACLKB
XTALCLKout
GNDx
GNDd
VREGout
Vcore Vcore
Vbypass
Vbypass
Vbypass
NC1
GNDa
GNDa
GNDa
GNDa
GNDa
GNDa
GNDa
GNDa
GNDa
GNDa
VREGin
Va
NC3
Vcoreadc
Vpll
GNDd
Vcore
HSYNCOUT
NC2
GNDa
Va
Vx
Vd
Vd
GNDd
GNDd
GNDd
GNDd
GNDd
Va
GNDd
VS1
1
FB7
R3
22
TP2
1
C3
10 nF
FB5
R158
0 Ohm
RP11
33 Ohm
1
2
3
4 5
6
7
8
RP6
33 Ohm
1
2
3
4 5
6
7
8
R28
0 Ohm
C18
4.7 uF
TP12
1
R7
75
C150
10uF
RP12
33 Ohm
1
2
3
4 5
6
7
8
TP11
1
R151
500
C155
0.1uF
R18
1K
C1
0.1uF
R4
75
RP9
33 Ohm
1
2
3
4 5
6
7
8
R154
4.7K
R17
680
R157
0 Ohm
R16
1K
gnd2
1
TP7
1
TP16
1
TP1
1
JP1
VGA1-HD-15HF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R14
680
Rin1
1
FB6
RP10
33 Ohm
1
2
3
4 5
6
7
8
Gin1
1
RP3
33 Ohm
1
2
3
4 5
6
7
8
TP15
1
R21
33 Ohm
C4
0.1uF
gnd1
1
C12
0.1uF
JP44
1
2
3
Bin1
1
TP13
1
TP14
1
RP4
33 Ohm
1
2
3
4 5
6
7
8
C19
0.1uF
C25
0.1uF
C2
0.1uF
RP7
33 Ohm
1
2
3
4 5
6
7
8
C157
0.1uF
VSin1
1
JL6
12
C14
0.1uF
RP1
33 Ohm
1
2
3
4 5
6
7
8
R20
100
R155
50K
HSin1
1
RP2
33 Ohm
1
2
3
4 5
6
7
8
RP8
33 Ohm
1
2
3
4 5
6
7
8
C16
0.1uF
TP81
R1
22
TP9
1

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To X980xx Channel 2
To X980xx Channel 2
Test Points
COMPONENT
VIDEO 1
COMPONENT
VIDEO 2
COMPOSITE
VIDEO
COMPUTER
RGB
Note: Put 75 Ohm termination close to U31
input as possible. Shield R,G, and B inputs
with ground traces.
From CYPRESS mP
32-Pin QFN
24-Pin QSOP
Pr1
Pb1
Y1
Y2
Pr2
Pb2
ISL98001 1.0
ISL98001 Evaluation Board
B
27Tuesday, March 29, 2005
Title
Size Document Number Rev
Date: Sheet of
BLUE2
HSYNC2
RED2
GREEN2
DDC_SCL2
DDC_SDA2
VSYNC2
RGBgnd2
PR1
Y1
OUTB
OUTC
OUTA
MP_S0
MP_S1
COMPS1
PB1
PR2
Y2
PB2
RED2
GREEN2 BLUE2
PR1
Y1 PB1
PR2
Y2 PB2
COMPS1
DDC_SDA2 (3)
HSYNC2 (1)
VSYNC2 (1)
DDC_SCL2 (3)
VSYNC2(1)
HSYNC2(1)
MP_S1(7) MP_S0(7)
MP_P1(7) MP_P0(7)
ISL_SDENB#(7)
ISL_SCL
(7)
ISL_SDA(7)
G_IN_2 (1)
SOG_IN_2 (1)
B_IN_2 (1)
MP_ODD_EVEN_FIELD (7)
VSYNC2 (1)
HSYNC2 (1)
VIDEO_CLAMP_EXT (1)
PLL_COAST_EXT (1)
RGBgnd2(1)
R_IN_2 (1)
5V_VGA2
AVdd_3.3V
5V
-5V
5V
PB1
1
J10C RCA_COM
3
6
R177
75
J9A RCA_COM
1
2
R174
75
C5
0.1uF
PR2
1
R175
75
R9
75
COMPS1
1
R30 20K
C6
0.1uF
R31
10K
R173
75
Y2
1
R15
75
R32
100K
U23
EL4511CU
1
2
3
4
5
6
7
8
9
10
11
12 13
15
24
14
16
17
18
20
19
21
22
23
XTAL
VBLANK
SYNCLOCK
PDWN
SDENB
SCL
SDA
GNDD1
HIN
SYNCIN
VERTIN
LEVEL GNDA1
VCCA2
XTALN
VCCA1
GNDA2
GNDD2
VCCD
BACKPORCH
SYNCOUT
HOUT
VERTOUT
ODD/EVEN
C164
0.1uF
C24
22pF
JP4
1 2
Q1
MPS3906
C165
0.1uF
J9B RCA_COM
3
4
C163
0.1uF
PB2
1
JL43
1 2
C20
0.1uF
C8
0.1uF
Bin2
1
R12
4.7K
Gin2
1
R178
75
PR1
1
Rin2
1
R8 22
R10 22
R13 22
J10A RCA_COM
1
2
J11
RCA_Y
2
1
R29
75
C7
10 nF
R11
75
J9C RCA_COM
3
6
R150500
Y1
1
U31
EL4342
1
6
9
2
8
10
4
7
13
3
11
5
15 24
28
17
21
19
20
22
23
26
25
30
12
14
16
18
27
29
31
32
IN1A
GNDB
IN2B
NC1
GND
IN2C
NC2
IN2A
NC3
IN1B
GNDC
IN1C
NC4 NC5
NC6
S1
VSM
OUTC
OUTB
OUTA
VSP
HIZ
ENABLE
NC7
IN3A
IN3B
IN3C
S0
IN0C
IN0B
IN0A
GNDA
J10B RCA_COM
3
4
JP2
VGA1-HD-15HF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R176
75

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EDID EEPROM 1
EDID EEPROM 2
LA_POD_3
LA_POD_0 LA_POD_2
LA_POD_1
LOGIC ANALYZER HEADERS
Note: Place EDID EEPROM on
bottom layer
ISL98001 1.0
ISL98001 Evaluation Board
B
37Tuesday, March 29, 2005
Title
Size Document Number Rev
Date: Sheet of
DDC_SDA1
DDC_SCL1
DDC_SCL2
DDC_SDA2
GS_D1
RP_D4
RP_D2
GP_D7
BS_D3
BS_D2
RP_D5
RP_D6
GP_D2
GS_D6
BS_D7
BS_D1
BP_D2
GP_D3
BS_D6
DATACLK_S
BP_D[7..0]
GS_D[7..0]
GS_D2
GP_D6
GP_D[7..0]
BP_D5
RP_D1
GP_D5
GS_D4
BP_D1
GS_D3
RP_D3
BP_D6
BS_D4
BS_D0
GP_D4
BP_D4
GP_D1
BP_D3
GS_D0
BP_D0
GS_D5
RP_D0
BP_D7RP_D7
BS_D5
GS_D7
GP_D0
BS_D[7..0]
RP_D[7..0]
RS_D5
RS_D[7..0]
RS_D6
RS_D1
RS_D4
RS_D7
RS_D0
RS_D2
RS_D3
RP_D[7..0] (1,5)
GP_D[7..0] (1,5)
GS_D[7..0] (1,5)
BP_D[7..0] (1,5)
BS_D[7..0] (1,5)
DATACLK_S (1,5)
DATACLKB_S (1,5)
HSOUT_S (1,5)
VSOUT_S (1,5)
HSYNCOUT_S (1,5)
VSYNCOUT_S (1,5)
DDC_SDA2 (2)
DDC_SCL2 (2)
DDC_SDA1 (1)
DDC_SCL1 (1)
RS_D[7..0] (1,5)
DATACLK_S(1,5)
5V_VGA1
5V_VGA2
U4
24LC02 + SMT
1
2
3
4 5
6
7
8
A0
A1
A2
Gnd SDA
SCL
WP
VCC
U3
24LC02 + SMT
1
2
3
4 5
6
7
8
A0
A1
A2
Gnd SDA
SCL
WP
VCC
R26
4.7K
HDR23
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
HDR18
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
C28
0.1uF
JP13
1
2
HDR16
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
R25
4.7K
HDR22
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
HDR15
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
HDR17
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
C22
0.1uF
HDR21
HEADER 8x2/SM
12
34
56
78
910
11 12
13 14
15 16
R23
4.7K
R22
4.7K

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5V
POWER
For U1 Decoupling Capacitor
FPGA and DVI Tx
3.3V-Regulator
TO220
TO220
Not Stuff
Xilinx FPGA VccAUX and VccCORE
For FPGA Decoupling
Capacitor
Xilinx FPGA FLASH ROM
Red Power ON LED
-5V supply for EL4342
ISL98001LC 1.0
ISL98001 Evaluation Board
B
47Tuesday, March 29, 2005
Title
Size Document Number Rev
Date: Sheet of
POWERIN 5V 3.3V
5V
ADJ
2.5V
3.3V 3.3V
1.2V
CY_DIN0
CY_CLK
TDO
TMS
TCK
CY_PROG
CY_DONE
CY_INITB
3.3REG(1)
TDO(5)
TMS(5)
TCK(5)
CY_DIN0(5,7)
CY_CLK(5,7)
CY_PROG(5,7)
CY_DONE(5,7)
CY_INITB(5,7)
TDI (5)
5V
DVdd_3.3V
AVdd_3.3V
XVdd_3.3V
3.3V
5V
2.5V
2.5V
3.3V
1.2V
3.3V
3.3V
3.3V
-5V
5V
1.2V
C54
0.1uF
+
C39
10uF
12
+
C34
100uF
12
C72
0.1uF
U8
LM317
3
1
2
4
VIN
ADJ
VOUT
TAB
C69
0.1uF
R164
1.1K
C40
0.1uF
J6
2.1mm
1
2
+
C51
10uF
12
C70
0.1uF
R190
100
C168
0.01uF
R48
390
D9
LED
+
C32
10uF
12
C65
0.1uF
C11 0.1uF
TP5
1
C77
0.1uF
+
C35
47uF
12
C53
0.1uF
C58
0.1uF
C79
0.1uF
C64
0.1uF
C167
22uF
12
C166
0.1uF
R47
240
R163
330
TP6
1
C73
0.1uF
C23
0.1uF
C68
0.1uF
C75
0.1uF
C57
0.1uF
R42
0 Ohm
C78
0.1uF
C55
0.1uF
SW3
C63
0.1uF
U29
LM1117
1 2 3
4
ADJ Vo2 Vin
Vo4
C36
0.1uF
R152
1K
U32
XCF02S_VO20
1
2
9 12
14
15
16
11
20
19
18
13
10
3
4
5
6
7
8
17
D0
NC1
NC2 NC3
NC4
NC5
NC6
GND
VCCJ
VCCO
VCCINT
CEO
CE
CLK
TDI
TMS
TCK
CF
OE/RESET
TDO
R34
1.8K
R189 100
C71
0.1uF
C169
0.1uF
D7
C26
0.01uF
C50
0.1uF
C52
0.1uF
U9
LM317
3
1
2
4
VIN
ADJ
VOUT
TAB
JL31
1 2
R35
1.1K
U34
ICL7660S
1
2
3
4 5
6
7
8
BOOST
CAP+
GND
CAP- VOUT
LV
OSC
V+
C76
0.1uF
L4
FB
JL32
1 2 C74
0.1uF
L5
FB
C42
0.1uF
U30
LM1117
1 2 3
4
ADJ Vo2 Vin
Vo4
+
C189
10uF
12
C43
0.1uF
JL33
1 2
D1
LED0
+
C190
10uF
1 2
TP18
1
C66
0.1uF
R44
390
C44
0.1uF
C56
0.1uF
R43
240
L1
FB
R27
1K
L3
FB C38
0.1uF
R188 100
C187
22uF
12
JP411
2
3
C45
0.1uF
C33
0.1uF
+
C49
47uF
12
L2
FB
C67
0.1uF
TP4
1
C41
0.1uF