Intersil ISL70219ASEHEV1Z User manual

USER MANUAL
UG007
Rev.1.0
Jul 1, 2021
ISL70219ASEHEV1Z
Evaluation Board
UG007 Rev.1.0 Page 1 of 8
Jul 1, 2021 © 2014 Renesas Electronics
Introduction
The ISL70219ASEHEV1Z evaluation platform is designed to
evaluate the ISL70219ASEH. The ISL70219ASEH contains two
very high precision amplifiers featuring the perfect combination
of low noise vs power consumption. Low offset voltage, low IBIAS
current and low temperature drift making them the ideal choice
for applications requiring both high DC accuracy and AC
performance. The combination of high precision, low noise, low
power and small footprint provides the user with outstanding
value and flexibility relative to similar competitive parts.
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
The ordering number for this board is ISL70219ASEHEV1Z.
Please go to ordering tab on the landing page for the
ISL70219ASEH.
Related Literature
•ISL70219ASEH Datasheet
• ISL70219ASEH SMD 5962-14226
• ISL70219ASEH Radiation Test Report
• TR002: Single Event Effects (SEE) Testing of the
ISL70219ASEH Dual Operational Amplifier
Key Features
•WideV
IN range single supply or dual supply
- ±2.25V to ±18V
- +4.5V to +36V
• Singled-ended or differential input operation
• External VREF input
• Banana Jack connectors for power supply and VREF inputs
• BNC connectors for op amp input and output terminals
• Convenient PCB pads for op amp input/output impedance
loading.
Specifications
• V+ range: +2.25V to 18V
• V- range: -2.25V to -18V
• Common mode input range: 2V within V+ and V- rails.
Ordering Information
PART NUMBER DESCRIPTION
ISL70219ASEHEV1Z Evaluation Board
FIGURE 1. ISL70219ASEHEV1Z EVALUATION BOARD

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ISL70219ASEHEV1Z USER MANUAL
Power Supplies
External power connections are made through the +V, -V, VREF
and Ground connections on the evaluation board. For single
supply operation, the -V and Ground pins are tied together to the
power supply negative terminal. For split supplies, +V and -V
terminals connect to their respective power supply terminals.
Decoupling capacitors C2, C3, C4and C6connect to their
respective supplies through R11 and R14 resistors. These
resistors are 100Ωbut can be changed by the user to provide
additional power supply filtering, or to reduce the voltage rate of
rise to less than ±1V/µs. Two additional capacitors, C5 and C7,
are connected close to the part to filter out high frequency noise.
Anti-reverse diode D1protects the circuit in the momentary case
of accidentally reversing the power supplies to the evaluation
board. The VREF pin can be connected to ground to establish a
ground referenced input for split supply operation, or can be
externally set to any reference level for single supply operation.
Amplifier Configuration
A simplified schematic of the evaluation board is shown in
Figure 2. The input stage with the components supplied is
shown in Figure 4, with a closed loop gain of 10V/V. The
differential amplifier gain is expressed in Equation 1:
For single-ended input with an inverting gain G = -10V/V, the
IN+ input is grounded and the signal is supplied to the IN-
input. The VREF can be connected to a reference voltage
between the V+ and V- supply rails. For non-inverting operation
with G = 11V/V, the IN- input is grounded and the signal is
supplied to the IN+ input. The non-inverting gain is strongly
dependent on any resistance from IN- to GND. For good gain
accuracy, a 0Ωresistor should be installed on the empty R5
pad. The VREF pin must be connected to ground to establish a
ground referenced input for dual supply operation, or can be
externally set to any reference level for single supply
operation. The VREF should not be left floating.
PCB Layout Considerations
There a few layout constraints to consider when using the
ISL70219ASEH, but this will generally apply to any generic
operational amplifier. Analog circuits can conduct noise
through paths that connect it to the “outside world”. These
paths include the V+, V-, IN+, IN- and OUT terminals. It’s
important to make sure these paths are kept away from
known noise sources to ensure optimal performance of the
part. If the ISL70219ASEH resides on the same boards as
digital circuitry it is necessary to decouple the power pins on
the analog as well as the digital circuitry. This is done on the
evaluation board with C2through C7, with the lower value
capacitors, C5and C7, placed near the V- and V+ pins
respectively to minimize high frequency noise.
FIGURE 2. BASIC AMPLIFIER CONFIGURATION
IN-
IN+
RF
VREF
IN-
IN+
GND
100kΩ
RREF+
VOUT
ISL70219 (1/2)
VP
V-
0Ω
VN
VCM
IN-
IN+
VREF
V+
RIN-
10kΩ
RIN+
10kΩ
100kΩ
RL
DNP
-
+
+
-
-
+
+
-
VOUT VIN+ VIN-RF  RIN–VREF += (EQ. 1)
0.01µF0.01µF
R14
R11
D1
C2 C4
C5 C7
J7
J10
J8 J9
J5
J6
100
100
1µF 1µF
VREF
V+V-
FIGURE 3. POWER SUPPLY CIRCUIT
0.1µF0.1µF
C3 C6

UG007 Rev.1.0 Page 3 of 8
Jul 1, 2021
ISL70219ASEHEV1Z USER MANUAL
User-selectable Options
Component pads are included to enable a variety of
user-selectable circuits to be added to the amplifier VREF, inputs,
outputs, and the amplifier feedback loops.
A voltage divider (Figure 4, R6and R12) can be added to
establish a power supply-tracking common mode reference
using the VREF input. The input stages (see Figure 4) have
additional resistor and/or capacitor pads that may be used to
add voltage divider networks or feedback networks for adding
input attenuation, or to establish input DC offsets through the
VREF pin. The output stages (see Figure 5) have additional
resistor and capacitor placements for loading.
NOTE: Operational amplifiers are sensitive to output capacitance
and may oscillate. In the event of oscillation, reduce output
capacitance by using shorter cables, or add a resistor in series
with the output.
FIGURE 4. INPUT STAGE (1/2) FIGURE 5. OUTPUT STAGE (1/2)
C1
R5
R3
J2
J1
R1
R2
R10
R12
R6
R9 R4
DNP
DNP
DNP
OPEN
DNP
10k 100k
100k
10k
0
VREF IN+
IN-
OUTPUT
R26
C6
R28 DNP
OPEN
OPEN
0
FROM OUTPUT
Bill of Materials
DEVICE # DESCRIPTION COMMENTS
C2, C4 CAP, SMD, 1206, 1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling
C3, C6 CAP, SMD, 0805, 0.1µF, 50V, 10%, X7R, ROHS Power Supply Decoupling
C5, C7 CAP, SMD, 0603, 0.01µF, 25V, 10%, X7R, ROHS Power Supply Decoupling
C1, C8, C9, C10, C11, C12 CAP, SMD, 0603, DNP-PLACE HOLDER, ROHS User selectable capacitors - not populated
D1 DIODE-SCHOTTKY BARRIER, SMD, SOT-23, 3P, 40V, ROHS Reverse Power Protection
U1 ISL70219ASEHF/PROTO, DUAL OP AMP, 10Ld. FLATPACK
R1, R2, R5, R7, R8, R9, R17, R20, R23,
R24
RESISTOR, SMD, 0603, 0.1%, MF, DNP PLACEHOLDER User selectable resistors - not populated
R3, R19, R21, R22 RES, SMD, 0603, 0Ω, 1/10W,TF, ROHS 0Ωuser selectable resistors
R11, R14 RES, SMD, 0603, 100Ω, 1/10W, 1%, TF, ROHS
R4, R6, R16, R18 RES, SMD, 0603, 10kΩ, 1/10W, 1%, TF, ROHS Gain resistors
R10, R12, R13, R15 RES, SMD, 0603, 100kΩ, 1/10W, 1%, TF, ROHS Gain resistors

UG007 Rev.1.0 Page 4 of 8 Jul 1, 2021
ISL70219ASEHEV1Z USER MANUAL
FIGURE 6. ISL70219ASEHEV1Z SCHEMATIC DIAGRAM
RELEASED BY:
DRAW N BY: DATE:
DATE:
DATE:
DENGINEER:
TITLE:
UPDATED BY:
TIM KLEMANN
10/14/2014
Kiran Bernard
ISL70219ASEH
EVALUATION BOAR
IN- A
IN- B
IN+ B
IN+ A
OUT B
OUT A
C3 AND C5 CLOSE TO PART
V-
VREF
V+ VREF
R8
DNP
J10
100K
R10
0.01UF
C7
JP1
DNP
R7
J5
C6
0.1UF
R5
DNP
LID
+INB
-INB+INA
-INA OUTB
V+
V-
NC
OUTA
ISL70219ASEHVF
U1
1
2
3
4
5 6
7
8
9
10
R2
DNP
R20
DNP
R11
100
R14
100
R6
10K
DNP
R23
DNP
R1
OPEN
C9
J9
R4
10K
R24
DNP
D1
1 2
3
R22
0
0.01UF
C5
OPEN
C10
J4
10K
R18
J12
C8
OPEN
0.1UF
C3
R15
100K
J3
J11
R13
100K
0
R21
R12
100K
R16
10K
J2
R19
0
R9
DNP
J7
C12
OPEN
C2
1UF
J8
J1
C1
OPEN
C4
1UF
R17
DNP
R3
0
C11
OPEN
J6

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Jul 1, 2021
ISL70219ASEHEV1Z USER MANUAL
ISL70219ASEH Board Layout
FIGURE 7. TOP VIEW

UG007 Rev.1.0 Page 6 of 8
Jul 1, 2021
ISL70219ASEHEV1Z USER MANUAL
Typical Performance Curves
FIGURE 8. FREQUENCY RESPONSE vs ACL (±5.0V) FIGURE 9. FREQUENCY RESPONSE vs ACL (±18.0V)
FIGURE 10. FREQUENCY RESPONSE vs RL(±5.0V) FIGURE 11. FREQUENCY RESPONSE vs RL(±18.0V)
FIGURE 12. FREQUENCY RESPONSE vs CL(±5.0V) FIGURE 13. FREQUENCY RESPONSE vs CL(±18.0V)
-60
-40
-20
0
20
40
60
80
100 1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
ACL1
ACL10
ACL100
ACL1000
-60
-40
-20
0
20
40
60
80
100 1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
ACL1
ACL10
ACL100
ACL1000
-10
-8
-6
-4
-2
0
2
4
1k 10k 100k 1M 10M
FREQUENCY (Hz)
RL=100Ω
RL= 500Ω
RL= 5kΩ
RL= 10kΩ
GAIN (dB)
RL= 1kΩ
-10
-8
-6
-4
-2
0
2
4
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
RL= 100Ω
RL= 500Ω
RL= 5kΩ
RL= 10kΩ
RL= 1kΩ
-10
-8
-6
-4
-2
0
2
4
6
8
10
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
CL= 4pF
CL= 470pF
CL= 1000pF
CL= 220pF
CL= 43pF
CL= 150pF
-10
-8
-6
-4
-2
0
2
4
6
8
10
1k 10k 100k 1M 10M
GAIN (dB)
FREQUENCY (Hz)
CL= 4pF
CL= 43pF
CL= 150pF
CL= 220pF
CL= 470pF
CL= 1000pF

UG007 Rev.1.0 Page 7 of 8
Jul 1, 2021
ISL70219ASEHEV1Z USER MANUAL
FIGURE 14. FREQUENCY RESPONSE vs SUPPLY VOLTAGE (+25°C) FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE (+25°C)
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE (+25°C) FIGURE 17. SLEW RATE vs TEMPERATURE VS = ±5V
FIGURE 18. SLEW RATE vs TEMPERATURE VS = ±18V FIGURE 19. ±18V POSITIVE SATURATION RECOVERY TIME (+25°C)
Typical Performance Curves (Continued)
-10
-8
-6
-4
-2
0
2
1k 10k 100k 100M 10M
GAIN (dB)
FREQUENCY (Hz)
VS= ±19.8V
VS= ±2.25V
VS= ±16.2V
VS= ±2.75V
VS= ±18V
VS= ±5V
VS= ±5.5V
VS= ±4.5V
VS= ±2.5V
TIME (µs)
SMALL SIGNAL TRANSIENT RESPONSE (mV)
-10
0
10
20
30
40
50
60
0 5 10 15 20 25 30 35 40
RL= 10k
AV= +1
CL= 4pF
VOUT = 50mVP-P
VS=±5, ±18V
TIME (µs)
LARGE SIGNAL TRANSIENT RESPONSE (V)
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
0 102030405060708090100
AV= +1
CL= 4pF
VOUT = 4VP-P
VS= ±5V, RL= 2k, 10k
VS= ±18V, RL= 2k, 10k
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-75 -50 -25 0 25 50 75 100 125 150
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
SLEW RATE (V/µs)
TEMPERATURE (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-75 -50 -25 0 25 50 75 100 125 150
SLEW RATE (V/µs)
TEMPERATURE (°C)
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
-0.24
-0.20
-0.16
-0.12
-0.08
-0.04
0
0.04
0.08
0 102030405060708090
INPUT VOLTAGE LEVEL (V)
TIME (µs)
INPUT
+25°C
-55°C
+125°C

UG007 Rev.1.0 Page 8 of 8
Jul 1, 2021
ISL70219ASEHEV1Z USER MANUAL
Revision History
FIGURE 20. ±18V NEGATIVE SATURATION RECOVERY TIME (+25°C) FIGURE 21. ±5V POSITIVE SATURATION RECOVERY TIME (+25°C)
FIGURE 22. ±5V NEGATIVE SATURATION RECOVERY TIME (+25°C)
Typical Performance Curves (Continued)
-0.08
-0.04
0
0.04
0.08
0.12
0.16
0.20
0.24
0 1020304050607080 90
TIME (µs)
INPUT VOLTAGE LEVEL (V)
-55°C
INPUT
+125°C
+25°C
-0.28
-0.24
-0.20
-0.16
-0.12
-0.08
-0.04
0
0.04
0 102030405060708090
TIME (µs)
INPUT VOLTAGE LEVEL (V)
+125°C
INPUT
+25°C
-55°C
-0.04
0
0.04
0.08
0.12
0.16
0.20
0.24
0.28
0 102030405060708090
TIME (µs)
INPUT VOLTAGE LEVEL (V)
-55°C
INPUT
+125°C
+25°C
REVISION DATE DESCRIPTION
1.0 Jul 1, 2021 Updated BOM, Figure 7, and minor text edits throughout document.
0.0 Oct 31, 2014 Initial release.

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