Intersil ISL70321SEHDEMO1Z User manual

Rev 0.00 Jul 2017
User’s Manual
ISL70321SEHDEMO1Z
User’s Manual: Demonstration Board
High Reliability

UG124 Rev.0.00 Page 2 of 9
Jul 24, 2017
UG124
Rev.0.00
Jul 24, 2017
ISL70321SEHDEMO1Z
Demonstration Board
USER’S MANUAL
1. Overview
The ISL70321SEHDEMO1Z is a Small Form Factor (SFF) board suitable for integrating onto an existing circuit board
or onto a prototype system circuit. The demonstration board provides up to four sequencing events for Point-of-Load
(POL) regulators powering multi-rail loads.
The ISL70321SEHDEMO1Z provides access to the IC pins for integration along with a minimum of external passives
to provide decoupling, a 2:1 resistive divider on the four VM inputs, pull-ups, and the timers set to 2ms and 4ms for the
delay and power-good durations, respectively.
1.1 Key Features
• Small, compact design
• Easy to integrate into an existing circuit
• Highly customizable
1.2 Specifications
This board provides for the following operating conditions:
•Nominal V
IN = 3.3V to 12V
• Sequence up and down in reverse order
• 1.5% accuracy voltage monitoring
• Adjustable voltage monitoring thresholds
• Adjustable delay between sequenced events
• Adjustable power-good delay
1.3 Ordering Information
1.4 Related Literature
• For a full list of related documents please visit our website
•ISL70321SEH product page
Part Number Description
ISL70321SEHDEMO1Z ISL70321SEH Mini Demonstration Board
Figure 1. Block Diagram
4xEN
4xVMIN
VDD
GND
KILL
UP
INIT
DONE
VCC5
ISL70321SEH

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ISL70321SEHDEMO1Z 2. Board Functional Description
2. Board Functional Description
The ISL70321SEHDEMO1Z demonstration board provides a simple platform with which to drop in an integrated
circuit solution to sequence up to four events into an existing or a prototype multi power supply system circuit.
After it is connected into the circuit and properly addressed using the UP and INIT inputs, the ISL70321DEMO1Z
starts sequencing the ENABLE outputs from low to high, EN1 through EN4 order. The DONE output is released to
pull high after sequencing is completed.
After the UP input is pulled low, the ISL70321SEHDEMO1Z starts sequencing the ENABLE outputs from high to
low, EN4 through EN1 order. The DONE output is pulled low when the down sequencing is completed.
The ISL70321SEHDEMO1Z is shown in Figures 8 through 10 in photographic and schematic forms.
2.1 Operating Range
The ISL70321SEHDEMO1Z is configured for the operating conditions of VDD from 3V to 13.2V, with the ENx
outputs resistively connected to the VCC5 5V pull-up supply. The VMx, UP, and INIT inputs are limited to a
maximum of 5V.
2.2 Default Configuration Settings
All functional and performance configuration settings for this demonstration board will be set by the circuit design
requirements. However, a default set of conditions for the VM input threshold and the delay timing have been
configured for building familiarity with its functions before system integration.
The default configuration is set as follows:
• The VMx inputs all have 2:1 resistor dividers from the VMx_IN connection points to the VM1 to VM4 inputs.
This sets the nominal VM rising input voltage threshold to be ~1.2V.
• The ENx, DONE, and KILL outputs all have 10kΩ pull-up resistors to VCC5.
• The Power-Good Timer (PGTMR) and the Time Delay (TDLY) pins both have 10kΩ resistors to ground
providing a nominal 4ms for the monitored voltage to be ‘GOOD’ and a nominal 2ms for the delay between
sequenced enable outputs.
2.3 Quick Start Guide
With the default or user intended configuration components in place, ensure that the board is properly connected to
the appropriate supplies and loads before applying any power.
(1) Change the delay and power-good timer resistors on the board as necessary to achieve the desired timing of
sequenced events using the provided resistor positions.
(2) Connect the appropriate bias supply to VDD and GND.
(3) Connect the enabling input of the POLs to be sequenced to the appropriate ISL70321SEH ENx outputs in
order of desired turn-on sequence
(4) Connect the POL outputs to the appropriate ISL70321SEH VMx inputs.
(5) Connect UP to the appropriate signaling input.
(6) Use oscilloscopes and DVMs to monitor signals and voltages.
(7) Turn system input power supply ON.
(8) Signal the UP input.
(9) Observe sequencing function and adjust timing and threshold voltages as desired.

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ISL70321SEHDEMO1Z 3. Application Considerations
3. Application Considerations
3.1 Connecting Unused Rails
The simplified schematic in Figure 2 highlights the necessary connections for unused ENX and VMXun pins. The
unused VMX and ENX must be shorted together in pairs and each pair pulled up to VCC5 with an external resistor.
An unused ENx/VMx pair can be used to establish a delayed active high output for down stream signaling.
Figures 4 and 5 illustrate three POLs being turned on and off respectively.
3.2 Automatic Fault Clearing Reset and Restart Configuration
There is an auto restart configuration in case the ISL70321SEH is set up to be self starting upon bias without
signaling. When the ISL70321SEH restarts, it will sequence up all of its ENABLE outputs without intervention.
The EN output delays can be programmed to allow for the down stream sequenced circuits to be ready before being
enabled. Faults resulting in an immediate KILL will then make the ISL70321SEH cycle through an infinite number
of attempts at restarting and KILL shut down until the fault is cleared. Figure 3 shows the auto restart connection.
When KILL is invoked, it is used to automatically clear and reset the sequencer. This results in the ISL70321SEH
attempting to restart the entire sequence up progression. Figure 6 shows the details of a low VM input (to invoke a
KILL), the KILL output pulling low with both the UP and INIT pins low as well. Figure 7 shows the resulting
restart with EN1, EN, DONE, and KILL signals.
This configuration can be used if required criteria must be met before turn-on by continuously checking for those
requirements while attempting turn-on.
In this configuration, the sequence down can be invoked through a pull down on UP/INIT with isolation to KILL
input. Using KILL as an input will produce a simultaneous shutdown of the EN outputs.
Figure 2. Connecting Unused Rails
Figure 3. Auto Fault Clear and Reset Configuration
POL-1
EN
VO1
18
17
16
15
14
1
2
3
4
5
VDD
INIT
UP
VM1
VM2
VCC5
EN1
EN2
EN3
EN4 13
12
11
6
7
8
VM3
VM4
PGTMR
DONE
KILL
GND 109TDLY
VREF
5V
POL-2
EN
VO2
5V
5V
VCC5
KILL
INIT
UP
ISL70321SEH
GND
10k
10k
10k
10k
90k

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ISL70321SEHDEMO1Z 3. Application Considerations
Figure 4. Sequencing On 3 POLs, RTDLY = 2ms Figure 5. Sequencing Off 3 POLs, RTDLY = 2ms
Figure 6. VM Low to KILL, UP, and EN1 Figure 7. Auto Fault Clear and Reset Waveform
UP/INIT
POL1 VOUT
POL2 VOUT
POL3 VOUT
2ms/DIV
UP/INIT
POL1 VOUT
POL2 VOUT
POL3 VOUT
5ms/DIV
VM
KILL
EN1
UP
DONE
EN1
KILL
UP

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ISL70321SEHDEMO1Z 4. PCB Layout Guidelines
4. PCB Layout Guidelines
The ISL70321SEHDEMO1Z PCB layout has been optimized for size and ease of use.
The following key features are:
• The small 2” x 1” size allows easy drop-in placement in system
• Connection posts allow for quick wire-in to circuitry
• 0402 components provide easy handling and customization.
4.1 ISL70321SEHDEMO1Z Evaluation Board
4.2 ISL70321SEHDEMO1Z Schematic
Figure 8. Top of Board Figure 9. Bottom of Board
Figure 10. ISL70321SEHDEMO1Z Schematic
GND
GND
E E E E
E
E E
E
E
TP13
R10
10K
R8 10K
TP4
TP12
10K R4
R13
10K
R7 10K
TP3
TP11
R11
10K
10K R3
R14
10K
TP8
TP2
TP10
R15
10K
TP7
TP1
TP9
VDD
EN1
EN2VM2
VCC5
VREF
EN3
EN4
KILL
GND
DONE
VM1
UP
VM3
VM4
PGTMR
INIT
TDLY
U1
ISL70321SEHVF
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
R6 10K
R16
10K
R9
10K
TP5
C2
0.47UF
10K R5
10K
R17
C3
0.22UF
TP16
TP15
0.47UF
C1
10K R2
TP6
TP14
10K R1
R12
10K
DONE
EN1
EN2
EN3
EN4
INIT
KILLPGT
TDLY
UNNAMED_1_ISL70321SEH_I 866_PIN17
UP
VCC5
VDD
VM1
VM1_IN
VM2
VM2_IN
VM3
VM3_IN
VM4
VM4_IN

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ISL70321SEHDEMO1Z 4. PCB Layout Guidelines
4.3 Bill of Materials
4.4 Board Layout
Item Qty
Reference
Designator Value
Tol
(%) Rating Type PCB Footprint Manufacturer
Manufacturer
Part Number
11U1 Intersil ISL70321SEH/PROTO
2 2 C1, C2 0.47µF 10 16V X7R SM0603 Various Generic
3 1 C3, 0.22µF 10 16V X7R SM0402 Various Generic
4 17 R1 - R17 10kΩ 1 1/16W CHIP SM0402 Various Generic
Figure 11. Top Silkscreen Figure 12. Top Layer
Figure 13. Bottom Trace Layers Figure 14. Bottom Silkscreen

ISL70321SEHDEMO1Z 5. Revision History
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
© Copyright Intersil Americas LLC 2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
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5. Revision History
Rev. Date Description
0.00 Jul 24, 2017 Initial release

ISL70321SEHDEMO1Z
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