Intersil ISL70321SEHEV Z Series User manual

Rev 0.00 Sep 2017
User’s Manual
ISL70321SEHEVxZ
User’s Manual: Evaluation Board
High Reliability

UG122 Rev.0.00 Page 2 of 15
Sep 18, 2017
UG122
Rev.0.00
Sep 18, 2017
ISL70321SEHEVxZ
Evaluation Board
USER’S MANUAL
1. Overview
The ISL70321SEH evaluation boards highlight an innovative turn-on and turn-off sequencer solution for multi-voltage
space-based applications using Point-of-Load (POL) DC/DC voltage converters. The ISL70321SEHEV1Z platform
provides a single IC 4-event evaluation platform, whereas the ISL70321SEHEV2Z provides a dual cascaded IC
8-event evaluation platform. Both evaluation boards are provided on the same PCB design, and are both available from
inventory in the desired configuration.
1.1 Key Features
• Jumper enabled for stand alone or POL evaluation
• Convenient power connection
• Done indicator
• Easy interconnectivity with other Intersil boards
1.2 Specifications
This board has been configured for the following default operating conditions:
• ISL70321SEHEV1Z for four sequenced outputs
• ISL70321SEHEV2Z for eight sequenced outputs
•V
IN = 3V to 13.2V
• Delay timer set for 2ms
• Power-good timer set for 4ms
• Jumper configured for stand-alone evaluation
1.3 Ordering Information
1.4 Related Literature
• For a full list of related documents please visit our website
•ISL70321SEH product page
Part Numbers Description
ISL70321SEHEV1Z Single sequencer configuration
ISL70321SEHEV2Z Dual cascaded sequencer configuration

UG122 Rev.0.00 Page 3 of 15
Sep 18, 2017
ISL70321SEHEVxZ 1. Overview
Figure 1. Block Diagrams
4xEN
4xVMIN
VDD
GND
KILL
UP
INIT
DONE
VCC5
ISL70321
8xEN
8xVMIN
VDD
GND
KILL
UP
INIT
DONE
VCC5
ISL70321
ISL70321SEHEV1Z (FOUR OUTPUTS) ISL70321SEHEV2Z (EIGHT OUTPUTS)
2X

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Sep 18, 2017
ISL70321SEHEVxZ 2. Functional Description
2. Functional Description
The ISL70321SEHEV1Z evaluation board provides a simple platform to demonstrate the functionality and features of
the ISL70321SEH sequencer IC. The default configuration is a standalone mode wherein the ENx outputs are fed back
to the VMx inputs so that the sequencing operation can be demonstrated. Using a combination of jumper settings, the
ISL70321SEHEV1Z can be used to address the enable inputs of multiple Intersil POL or LDO evaluation boards using
the ENx outputs to create a sequenced on and off multi-voltage rail power supply block.
A common delay timing between the sequenced ENx outputs can be adjusted by changing the TDLY resistor values.
Likewise, the power-good timer can be adjusted so that various ramp times of the enabled power supplies can be
predetermined.
2.1 Operating Range
By default, the ISL70321SEHEV1Z is configured for the operating VIN range of 3V to 13.2V. The ENx, DONE,
and KILL outputs are pulled up resistively to the VCC5 output. These outputs can be pulled to another voltage once
jumpers are removed. The sequence delay and power-good timers are set to 2ms and 4ms, respectively.
2.2 Quick Start Guide
2.2.1 Single IC Stand-Alone Operation (ISL70321SEHEV1Z)
(1) Ensure that the board is properly connected to the supply and loads prior to applying any power.
(2) Connect the input supply to VIN and GND.
(3) Signal UP high, monitor the four ENABLE outputs with an oscilloscope to see them go high in order.
(4) Signal UP low, monitor the four ENABLE outputs with an oscilloscope to see them go low in reverse order.
2.2.2 Dual IC Cascaded Stand-Alone Operation (ISL70321SEHEV2Z)
(1) Ensure that the board is properly connected to the supply and loads prior to applying any power.
(2) Connect the input supply to VIN and GND.
(3) Signal UP high, monitor the eight ENABLE outputs with oscilloscopes to see them go high in order.
(4) Signal UP low, monitor the eight ENABLE outputs with oscilloscopes to see them go low in reverse order.
2.2.3 Sequence Power Supplies
(1) Change the delay and power-good timer resistors on the board as necessary to achieve the desired timing of
sequenced events through the provided resistor positions. Take into account the rise times of the power
supplies and the VM input threshold voltage.
(2) Connect the appropriate bias supply to VDD and GND.
(3) Connect the enabling input of the POL or LDO power supplies to be sequenced to the appropriate
ISL70321SEH ENx outputs in the order of desired turn-on sequence.
(4) Connect the power supply outputs to the appropriate ISL70321SEH VMx inputs.
(5) Connect UP to the appropriate signaling input.
(6) Use oscilloscopes and DVMs to monitor signals and voltages.
(7) Turn system input power supply ON.
(8) Signal the UP input.
(9) Observe sequencing function and adjust timing and threshold voltages as desired.

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ISL70321SEHEVxZ 3. PCB Layout Guidelines
3. PCB Layout Guidelines
The ISL70321SEH PCB layout requires no special treatment other than the good design practice of placing the VDD,
VCC5, and VREF caps close to the IC body.
3.1 ISL70321SEHEV1Z Evaluation Board
Figure 2. Top Side
POPULATED FOR ISL70321SEHEV1Z
POPULATED FOR ISL70321SEHEV2Z
FOLLOWER
LEADER

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Sep 18, 2017
ISL70321SEHEVxZ 3. PCB Layout Guidelines
Figure 3. Block Diagram Showing ISL70321SEHEV1Z Enabling Three ISL7000X Regulator
Evaluation Boards (See Figures 12, 13)
ISL70003A VOUT
VIN
4xEN
4xVMIN
VDD
GND
KILL
UP
INIT
DONE
VCC5
ISL70321
ENABLE
ISL70002 VOUT
VIN
ENABLE
ISL70001A VOUT
VIN
ENABLE
12V
5V
3.3V
1.0V
GND
SIGNAL UP WITH 2V

UG122 Rev.0.00 Page 7 of 15 Sep 18, 2017 ISL70321SEHEVxZ 3. PCB Layout Guidelines
3.2 ISL70321SEHEVxZ Circuit Schematics
Figure 4. ISL70321SEHEVxZ Schematic - Leader
GND
LEADER
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
IN
IN
IN
IN
OUT IN
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
TP7
VDD
EN1
EN2VM2
VCC5
VREF
EN3
EN4
KILL
GND
DONE
VM1
UP
VM3
VM4
PGTMR
INIT
TDLY
U1
ISL70321SEHVF
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
P2
JP5
20K
R6
0.47UF
C2
J1
TP6
P1
R5
56.2K
C8
OPEN
R11
0
JP2
TP12
TP5
TP10
20K
R8
R17 10K
10K
R12
J4
20K
R2
TP4
TP11
R7
56.2K
TP9
56.2K
R1
C6
OPEN
TP3
TP13
0.47UF
C4
R9
6.81K
OPEN
C9
TP1
J3
JP3
10K R15
TP14
TP18
C1
OPEN
R19 10K
R13 10K
20K
R4
TP15
0.22UF
C5
P3
LED1
Default
R18
1K
J2
R3
56.2K
C7
OPEN
R10 10K
TP16
1.62K
R28
JP1
10K R14
TP8
TP19
OPEN
C3
TP17
JP4
R16 10K
DONE1
EN1_1
EN1_1
EN2_1
EN2_1
EN3_1
EN3_1
EN4_1
EN4_1
KILL
UNNAMED_1_ISL70321SEH_I543_PIN1
UNNAMED_1_ISL70321SEH_I543_PI N17
UNNAMED_1_ISL70321SEH_I543_PIN3
UNNAMED_1_ISL70321SEH_I543_PIN4
UNNAMED_1_ISL70321SEH_I543_PIN5
UNNAMED_1_ISL70321SEH_I543_PIN6
UNNAMED_1_ISL70321SEH_I543_PIN7
UNNAMED_1_ISL70321SEH_I543_PIN8
UNNAMED_1_ISL70321SEH_I543_PIN9
UNNAMED_1_JUMPER2_I677_IN2
UNNAMED_1_JU MPER2_I688_IN 2
UNNAMED_1_JU MPER2_I689_IN 2
UNNAMED_1_JU MPER2_I690_IN 2
UP
UP
UP_IN
VCC5
VCC5A
VDD
LEADER

UG122 Rev.0.00 Page 8 of 15 Sep 18, 2017 ISL70321SEHEVxZ 3. PCB Layout Guidelines
Figure 5. ISL70321SEHEV2Z Schematic - Follower
RELEASED BY:
DRAW N BY: DATE:
DATE:
DATE:
DATE:ENGINEER:
TITLE:
UPDATED BY:
TIM KLEMANN
09/19/2016
TIM KLEMANN
ISL70321SEH
LARRY GOUGH
EVALUATION BOARD
03/21/2017
FOLLOWER
E
E
E
E
E E
E
E
E
E
E
E
E
E
E
E
E
E
IN
IN
IN
IN
IN
IN
IN
IN
OUT
TP33
TP23
OPEN
C27
JP9
VDD
EN1
EN2VM2
VCC5
VREF
EN3
EN4
KILL
GND
DONE
VM1
UP
VM3
VM4
PGTMR
INIT
TDLY
ISL70321SEHVF
U2
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
J5
C25
OPEN
20K R25
TP30
TP34
TP22
R31 10K
JP8
0.47UF
C10
R34
10K
R24
56.2K
C22
0.22UF
P6
JP7
LED2
Default
20K R27
0.47UF
C21
P5
TP29
J8
TP28
C23
OPEN
JP6
TP36
OPEN
C26
56.2K
R26
JP10
P4
TP21
R32 10K
20K R21
TP37
R35
10K
TP27
J7
R20
56.2K
TP35
TP26
R30 10K 10K R29
C24
OPEN
20K R23
TP31
TP25
C28
OPEN
J6
P9
R33 10K
56.2K
R22
TP32
TP24
1K
R37
P8
10K
R36
DONE
DONE1
EN1_2
EN1_2
EN2_2
EN2_2
EN3_2
EN3_2
EN4_2
EN4_2
KILL
UNNAMED_2_ISL70321SEH _I31_PIN17
UNNAMED_2_ISL70321SEH _I31_PIN18
UNNAMED_2_ISL70321SEH _I31_PIN3
UNNAMED_2_ISL70321SEH _I31_PIN4
UNNAMED_2_ISL70321SEH _I31_PIN5
UNNAMED_2_ISL70321SEH _I31_PIN6
UNNAMED_2_ISL70321SEH _I31_PIN8
UNNAMED_2_ISL70321SEH _I31_PIN9
UNNAMED_2_JU MPER2_I92_IN 2
UNNAMED_2_JU MPER2_I93_IN 2
UNNAMED_2_JU MPER2_I94_IN 2
UNNAMED_2_JU MPER2_I95_IN 2
UP_IN
VCC5A
VCC5B VDD
U2 IC IS ONLY USED ON ISL70321SEHEV2Z
FOLLOWER

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ISL70321SEHEVxZ 3. PCB Layout Guidelines
3.3 Bill of Materials
Item Qty
Reference
Designator Value
Tol
(%) Rating
PCB
Footprint Manufacturer
Manufacturer
Part Number
1 2* U1, U2* - - - 18 ld Flat Pack Intersil ISL70321/PROTO
2 1 R11 0Ω - 1/10W 0603 GENERIC GENERIC
3 2 R18, R28, R37 DNP 1 1/10W 0603 GENERIC GENERIC
4 4 C2, C4, C10, C21 0.47µF 10 16V 0603 TDK C1608X7R1C474K
5 2 C5, C22 0.22µF 10 10V 0603 GENERIC GENERIC
6 12 C1, C3, C6-C9, C23-C28 DNP - 0603 GENERIC DNP
7 8 R1, R3, R5, R7, R20, R22,
R24, R26
27.4kΩ 1 1/10W 0603 GENERIC GENERIC
8 1 R9 6.81kΩ 1 1/10W 0603 GENERIC GENERIC
9 16 R10, R12-R17, R19,
R29-R36
10kΩ 1 1/10W 0603 GENERIC GENERIC
10 8 R2, R4, R6, R8, R21, R23,
R25, R27
20kΩ 1 1/10W 0603 GENERIC GENERIC
Note:* U2 only in ISL70321SEHEV2Z Dual Cascaded Evaluation Board

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ISL70321SEHEVxZ 3. PCB Layout Guidelines
3.4 Board Layout - Two Layers
Figure 6. Top Layer (Silkscreen with Top Layer)

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ISL70321SEHEVxZ 3. PCB Layout Guidelines
Figure 7. PCB – Bottom Layer (Viewed from Top)

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Sep 18, 2017
ISL70321SEHEVxZ 3. PCB Layout Guidelines
3.5 Typical Performance Curves
Unless noted: VIN = 12V, TA = +25°C
Figure 8. Off and On EN1 - EN4 Sequencing Figure 9. Up to EN1 through EN4,
RTDLY = 10kΩ = 2ms
Figure 10. Up to EN1 through EN4,
RTDLY = 100kΩ = 20ms
Figure 11. EN1 through EN4, Disabled Delay,
TDLY = VCC5
EN1 EN2
EN3 EN4
2V/DIV
2ms/DIV
EN3
EN2
EN1
EN4
2V/DIV
1ms/DIV
UP
EN3
EN2
EN1
EN4
2V/DIV
10ms/DIV
UP
EN3
EN2
EN1
2V/DIV
5µs/DIV
EN4

UG122 Rev.0.00 Page 13 of 15
Sep 18, 2017
ISL70321SEHEVxZ 3. PCB Layout Guidelines
Figure 12. Sequencing On Three POLs,
RTDLY = 2ms
Figure 13. Sequencing Off Three POLs,
RTDLY = 2ms
Figure 14. Dual Sequencer On and Off Sequence Figure 15. Dual Sequencer Handshake Signals
Unless noted: VIN = 12V, TA = +25°C (Continued)
UP/INIT
POL1 VOUT
POL2 VOUT
POL3 VOUT 1V/DIV
2ms/DIV
UP/INIT
POL1 VOUT
POL2 VOUT
POL3 VOUT
1V/DIV
5ms/DIV
2V/DIV
5ms/DIV
EN1EN2
EN3
EN4
EN5EN6EN7 EN8
5V/DIV
5ms/DIV
UP
EN1 of 2nd ISL70321
DONE1/INIT2 NODE
EN1 of 1st ISL70321
DONE of 2nd ISL70321

ISL70321SEHEVxZ 4. Revision History
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the document is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
© Copyright Intersil Americas LLC 2017. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
UG122 Rev.0.00 Page 14 of 15
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4. Revision History
Rev. Date Description
0.00 Sep 18, 2017 Initial release

ISL70321SEHEVxZ
UG122