Intersil ISLVERSALDEMO2Z User manual

Demonstration Board Manual
R34UZ0015EU0102 Rev.1.02 Page 1
Feb 7, 2024 © 2023-2024 Renesas Electronics
The ISLVERSALDEMO2Z evaluation board provides
the power management for the AMD Xilinx Space
Grade Versal ACAP AI Core VC1902 using Renesas'
Radiation Hardened Power Management devices.
The Versal ACAP system requires various supply
rails, including the core, digital, analog and DDR
memory. The ISLVERSALDEMO2Z provides all these
rails for the user to evaluate the performance against
the Versal ACAP DC and AC electrical specifications.
Power Supply Specifications
▪+12VDC ±10% (Banana Jack Connectors)
Features
▪Radiation hardened QMLV power solution by
Renesas (MIL-PRF-38535)
▪Designed to power AMD Xilinx Space Grade Versal
ACAP AI Core VC1902
▪Includes regulators for all VC1902 rails, DDR4
Memory and general +5V/+3.3V bus
▪Power Supply Sequencing up and down on all rails
Figure 1. Power Management Block Diagram
AMD Xilinx
Versal
ACAP
AI Core
ISL73847 (x1)
ISL73041 (x2)
ISL70020 (x8)
12V
5V0_SYS
VCCINT, 0.8V/100A
ISL73007 VGTYAVTT, 1.2V/3A
ISL73007 VCCO_XPIO, 1.0V-1.5V/3A
ISL73007 VCCAUXPMC, 1.5V/0.5A
ISL73007 VCCO50x, 1.8V-3.3V/3A
ISL73007 VCCPMC, 0.8V/0.5A
P
M
C
ISL73007 VGTYAVCC, 0.88V/3A
ISL70001A VCCAUX, 1.5V/6A
ISL70003A
3V3_SYS
ISL73007 VGTYAVCCAUX, 1.5V/1A
DDR4/
LPDDR4
VDD/VDDQ
VTT
VPP
ISL73007
ISL70005
ISL70001A VCC_SOC_IO, 0.8V/5A
ISL73007
ISL73007 VCCPSLP, 0.8V/1A
VCCPSFP, 0.8V/3A
VDDQ, 1.2V/3A
VTT, 0.6V/1A
VPP, 2.5V/1A
3V3_SYS
ISL73847 (x2)
ISL73041 (x4)
ISL70020 (x12)
AMD Xilinx Versal ACAP
Full Power Management
Specification
ISLVERSALDEMO2Z

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ISLVERSALDEMO2Z Demonstration Board Manual
Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Renesas Power Management Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Adjustable Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Output Voltage Monitor Test Points and Load Transient Generators . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 0.8V/100A Core Rail Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Power Sequence and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7 Power LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 12V Power Supply and Sequencing Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9 5V Circuit Breaker Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.10 All Voltage Rail Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Typical Performance Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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ISLVERSALDEMO2Z Demonstration Board Manual
1. Functional Description
1.1 Power Tree
The power tree diagram and AMD Xilinx Versal ACAP supply rail requirements table is shown below. The power
management solution is developed for the Full Power Management application of the AMD Xilinx Versal ACAP
which requires individual supplies for most of the rails and a specific power sequencing.
The ISLVERSALDEMO2Z evaluation board operates on a +12V DC power supply. Two front end DC-DC
regulators provide +5.0V and +3.3V system rails that powers all the other POL DC-DC regulators.
Important: This startup and shutdown sequence is provided as an example only. Refer to the ACAP
documentation to ensure the design satisfies its sequencing requirements.
Figure 2. Renesas Radiation Hardened Power Tree for AMD Xilinx Versal ACAP
1.8V/2.5V/3.3V
ISL73007SEH
EN VCCO
VCC_P MC
3
3
Xilinx Versal AI Core VC1902
Power Tree
+12VDC 5.0V
ISL73847SEH (x1)
ISL73041SEH (x2)
ISL70020SEH (x8)
5V0_SYS
0.88V
ISL73007SEH
4
1.5V
ISL70001ASEH
5
VCCO_500
VCCO_501
VCCO_502
VCCO_503
VCCO_HDIO
VCC_P SLP
VCCAUX
EN 3V3SYS
2
VCC_INT
VCC_RAM
0.8V/0.88V
ISL73007SEH
EN 0V8
4
3.3V
ISL70003ASEH
1
3V3_SYS
EN 5V0SYS
EN VCCO
1.0V/1.2V/1.5V
ISL73007SEH VCCO_XPIO
0.8V
ISL73007SEH
3VCC_PSFP
0.8V/0.88V
ISL73847SEH (x2)
ISL73041SEH (x4)
ISL70020SEH (x12)
4
1st
ISL70321SEH
2nd
ISL70321SEH
START
5V0_SYS
3V3_SYS
VCCO
INT
VCCAUX
GTY AVCCAUX
GTY AVTT
EN 5V0SYS
EN 3V3SYS
EN VCCO
EN 0V8
EN VCCAUX
EN GTY AVCCAUX
EN GTY AVTT
EN DDR
1
2
3
4
5
6
7
DDR 8
*DONE on the 2
nd
ISL70321 sequencer
is the FPGA POR_B signal. It is kept
low until all power supplies have
sequenced up. DONE asserts high to
complete FPGA POR.
0V8 DONE
DONE/POR_B
EN 0V8
EN 0V8
3V3_SYS
3V3_SYS
3V3_SYS
1.2V/0.6V
ISL70005SEH
VCCAUX_PMC
VCCAUX_SMON
VDDR_VDDQ
VDDR_VTT
8
1.2V
ISL73007SEH
7VGTY_AVTT
EN DDR
2.5V
ISL73007SEH
VDDR_VPP
8
EN DDR
1.5V
ISL73007SEH
5
0.88V
ISL73007SEH
5
3V3_SYS
VGTY_AVCC
VGTY_AVCCAUX
1.5V
ISL73007SEH
6
4
0.8V/0.88V
ISL70001ASEH
VCC_I/O
VCC_SOC
3V3_SYS
EN VCCO
EN 0V8
EN VCCAUX
EN VCCAUX
EN VCCAUX
EN GTY
AVCCAUX
EN GTY AVTT

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ISLVERSALDEMO2Z Demonstration Board Manual
1.2 Renesas Power Management Solution
The most prominent power supply rail for the AMD Xilinx Versal ACAP is the VCC_INT core rail which consumes
up to 100A while delivering 0.8V. This is provided by the Renesas Radiation Hardened Point of Load Regulator
that consist of: (2) ISL73847SEH PWM Controllers, (4) ISL73041SEH GaN FET Drivers, and a ISL70020SEH
40V, 65A, 3.5mΩGaN FET.
Note: On the ISLVERSALDEMO2Z a 4 phase solution is implemented to deliver 100A with a 25A/phase design.
However, the design can be revised to provide 35A/phase for 140A total by changing components to handle a
larger per phase current. See 0.8V/100A Core Rail Design for changing the design to handle 140A.
The other digital and analog rails for the Versal ACAP are provided by the ISL70001ASEH and ISL73007SEH
Integrated FET Synchronous Buck Regulators. The DDR4 memory VDDQ and VTT rails external to the Versal
ACAP is powered with the ISL70005SEH Synchronous Buck Regulator + Source/Sink LDO.
The power sequencing, which is critical for the Full Power Management operation of the AMD Xilinx Versal ACAP,
is handled by the ISL70321SEH quad sequencer. Table 2 shows the full list of Renesas Radiation Hardened
Power Management parts used in the ISLVERSALDEMO2Z.
Table 1. AMD Xilinx Versal ACAP AI Core VC1902 Power Management Specifications
Power
Sequencing Rail Voltage Rail Name Current Demand DC Tol AC Tol Renesas Solution
1
5.0V 5V0_SYS 35A ±5%
(1) ISL73847SEH +
(2) ISL73041SEH +
(8) ISL70020SEH
3.3V 3V3_SYS 3A ±3% ISL70003ASEH
2
1.8V, 2.5V or
3.3V
VCCO_500,
VCCO_501,
VCCO_502,
VCCO_503,
VCCO_HDIO
3A ±1%
+3%/-5% for
3.3V
±5%
otherwise
ISL73007SEH
1.0V to 1.5V VCCO_XPIO 3A ±1% ±5% ISL73007SEH
0.8V or 0.88V VCC_PSFP 1.5A ±1% ±17mV ISL73007SEH
3
0.8V or 0.88V VCC_SOC, VCC_IO 3.5A ±1% ±17mV ISL70001ASEH
0.8V or 0.88V VCC_PMC 0.35A ±1% ±17mV ISL73007SEH
0.8V or 0.88V VCC_PSLP 0.3A ±1% ±17mV ISL73007SEH
0.8V or 0.88V VCCINT, VCC_RAM 100A ±1% ±17mV
(2) ISL73847SEH +
(4) ISL73041SEH +
(12) ISL70020SEH
4
1.5V VCCAUX 4.2A ±1% ±2% ISL70001ASEH
1.5V VCCAUX_SMON,
VCCAUX_PMC 0.35A ±1% ±2% ISL73007SEH
0.88V VGTY_AVCC 1.7A ±2% 10mVpp ISL73007SEH
5 1.5V VGTY_AVCCAUX 0.1A ±2% 10mVpp ISL73007SEH
6 1.2V VGTY_AVTT 2.8A ±2% 10mVpp ISL73007SEH
71.2V/0.6V
DDR_VDDQ,
DDR_VTT 3A/1A ±5% ISL73005SEH
7 2.5V DDR_VPP 1A ±5% ISL73007SEH

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ISLVERSALDEMO2Z Demonstration Board Manual
1.3 Adjustable Output Voltages
The AMD Xilinx Versal ACAP specifies different operating voltage on certain digital rails; for example at different
Versal speed grades certain 0.8V rails must be operated at 0.88V. Also, the VCCO_XPIO and VCCO_50x rails
can be set for different digital logic I/O levels required by the user.
The ISLVERSALDEMO2Z includes the necessary jumpers to change the feedback resistors to set the different
output voltage.
The VCCO 50x rail can be adjusted for 1.8V, 2.5V or 3.3V. See Table 3 .
The VCCO XPIO rail can be adjusted for 1.0V, 1.2V, or 1.5V. See Table 4.
Table 2. Renesas Radiation Hardened parts used on ISLVERSALDEMO2Z
Device Name Description Used For
ISL73847SEH 12V PWM Dual Phase Controller
5V System Rail
0.8V VCC_INT Core Rail
ISL73041SEH 12V GaN Half Bridge Driver
ISL70020SEH 40V, 65A, 3.5mΩGaN FET
ISL70001ASEH 5V, 6A Integrated FET Synchronous Buck VCC SOC I/O Rail,
VCC Aux Rail
ISL70003ASEH 12V, 9A Integrated FET Synchronous Buck 3.3V System Rail
ISL73007SEH 12V, 3A Integrated FET Synchronous Buck Various Digital
and Analog Rails
ISL70005SEH 5V, 3A Synchronous Buck + 1A Source and Sink LDO DDR4 Memory Supply Rails
ISL70321SEH Quad Channel Supply Sequencer Supply Rail Sequencing and Monitoring
ISL70218SEH Dual 36V Precision Rail to Rail Output Operational Amplifier Buffer for DDR VREF
Table 3. VCCO_50x Adjustments
VOUT Jumper Status
1.8V Both Open
2.5V Jumper JP1051
3.3V Jumper JP1052
Table 4. VCCO_XPIO Adjustments
VOUT Jumper Status
1.0V Both Open
1.2V Jumper JP1101
1.5V Jumper JP1102

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ISLVERSALDEMO2Z Demonstration Board Manual
The VCC PSFP, VCC SOC I/O, VCC PMC and VCC PSLP rails can be adjusted for 0.8V or 0.88V. See Tab l e 5 .
1.4 Output Voltage Monitor Test Points and Load Transient Generators
The ISLVERSALDEMO2Z provides test points for monitoring the output voltage and terminals to apply an external
load current. Certain output rails also provide an onboard transient load generator for a step load. Table 6
summarizes output rail monitoring, test points, and load transient generator input control for the supply rails.
The transient load generator comprises a FET driver controlling a common source NFET that pulls a load resistor
to GND to provide a transient load to the supply rail. The ISL73847_VCCINT 0.8V core rail uses an
ISL71040MRTZ GaN FET driver, while all other load generators use the HIP2211FBZ half-bridge driver. In both
cases, a 0V-5V logic control signal is used to switch the transient load where 0V turns the load off, and 5V turns
the load on. Figure 3 through Figure 8 show the input connection to the transient load generator control. The load
comprises multiple parallel 2W-rated, 2512-sized resistors. The transient load generator is intended for pulse load
operation only where the frequency and duty cycle of the load do not exceed the power dissipation of the
resistors.
Table 5. VCC PSFP, VCC SOC I/O, VCC PMC and VCC PSLP Rail Adjustments
VOUT Jumper Status VCC PSFP VCC SOC I/O VCC PMC VCC PSLP
0.8V Jumper Open
JP452 JP1002 JP551 JP351
0.88V Jumper Short
Table 6. Output Rail Test Points and Transient Load Control Input Connection
ISLVERSALDEMO2Z Node
Name
Oscilloscope Test Point
(2pin jumper)
DC Test Point/External Load
Access (VOUT/GND)
Transient Load
Generator Control
ISL73847_5V0_SYS TP701
ISL70003A_3V3_SYS TP501 P501/P502
ISL73007_VCCO_50x TP1051 P1051/P1052
ISL73007_VCCO_XPIO TP1101 P1101/P1102 JP1104
ISL73007_VCC_PSFP TP451 P451/P452 JP453
ISL70001A_VCC_SOC/IO TP1001 P1001/P1002 JP1003
ISL73006_VCC_PMC TP551 P551/P552
ISL73006_VCC_PSLP TP351 P351/P352
ISL73847_VCCINT TP1 TERM1/TERM2 TP22
ISL70001A_VCCAUX TP901 P901/P902 JP902
ISL73006_VCCAUX_SMON/PMC TP951 P951/P952
ISL73007_GTY_AVCC TP251 P251/P252
ISL73006_GTY_AVCCAUX TP401 P401/P402
ISL73007_GTY_AVTT TP201 P201/P202 JP201
ISL73005_DDR_VDD TP801 P801/P802
ISL73005_DDR_VTT TP802 P803/P804
ISL73006_DDR_VPP TP851 P851/P852

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ISLVERSALDEMO2Z Demonstration Board Manual
Figure 3. ISL73007_VCCO_XPIO Load Generator Input Orientation
Figure 4. ISL73007_VCC_PSFP Load Generator Input Orientation
GND IN
GND IN

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ISLVERSALDEMO2Z Demonstration Board Manual
Figure 5. ISL70001A_VCC_SOC_IO Load Generator Input Orientation
Figure 6. ISL73847_VCC_INT Load Generator Input Orientation
GND
IN
GND
IN

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ISLVERSALDEMO2Z Demonstration Board Manual
Figure 7. ISL70001A_VCC_AUX Load Generator Input Orientation
Figure 8. ISL73007_GTY_AVTT Load Generator Input Orientation
GND
IN
GNDIN

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ISLVERSALDEMO2Z Demonstration Board Manual
1.5 0.8V/100A Core Rail Design
The 0.8V/100A core rail is delivered by the discrete design of (2) ISL73847SEH PWM Controllers, (4)
ISL73041SEH GaN FET Drivers, and (12) ISL70020SEH 40V GaN FETs. Each PWM Controller is a dual-phase
IC; therefore, the design is a 4-phase solution. Each ISL73847SEH controller operates its two phases at 180
degrees phase shift. Using an external clock with a 50% duty cycle and an inverted and non-inverted input to the
SYNC-I pins of the ISL73847SEH provides the 90 degrees phase shift needed for 4-phase operation. Each phase
delivers 25A RMS for a total 100A solution.
The external clock solution is implemented with an ISL71041MRTZ Current Mode PWM Controller. Timing is
made through the RTCT pin, which provides a square wave clock signal at the OUT pin. The inverted clock output
is generated by putting the clock signal into the ISL71040MRTZ GaN FET Driver, which offers an INB input that
provides the inverted clock signal at OUTH/OUTL. While the 2MHz clock generated by the ISL71041MRTZ works
under a nominal case, it cannot be guaranteed over full operational range. Renesas recommends using a
dedicated clock generator instead. The ISL71040MRTZ GaN FET Driver can still be used to generate the inverted
clock signal.
If the full 135A specified by the AMD Xilinx Versal ACAP specification is required, modify the design to increase
the per-phase current to 35A for a total 140A solution. Make the following changes to the ISLVERSALDEMO2Z
board:
Figure 9. Schematic of Transient Load Generator FET Drivers
Figure 10. External Synchronized Clock Generator Circuit
IN
R31
DNP
R57
0
EP
VDD
IN
INB
VSS
VDRV
VSSP
OUTL
OUTH
U7
ISL71040MRTZ
1
2
3
4 5
6
7
8
9
R32
0
C33
4.7UF
C35
0.15UF
R58
20
R34
20
C34
0.15UF
C164
4.7UF
21
TP22
12
+12V_HK
UNNAMED_111_ISL71040M_I16_PIN2
UNNAMED_111_ISL71040M_I16_PIN6
UNNAMED_111_ISL71040M_I16_PIN7
UNNAMED_111_ISL71040M_I16_PIN8
UNNAMED_111_SMRES_I22_B
UNNAMED_111_SMRES_I66_B
IN
C1112
10UF
JP1104
1 2
C1113 0.1UF
VDD
HB
HO
HS HI
LI
VSS
LO
U1102
HIP2211FBZ
1
2
3
4 5
6
7
8
+12V_HK
UNNAMED_113_H IP221011_I21_PI N3
UNNAMED_113_H IP221011_I21_PI N5
IN
OUT
OUT
C160
4.7UF
C156
OPEN
TP3
C155
OPEN
EP
VDD
IN
INB
VSS
VDRV
VSSP
OUTL
OUTH
U108
ISL71040MRTZ
1
2
3
4 5
6
7
8
9
TP2
R53
0
R26
910
C159
0.15UF
EP
VREF
VDD
OUT
GNDRTCT
CS
FB
COMP
U107
ISL71041MRTZ
1
2
3
4 5
6
7
8
9
R25
1.2K
C151
0.15UF
C153
0.15UF
C157
4.7UF
C152 10PF
R33
10
R9
11K
R47
10
TP5
R50
DNP
C154
1UF
C158
0.15UF
TP4
+12V_HK
SYNC-I
SYNC-I_2
UNNAMED_110_ISL71040M_I 70_PIN3 UNNAMED _110_ISL71040M_I70_PIN6
UNNAMED_110_ISL71040M_I 70_PIN7
UNNAMED_110_ISL71040M_I 70_PIN8UNNAMED_110_ISL71041M_I 82_PIN1
UNNAMED_110_ISL71041M_I 82_PIN4
UNNAMED_110_SMCAP_I75_B