Intersil ISLVERSALDEMO2Z User manual

Demonstration Board Manual
R34UZ0015EU0102 Rev.1.02 Page 1
Feb 7, 2024 © 2023-2024 Renesas Electronics
The ISLVERSALDEMO2Z evaluation board provides
the power management for the AMD Xilinx Space
Grade Versal ACAP AI Core VC1902 using Renesas'
Radiation Hardened Power Management devices.
The Versal ACAP system requires various supply
rails, including the core, digital, analog and DDR
memory. The ISLVERSALDEMO2Z provides all these
rails for the user to evaluate the performance against
the Versal ACAP DC and AC electrical specifications.
Power Supply Specifications
▪+12VDC ±10% (Banana Jack Connectors)
Features
▪Radiation hardened QMLV power solution by
Renesas (MIL-PRF-38535)
▪Designed to power AMD Xilinx Space Grade Versal
ACAP AI Core VC1902
▪Includes regulators for all VC1902 rails, DDR4
Memory and general +5V/+3.3V bus
▪Power Supply Sequencing up and down on all rails
Figure 1. Power Management Block Diagram
AMD Xilinx
Versal
ACAP
AI Core
ISL73847 (x1)
ISL73041 (x2)
ISL70020 (x8)
12V
5V0_SYS
VCCINT, 0.8V/100A
ISL73007 VGTYAVTT, 1.2V/3A
ISL73007 VCCO_XPIO, 1.0V-1.5V/3A
ISL73007 VCCAUXPMC, 1.5V/0.5A
ISL73007 VCCO50x, 1.8V-3.3V/3A
ISL73007 VCCPMC, 0.8V/0.5A
P
M
C
ISL73007 VGTYAVCC, 0.88V/3A
ISL70001A VCCAUX, 1.5V/6A
ISL70003A
3V3_SYS
ISL73007 VGTYAVCCAUX, 1.5V/1A
DDR4/
LPDDR4
VDD/VDDQ
VTT
VPP
ISL73007
ISL70005
ISL70001A VCC_SOC_IO, 0.8V/5A
ISL73007
ISL73007 VCCPSLP, 0.8V/1A
VCCPSFP, 0.8V/3A
VDDQ, 1.2V/3A
VTT, 0.6V/1A
VPP, 2.5V/1A
3V3_SYS
ISL73847 (x2)
ISL73041 (x4)
ISL70020 (x12)
AMD Xilinx Versal ACAP
Full Power Management
Specification
ISLVERSALDEMO2Z

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ISLVERSALDEMO2Z Demonstration Board Manual
Contents
1. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Power Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Renesas Power Management Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Adjustable Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Output Voltage Monitor Test Points and Load Transient Generators . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 0.8V/100A Core Rail Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Power Sequence and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7 Power LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.8 12V Power Supply and Sequencing Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.9 5V Circuit Breaker Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.10 All Voltage Rail Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3. Typical Performance Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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ISLVERSALDEMO2Z Demonstration Board Manual
1. Functional Description
1.1 Power Tree
The power tree diagram and AMD Xilinx Versal ACAP supply rail requirements table is shown below. The power
management solution is developed for the Full Power Management application of the AMD Xilinx Versal ACAP
which requires individual supplies for most of the rails and a specific power sequencing.
The ISLVERSALDEMO2Z evaluation board operates on a +12V DC power supply. Two front end DC-DC
regulators provide +5.0V and +3.3V system rails that powers all the other POL DC-DC regulators.
Important: This startup and shutdown sequence is provided as an example only. Refer to the ACAP
documentation to ensure the design satisfies its sequencing requirements.
Figure 2. Renesas Radiation Hardened Power Tree for AMD Xilinx Versal ACAP
1.8V/2.5V/3.3V
ISL73007SEH
EN VCCO
VCC_P MC
3
3
Xilinx Versal AI Core VC1902
Power Tree
+12VDC 5.0V
ISL73847SEH (x1)
ISL73041SEH (x2)
ISL70020SEH (x8)
5V0_SYS
0.88V
ISL73007SEH
4
1.5V
ISL70001ASEH
5
VCCO_500
VCCO_501
VCCO_502
VCCO_503
VCCO_HDIO
VCC_P SLP
VCCAUX
EN 3V3SYS
2
VCC_INT
VCC_RAM
0.8V/0.88V
ISL73007SEH
EN 0V8
4
3.3V
ISL70003ASEH
1
3V3_SYS
EN 5V0SYS
EN VCCO
1.0V/1.2V/1.5V
ISL73007SEH VCCO_XPIO
0.8V
ISL73007SEH
3VCC_PSFP
0.8V/0.88V
ISL73847SEH (x2)
ISL73041SEH (x4)
ISL70020SEH (x12)
4
1st
ISL70321SEH
2nd
ISL70321SEH
START
5V0_SYS
3V3_SYS
VCCO
INT
VCCAUX
GTY AVCCAUX
GTY AVTT
EN 5V0SYS
EN 3V3SYS
EN VCCO
EN 0V8
EN VCCAUX
EN GTY AVCCAUX
EN GTY AVTT
EN DDR
1
2
3
4
5
6
7
DDR 8
*DONE on the 2
nd
ISL70321 sequencer
is the FPGA POR_B signal. It is kept
low until all power supplies have
sequenced up. DONE asserts high to
complete FPGA POR.
0V8 DONE
DONE/POR_B
EN 0V8
EN 0V8
3V3_SYS
3V3_SYS
3V3_SYS
1.2V/0.6V
ISL70005SEH
VCCAUX_PMC
VCCAUX_SMON
VDDR_VDDQ
VDDR_VTT
8
1.2V
ISL73007SEH
7VGTY_AVTT
EN DDR
2.5V
ISL73007SEH
VDDR_VPP
8
EN DDR
1.5V
ISL73007SEH
5
0.88V
ISL73007SEH
5
3V3_SYS
VGTY_AVCC
VGTY_AVCCAUX
1.5V
ISL73007SEH
6
4
0.8V/0.88V
ISL70001ASEH
VCC_I/O
VCC_SOC
3V3_SYS
EN VCCO
EN 0V8
EN VCCAUX
EN VCCAUX
EN VCCAUX
EN GTY
AVCCAUX
EN GTY AVTT

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ISLVERSALDEMO2Z Demonstration Board Manual
1.2 Renesas Power Management Solution
The most prominent power supply rail for the AMD Xilinx Versal ACAP is the VCC_INT core rail which consumes
up to 100A while delivering 0.8V. This is provided by the Renesas Radiation Hardened Point of Load Regulator
that consist of: (2) ISL73847SEH PWM Controllers, (4) ISL73041SEH GaN FET Drivers, and a ISL70020SEH
40V, 65A, 3.5mΩGaN FET.
Note: On the ISLVERSALDEMO2Z a 4 phase solution is implemented to deliver 100A with a 25A/phase design.
However, the design can be revised to provide 35A/phase for 140A total by changing components to handle a
larger per phase current. See 0.8V/100A Core Rail Design for changing the design to handle 140A.
The other digital and analog rails for the Versal ACAP are provided by the ISL70001ASEH and ISL73007SEH
Integrated FET Synchronous Buck Regulators. The DDR4 memory VDDQ and VTT rails external to the Versal
ACAP is powered with the ISL70005SEH Synchronous Buck Regulator + Source/Sink LDO.
The power sequencing, which is critical for the Full Power Management operation of the AMD Xilinx Versal ACAP,
is handled by the ISL70321SEH quad sequencer. Table 2 shows the full list of Renesas Radiation Hardened
Power Management parts used in the ISLVERSALDEMO2Z.
Table 1. AMD Xilinx Versal ACAP AI Core VC1902 Power Management Specifications
Power
Sequencing Rail Voltage Rail Name Current Demand DC Tol AC Tol Renesas Solution
1
5.0V 5V0_SYS 35A ±5%
(1) ISL73847SEH +
(2) ISL73041SEH +
(8) ISL70020SEH
3.3V 3V3_SYS 3A ±3% ISL70003ASEH
2
1.8V, 2.5V or
3.3V
VCCO_500,
VCCO_501,
VCCO_502,
VCCO_503,
VCCO_HDIO
3A ±1%
+3%/-5% for
3.3V
±5%
otherwise
ISL73007SEH
1.0V to 1.5V VCCO_XPIO 3A ±1% ±5% ISL73007SEH
0.8V or 0.88V VCC_PSFP 1.5A ±1% ±17mV ISL73007SEH
3
0.8V or 0.88V VCC_SOC, VCC_IO 3.5A ±1% ±17mV ISL70001ASEH
0.8V or 0.88V VCC_PMC 0.35A ±1% ±17mV ISL73007SEH
0.8V or 0.88V VCC_PSLP 0.3A ±1% ±17mV ISL73007SEH
0.8V or 0.88V VCCINT, VCC_RAM 100A ±1% ±17mV
(2) ISL73847SEH +
(4) ISL73041SEH +
(12) ISL70020SEH
4
1.5V VCCAUX 4.2A ±1% ±2% ISL70001ASEH
1.5V VCCAUX_SMON,
VCCAUX_PMC 0.35A ±1% ±2% ISL73007SEH
0.88V VGTY_AVCC 1.7A ±2% 10mVpp ISL73007SEH
5 1.5V VGTY_AVCCAUX 0.1A ±2% 10mVpp ISL73007SEH
6 1.2V VGTY_AVTT 2.8A ±2% 10mVpp ISL73007SEH
71.2V/0.6V
DDR_VDDQ,
DDR_VTT 3A/1A ±5% ISL73005SEH
7 2.5V DDR_VPP 1A ±5% ISL73007SEH

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ISLVERSALDEMO2Z Demonstration Board Manual
1.3 Adjustable Output Voltages
The AMD Xilinx Versal ACAP specifies different operating voltage on certain digital rails; for example at different
Versal speed grades certain 0.8V rails must be operated at 0.88V. Also, the VCCO_XPIO and VCCO_50x rails
can be set for different digital logic I/O levels required by the user.
The ISLVERSALDEMO2Z includes the necessary jumpers to change the feedback resistors to set the different
output voltage.
The VCCO 50x rail can be adjusted for 1.8V, 2.5V or 3.3V. See Table 3 .
The VCCO XPIO rail can be adjusted for 1.0V, 1.2V, or 1.5V. See Table 4.
Table 2. Renesas Radiation Hardened parts used on ISLVERSALDEMO2Z
Device Name Description Used For
ISL73847SEH 12V PWM Dual Phase Controller
5V System Rail
0.8V VCC_INT Core Rail
ISL73041SEH 12V GaN Half Bridge Driver
ISL70020SEH 40V, 65A, 3.5mΩGaN FET
ISL70001ASEH 5V, 6A Integrated FET Synchronous Buck VCC SOC I/O Rail,
VCC Aux Rail
ISL70003ASEH 12V, 9A Integrated FET Synchronous Buck 3.3V System Rail
ISL73007SEH 12V, 3A Integrated FET Synchronous Buck Various Digital
and Analog Rails
ISL70005SEH 5V, 3A Synchronous Buck + 1A Source and Sink LDO DDR4 Memory Supply Rails
ISL70321SEH Quad Channel Supply Sequencer Supply Rail Sequencing and Monitoring
ISL70218SEH Dual 36V Precision Rail to Rail Output Operational Amplifier Buffer for DDR VREF
Table 3. VCCO_50x Adjustments
VOUT Jumper Status
1.8V Both Open
2.5V Jumper JP1051
3.3V Jumper JP1052
Table 4. VCCO_XPIO Adjustments
VOUT Jumper Status
1.0V Both Open
1.2V Jumper JP1101
1.5V Jumper JP1102

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ISLVERSALDEMO2Z Demonstration Board Manual
The VCC PSFP, VCC SOC I/O, VCC PMC and VCC PSLP rails can be adjusted for 0.8V or 0.88V. See Tab l e 5 .
1.4 Output Voltage Monitor Test Points and Load Transient Generators
The ISLVERSALDEMO2Z provides test points for monitoring the output voltage and terminals to apply an external
load current. Certain output rails also provide an onboard transient load generator for a step load. Table 6
summarizes output rail monitoring, test points, and load transient generator input control for the supply rails.
The transient load generator comprises a FET driver controlling a common source NFET that pulls a load resistor
to GND to provide a transient load to the supply rail. The ISL73847_VCCINT 0.8V core rail uses an
ISL71040MRTZ GaN FET driver, while all other load generators use the HIP2211FBZ half-bridge driver. In both
cases, a 0V-5V logic control signal is used to switch the transient load where 0V turns the load off, and 5V turns
the load on. Figure 3 through Figure 8 show the input connection to the transient load generator control. The load
comprises multiple parallel 2W-rated, 2512-sized resistors. The transient load generator is intended for pulse load
operation only where the frequency and duty cycle of the load do not exceed the power dissipation of the
resistors.
Table 5. VCC PSFP, VCC SOC I/O, VCC PMC and VCC PSLP Rail Adjustments
VOUT Jumper Status VCC PSFP VCC SOC I/O VCC PMC VCC PSLP
0.8V Jumper Open
JP452 JP1002 JP551 JP351
0.88V Jumper Short
Table 6. Output Rail Test Points and Transient Load Control Input Connection
ISLVERSALDEMO2Z Node
Name
Oscilloscope Test Point
(2pin jumper)
DC Test Point/External Load
Access (VOUT/GND)
Transient Load
Generator Control
ISL73847_5V0_SYS TP701
ISL70003A_3V3_SYS TP501 P501/P502
ISL73007_VCCO_50x TP1051 P1051/P1052
ISL73007_VCCO_XPIO TP1101 P1101/P1102 JP1104
ISL73007_VCC_PSFP TP451 P451/P452 JP453
ISL70001A_VCC_SOC/IO TP1001 P1001/P1002 JP1003
ISL73006_VCC_PMC TP551 P551/P552
ISL73006_VCC_PSLP TP351 P351/P352
ISL73847_VCCINT TP1 TERM1/TERM2 TP22
ISL70001A_VCCAUX TP901 P901/P902 JP902
ISL73006_VCCAUX_SMON/PMC TP951 P951/P952
ISL73007_GTY_AVCC TP251 P251/P252
ISL73006_GTY_AVCCAUX TP401 P401/P402
ISL73007_GTY_AVTT TP201 P201/P202 JP201
ISL73005_DDR_VDD TP801 P801/P802
ISL73005_DDR_VTT TP802 P803/P804
ISL73006_DDR_VPP TP851 P851/P852

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ISLVERSALDEMO2Z Demonstration Board Manual
Figure 3. ISL73007_VCCO_XPIO Load Generator Input Orientation
Figure 4. ISL73007_VCC_PSFP Load Generator Input Orientation
GND IN
GND IN

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ISLVERSALDEMO2Z Demonstration Board Manual
Figure 5. ISL70001A_VCC_SOC_IO Load Generator Input Orientation
Figure 6. ISL73847_VCC_INT Load Generator Input Orientation
GND
IN
GND
IN

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ISLVERSALDEMO2Z Demonstration Board Manual
Figure 7. ISL70001A_VCC_AUX Load Generator Input Orientation
Figure 8. ISL73007_GTY_AVTT Load Generator Input Orientation
GND
IN
GNDIN

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ISLVERSALDEMO2Z Demonstration Board Manual
1.5 0.8V/100A Core Rail Design
The 0.8V/100A core rail is delivered by the discrete design of (2) ISL73847SEH PWM Controllers, (4)
ISL73041SEH GaN FET Drivers, and (12) ISL70020SEH 40V GaN FETs. Each PWM Controller is a dual-phase
IC; therefore, the design is a 4-phase solution. Each ISL73847SEH controller operates its two phases at 180
degrees phase shift. Using an external clock with a 50% duty cycle and an inverted and non-inverted input to the
SYNC-I pins of the ISL73847SEH provides the 90 degrees phase shift needed for 4-phase operation. Each phase
delivers 25A RMS for a total 100A solution.
The external clock solution is implemented with an ISL71041MRTZ Current Mode PWM Controller. Timing is
made through the RTCT pin, which provides a square wave clock signal at the OUT pin. The inverted clock output
is generated by putting the clock signal into the ISL71040MRTZ GaN FET Driver, which offers an INB input that
provides the inverted clock signal at OUTH/OUTL. While the 2MHz clock generated by the ISL71041MRTZ works
under a nominal case, it cannot be guaranteed over full operational range. Renesas recommends using a
dedicated clock generator instead. The ISL71040MRTZ GaN FET Driver can still be used to generate the inverted
clock signal.
If the full 135A specified by the AMD Xilinx Versal ACAP specification is required, modify the design to increase
the per-phase current to 35A for a total 140A solution. Make the following changes to the ISLVERSALDEMO2Z
board:
Figure 9. Schematic of Transient Load Generator FET Drivers
Figure 10. External Synchronized Clock Generator Circuit
IN
R31
DNP
R57
0
EP
VDD
IN
INB
VSS
VDRV
VSSP
OUTL
OUTH
U7
ISL71040MRTZ
1
2
3
4 5
6
7
8
9
R32
0
C33
4.7UF
C35
0.15UF
R58
20
R34
20
C34
0.15UF
C164
4.7UF
21
TP22
12
+12V_HK
UNNAMED_111_ISL71040M_I16_PIN2
UNNAMED_111_ISL71040M_I16_PIN6
UNNAMED_111_ISL71040M_I16_PIN7
UNNAMED_111_ISL71040M_I16_PIN8
UNNAMED_111_SMRES_I22_B
UNNAMED_111_SMRES_I66_B
IN
C1112
10UF
JP1104
1 2
C1113 0.1UF
VDD
HB
HO
HS HI
LI
VSS
LO
U1102
HIP2211FBZ
1
2
3
4 5
6
7
8
+12V_HK
UNNAMED_113_H IP221011_I21_PI N3
UNNAMED_113_H IP221011_I21_PI N5
IN
OUT
OUT
C160
4.7UF
C156
OPEN
TP3
C155
OPEN
EP
VDD
IN
INB
VSS
VDRV
VSSP
OUTL
OUTH
U108
ISL71040MRTZ
1
2
3
4 5
6
7
8
9
TP2
R53
0
R26
910
C159
0.15UF
EP
VREF
VDD
OUT
GNDRTCT
CS
FB
COMP
U107
ISL71041MRTZ
1
2
3
4 5
6
7
8
9
R25
1.2K
C151
0.15UF
C153
0.15UF
C157
4.7UF
C152 10PF
R33
10
R9
11K
R47
10
TP5
R50
DNP
C154
1UF
C158
0.15UF
TP4
+12V_HK
SYNC-I
SYNC-I_2
UNNAMED_110_ISL71040M_I 70_PIN3 UNNAMED _110_ISL71040M_I70_PIN6
UNNAMED_110_ISL71040M_I 70_PIN7
UNNAMED_110_ISL71040M_I 70_PIN8UNNAMED_110_ISL71041M_I 82_PIN1
UNNAMED_110_ISL71041M_I 82_PIN4
UNNAMED_110_SMCAP_I75_B

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ISLVERSALDEMO2Z Demonstration Board Manual
Note: The dissipative elements in the power stage (GaN FETs and inductor) see a higher temperature rise due to
the increased load current.
1. Operation of 140A on the ISLVERSALDEMO2Z is recommended only for low duty cycle transient durations. If
the customer requires to evaluate 140A continuous operation, Renesas recommends using a separate PCB
design to accommodate more GaN FETs in parallel and increase the number of PCB layers to handle the extra
current.
2. Decrease the Rsense resistor from 2mΩdown to 1.43mΩso that a 50mV full-scale input to the
ISENSE+/ISENSE- pins of the ISL73847SEH is developed with 35A RMS of load current. The Susumu
resistors have a 3mΩavailable, so two in parallel can be used for 1.5mΩ.
3. Reduce the inductor value. The inductor used is a Coilcraft SLR1070 120nH. There is no smaller inductance
in this family. However, the Coilcraft SLC1049 offers a 75nH inductor with adequate saturation and RMS current
ratings that can be substituted. The SLC1049 recommended PCB land pattern is slightly different but can be
reasonably mounted onto the PCB board.
4. Use the additional DNP placeholders for tantalum capacitors on the 0.8V rail to add the needed capacitance,
add 8×220µF.
5. Change the slope compensation, error amp compensation, and droop compensation per the loop design
calculator. At minimum, change C_comp from 4.7nF to 3.9nF.
6. Adjust the timing circuit on ISL71041MRTZ U107 from ~1MHz to 875kHz to comply with the maximum inductor
value recommended in the loop design calculator. Change C152 from 10pF to 22pF and R9 from 11kΩto
30.9kΩ.
7. It is not necessary to change the single ISL70020SEH GaN FET on the high side and two ISL70020SEH GaN
FET on the low side per phase. The high side operates at ~16% duty cycle, and the increase in per-phase
current does not necessitate changing the FETs for evaluating 140A transient load steps.
1.6 Power Sequence and Monitoring
The two ISL70321SEH quad rail sequencers handle the power sequencing and monitor all supply rails. When a
sequence up or down is initiated, the supply rails are enabled or disabled in a sequence, shown in Figure 11.
U603, the second sequencer’s DONE pin, signifies the completion of the entire power-up sequence. As described
in the AMD Xilinx Power Estimator (XPE) design tool for the Versal ACAP, the POR_B signal for the ACAP must
be asserted low during the power-up of the PMC domains. After the PMC domains have powered up, the POR_B
signal must be asserted high to complete the Power On Reset (POR). Therefore the DONE signal of the second
sequencer can be used for the POR_B of the Versal ACAP. Access to the DONE signal is provided on TP8.
Figure 11. Using Power Sequencer DONE signal for Versal POR_B Control
DONE
IN IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
R639 DNP
R647
13.8K
R656
4.99K
R635 DNP
R638
DNP
R646
10K
VDD
EN1
EN2VM2
VCC5
VREF
EN3
EN4
KILL
GND
DONE
VM1
UP
VM3
VM4
PGTMR
INIT
TDLY
U603
ISL70321SEHF/PROTO
1
2
3
4
5
6
7
8
910
11
12
13
14
15
16
17
18
R634
DNP
R651
7.87K
JP603
1
2
3
R641 DNP
R657
4.99K
R640
DNP
R653
100K
R637 DNP
R658
4.99K
C618
0.47UF
R649
13.8K
R636
DNP
R645
10K
R652
1K
J601
C619
0.22UF
R648
10K
R644
11.5K
C617
1UF
R643
10K
R655
4.99K
R660
10K
R650
121K
R654 100K
R642
11.5K
TP8
R659
4.99K
+12V_HK
+12V_HK
+5V_PRE
CD4027B_Q1
EN_DDR
EN_GTY_AVCCAUX
EN_GTY_AVTT
EN_VCCAUX
ISL70001A_VCCAUX
ISL70003A 3V3 SYS
ISL73005_DDR_VDD
ISL73007_GTY_AVCCAUX
ISL73007_GTY_AVTT
KILLN
KILLN
PGOOD5PGOOD6 PGOOD7 PGOOD8
SEQ_DONE
UNNAMED_129_ISL70321SEH_I 29_PIN12
UNNAMED_129_ISL70321SEH_I 29_PIN17
UNNAMED_129_ISL70321SEH_I 29_PIN18
UNNAMED_129_ISL70321SEH_I 29_PIN2
UNNAMED_129_ISL70321SEH_I 29_PIN3
UNNAMED_129_ISL70321SEH_I 29_PIN4
UNNAMED_129_ISL70321SEH_I 29_PIN5
UNNAMED_129_ISL70321SEH_I 29_PIN6
UNNAMED_129_ISL70321SEH_I 29_PIN7
UNNAMED_129_ISL70321SEH_I 29_PIN8
UNNAMED_129_ISL70321SEH_I 29_PIN9
UNNAMED_129_JUMPER3_I83_IN1

R34UZ0015EU0102 Rev.1.02 Page 12
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
1.7 Power LED Indicators
LED indicators are provided for a visual detection of when certain rails have powered up. The 12V LED is always
on when +12V power is applied to the board. All other LEDs are on when the PGOOD signal for that rail pulls
high.
1.8 12V Power Supply and Sequencing Initialization
The +12VDC power supply to the ISLVERSALDEMO2Z is provided by banana jack inputs to the board. Back-to-
back PMOS FETs prevent reverse current flow back to the power supply. Mechanical switch SW601 turns power
on and off to the board.
Power sequence initialization is provided by push button switch SW602 and the CD4027B JK flip flop. Pushing the
button switch provides one pulse, which latches the JK flip flop high and low, alternatively with every push. The
main power switch SW601 also controls the RESET pin of the JK flip flop. When the power switch is thrown off,
the RESET signal triggers a power-down sequence of the two ISL70321SEH sequencers instead of an
uncontrolled shutdown of the power rails. At the same time, a large RC time constant to the gate of Q602 PMOS
delays the turn-off of the 12V supply to the board for the power-down sequence to complete.
Note: The turn-off latching of the push-button switch occasionally causes a non-sequence simultaneous shutdown
of all rails. There is no issue with this other than all rails power down simultaneously.
Figure 12. Power LED Indicator
Figure 13. Power Sequence Initialization Circuit
IN
IN
IN
IN
IN
IN
IN
IN
IN
R1157
2K
VCC_AUX_LED1
Default
12
GTY_AVTT_LED1
Default
12
R1152
2K
TR2_G
TR1_G
TR2_S
TR2_D
TR2_S
TR1_D
U1151
QS6K1FRA
1
2
3 4
5
6
R1158
2K
3V3_LED1
Default
12
R1150
2K
TR2_G
TR1_G
TR2_S
TR2_D
TR2_S
TR1_D
U1152
QS6K1FRA
1
2
3 4
5
6
TR2_G
TR1_G
TR2_S
TR2_D
TR2_S
TR1_D
U1153
QS6K1FRA
1
2
3 4
5
6
DDR_LED1
Default
12
R1156
2K
12V_LED1
Default
12
TR2_G
TR1_G
TR2_S
TR2_D
TR2_S
TR1_D
U1154
QS6K1FRA
1
2
3 4
5
6
R1154
2K
GTY_AVCCAUX_LED1
Default
12
VCC_INT_LED1
Default
12
R1151
2K
R1153
2K
5V0_LED1
Default
12
VCC0_LED1
Default
12
R1155
2K
+12V_HK
PGOOD1
PGOOD2
PGOOD3
PGOOD4
PGOOD5
PGOOD6
PGOOD7
PGOOD8
UNNAMED_131_NCH ANNEL_I16_TR1D
UNNAMED_131_NCH ANNEL_I16_TR2D
UNNAMED_131_NCHANNEL_I28_TR1D
UNNAMED_131_NCHANNEL_I28_TR2D
UNNAMED_131_NCH ANNEL_I37_TR1D
UNNAMED_131_NCH ANNEL_I37_TR2D
UNNAMED_131_NCH ANNEL_I6_TR1D
UNNAMED_131_NCH ANNEL_I6_TR2D
UNNAMED_131_SMLED_I10_B UNNAMED_131_SMLED_I12_B UNNAMED_131_SMLED_I19_B
UNNAMED_13 1_SMLE D_I1_B UNNAMED_13 1_SMLE D_I22_ B UNNAMED_13 1_SMLE D_I23_ B UNNAMED_13 1_SMLE D_I2_B UNNAMED_13 1_SMLE D_I30_ B
UNNAMED_131_SMLED_I35_B
IN
IN
IN
OUT
C610
150UF
12
C601
150UF
12
R606
1K
R601
24.9K
R604
121K
SW601A
1
2
3
C608
150UF
12
R608
100
SW601B
4
5
6
C611
1UF
C605
22UF
Q2
RESET2
K2
J2
SET2
VSS
CLOCK2
VDD
Q1
CLOCK
RESET
K1
J1
SET1
Q2
Q1
U601
CD4027B
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R605
10K
C602
150UF
1 2
C612
10UF
C606
22UF
R602
10
C609
150UF
12
BA4
575-4
C603
150UF
12
C613
0.01UF
Q602
AON6411
1
2
3
4
5
6
7
8
BA3
575-4
R603
2.67K
C607
150UF
12
SW602
@switches.spst_mts(chips):page128_i52
1
2
3
4
R607
7.87K
BA2
575-4
C604
150UF
1 2
Q601
AON6411
1
2
3
4
5
6
7
8
BA1
575-4
+12V_HK
+12V_HK
+12V_IN
CD4027B_Q1
UNNAMED_128_CD4027B_I 76_PIN12
UNNAMED_128_CD4027B_I 76_PIN13
UNNAMED_128_ETDPDT _I92_COMM
UNNAMED_128_ETDPDT _I92_NO
UNNAMED_128_PCHANNEL_I141_G1
UNNAMED_12 8_SMPOL CAP_I142_B
UNNAMED_128_SMRES_I 51_A

R34UZ0015EU0102 Rev.1.02 Page 13
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
The VCCO_LED stays on for the longest duration during a power sequence off. This happens because the
previous rail being sequenced down that the ISL70321SEH monitors is the ISL73847_VCCINT rail, which has a
very large output capacitance to slowly discharge the output voltage. Until the sensed voltage on
ISL73847_VCCINT falls below the 600mV internal reference, the sequencer does not power down the next rail,
which is driven by the EN_VCCO signal and its PGOOD3 signal is driving the VCCO_LED.
1.9 5V Circuit Breaker Protection
The ISLVERSALDEMO2Z evaluation board includes a circuit breaker to disconnect the 5V rail powering the
0.8V/100A VCC INT core rail. This provides additional protection to the VC1902 under an overcurrent condition.
The circuit breaker function is implemented with (5) ISL70061SEH NMOS load switches connected in parallel that
is triggered to shut off during an overcurrent, as shown in the Figure 5 application circuit of the ISL70061SEH
datasheet.
The ISL70218SRHM 36V Precision Operational Amplifier is configured as a comparator to detect an overcurrent
condition. The current monitoring is done on the IMON pin of the ISL73847SEH PWM Controller used for the
+12V to +5V DC-DC converter. The reference into the comparator is set by the R301/R302 resistors with 0.316V.
The IMON pin outputs a current that represents the summed sensed voltage across the ISENSE+/ISENSE- pins
in the two phases of the DC-DC regulator with a transconductance gm of 0.39uA/mV. Given Rsense=2mΩused in
the design and a termination resistor of 10kΩfor IMON, when an RMS current of ~38.6A is detected, the
comparator drives the (5) NMOS load switches off to isolate the +5V rail from biasing the power stage of the 5V to
0.8V DC-DC converter that provides bias for the VCC INT rail. As shown in the schematic below, +5V_POST goes
to the power stage of the 4-phase 0.8V/100A rail and is isolated from +5V_PRE during an overcurrent condition.
Figure 14. 5V Circuit Breaker
IN
IN
IN OUT
V+
V-
OUT
U306
ISL70218SRHF/PROTO
1
2
3
510
C314
10UF
ON GND
EP
DON
SWI
SWI
SWI
SWI
SWI
SWI
SWO
SWO
SWO
SWO
SWO
U304
ISL70061SEHF/PROTO
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
R303
1K
C303
10UF
C315
10UF
ON GND
EP
DON
SWI
SWI
SWI
SWI
SWI
SWI
SWO
SWO
SWO
SWO
SWO
U303
ISL70061SEHF/PROTO
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
R305
DNP
ON GND
EP
DON
SWI
SWI
SWI
SWI
SWI
SWI
SWO
SWO
SWO
SWO
SWO
U302
ISL70061SEHF/PROTO
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
R304 DNP
R302
642
ON GND
EP
DON
SWI
SWI
SWI
SWI
SWI
SWI
SWO
SWO
SWO
SWO
SWO
U305
ISL70061SEHF/PROTO
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
C310
10UF
C309
0.1UF
ON GND
EP
DON
SWI
SWI
SWI
SWI
SWI
SWI
SWO
SWO
SWO
SWO
SWO
U301
ISL70061SEHF/PROTO
1
2
3
4
5
6
7 8
9
10
11
12
13
14
15
R301
10K
C311
10UF
C304
10UF
C301
10UF
C312
10UF
C302
10UF
C305
10UF
C313
10UF
C306
10UF
+5V_POST+5V_PRE
IMON_2P
UNNAMED_130_ISL70061SEH_I 1_7
UNNAMED_130_ISL70061SEH_I 1_9
UNNAMED_130_ISL70218_I 5_IN
VCC_2P

R34UZ0015EU0102 Rev.1.02 Page 14
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
1.10 All Voltage Rail Monitoring
J601 40 Pin header provides a convenient access point to monitor all the DC rails generated by the Renesas
Radiation Hardened Point of Load Regulators. Figure 15 shows the pinout of the voltage rails.
Note: Only use J601 for DC voltage monitoring. Attempting to measure the rail voltages for steady state ripple or
transient load step for meeting AMD Xilinx Versal power management rail requirements is not recommended
because J601 is routed a long distance away from the output capacitors for those rails and will not provide
accurate voltages at this measurement point.
Figure 15. Voltage Rail Pinout
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
R679
0
R665
0
R690
0
R695
0
R699
0
R677
0
R663
0
R688
0
R693
0
R674
0
R666
0
R661
0
R686
0
R691
0
R673
0
R664
0
R684
0
R689
0
R672
0
R662
0
R675
0
R682
0
R687
0
R697
0
R698
0
R680
0
R685
0
R669
0
14
16
18
20
15
17
19
11
13
2
4
6
8
12
10
1
3
5
7
9
29
27
25
23
21
30
28
24
26
22
31 32
33 34
35 36
37 38
39 40
J601
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
R671
0
R678
0
R683
0
R696
0
R694
0
R670
0
R676
0
R681
0
R667
0
R692
0
R668
0
+12V_HK
+5V_PRE
ISL70001A_VCCAUX
ISL70001A_VCC_SOC_IO
ISL70003A_3V3_SYS
ISL73005_DDR_VDD
ISL73005_DDR_VTT
ISL73007_DDR_VPP
ISL73007_GTY_AVCC
ISL73007_GTY_AVCCAUX
ISL73007_GTY_AVTT
ISL73007_VCCAUX_PMC/SMON
ISL73007_VCCO_50X
ISL73007_VCCO_XPIO
ISL73007_VCC_PMC
ISL73007_VCC_PSFP
ISL73007_VCC_PSLP
ISL73847_VCCINT
KILLN
UNNAMED_129_CONN40_I99_IN1
UNNAMED_129_C ONN40_I99_I N10
UNNAMED_129_CONN40_I99_IN11UNNAMED_129_C ONN40_I99_I N12
UNNAMED_129_CONN40_I99_IN13UNNAMED_129_C ONN40_I99_I N14
UNNAMED_129_CONN40_I99_IN15UNNAMED_129_C ONN40_I99_I N16
UNNAMED_129_CONN40_I99_IN17UNNAMED_129_C ONN40_I99_I N18
UNNAMED_129_CONN40_I99_IN19
UNNAMED_129_C ONN40_I99_I N2
UNNAMED_129_C ONN40_I99_I N20
UNNAMED_129_CONN40_I99_IN21UNNAMED_129_C ONN40_I99_I N22
UNNAMED_129_CONN40_I99_IN23UNNAMED_129_C ONN40_I99_I N24
UNNAMED_129_CONN40_I99_IN25UNNAMED_129_C ONN40_I99_I N26
UNNAMED_129_CONN40_I99_IN27UNNAMED_129_C ONN40_I99_I N28
UNNAMED_129_CONN40_I99_IN29
UNNAMED_129_CONN40_I99_IN3
UNNAMED_129_C ONN40_I99_I N30
UNNAMED_129_C ONN40_I99_I N32
UNNAMED_129_CONN40_I99_IN33UNNAMED_129_C ONN40_I99_I N34
UNNAMED_129_CONN40_I99_IN35UNNAMED_129_C ONN40_I99_I N36
UNNAMED_129_CONN40_I99_IN37UNNAMED_129_C ONN40_I99_I N38
UNNAMED_129_CONN40_I99_IN39
UNNAMED_129_C ONN40_I99_I N4
UNNAMED_129_C ONN40_I99_I N40
UNNAMED_129_CONN40_I99_IN5UNNAMED_129_CONN 40_I99_IN6
UNNAMED_129_CONN40_I99_IN7UNNAMED_129_CONN 40_I99_IN8
UNNAMED_129_CONN40_I99_IN9

R34UZ0015EU0102 Rev.1.02 Page 15
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
2. Board Design
2.1 Layout Guidelines
The general layout of the ISLVERSALDEMO2Z board is shown below. In the middle right of the board is the
0.8V/100A rail for the Versal ACAP core rail. The bottom half of the board contains the digital and DDR4 supply
rails. The upper right section of the board contains the analog supply rails. Along the upper-middle and left-
middle side of the board are the regulators to generate the +5.0V and +3.3V systems rails, along with the power
sequencers and LED indicators for each supply rail.
Figure 16. ISLVERSALDEMO2Z Evaluation Board
Power And Enable Switch
+12VDC
Input
Power
Sequencers
LED
Indicators
+3.3V Bus
Voltage
GTY_AVTT
0.8V/100A
Core Rail
+5.0V/50A
Bus Voltage
VCCO_XPIO
VCCO_50x
VCC_SOC_I/O
VCC_PMC
VCC_PSLP
VCC_AUXPMC
VCC_PSFP
VCC_AUX
DDR_VDD
DDR_VTT
DDR_VPP
GTY_AUX
GTY_AVCC
0.8V/100A
Core Rail

R34UZ0015EU0102 Rev.1.02 Page 16
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
For the ISLVERSALDEMO2Z schematic diagram, bill of materials, and board layout files, download the design
files from the website.
Figure 17. ISLVERSALDEMO2Z Board Layout
ISL70321
2x Sequencers
ISL73847 + ISL73041
4 Phase
0.8V, 100A
VCCINT Core Rail
ISL70003A
3V3_SYS
ISL73847
2 Phase
5V, 50A
5V0_SYS
ISL70061
Circuit
Break
ISL73007
VCCO50x
ISL73007
VCCAUXP
MC/SMON
ISL73007
PMC
ISL73007
XPIO
ISL70001A
VCC_SOC/IO
ISL70001A
VCC_AUX
ISL73007
PSLP
ISL73007
PSFP
ISL73007
GTY_AVCC
ISL73007
GTY_AUX
ISL73007
GTY_AVTT
ISL73005
DDR
ISL73007
DDR
VPP
LED Indicators
12V BUS
Power FETs
Switches

R34UZ0015EU0102 Rev.1.02 Page 17
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
3. Typical Performance Graphs
Figure 18. Power-Up Sequencing, Ch1-8 Figure 19. Power-Down Sequencing, Ch1-8
Figure 20. Power-Up Sequencing, Ch9-16 Figure 21. Power-Down Sequencing, Ch9-16
Figure 22. ISL73847_VCCINT Rail 46A Load Step
Transient with ±17mV Compliance Window
Figure 23. ISL73007_VCCO_XPIO Rail 3A load step with
±60mV Compliance Window

R34UZ0015EU0102 Rev.1.02 Page 18
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
Figure 24. ISL73007_VCC_PSFP Rail 1.33A load step
with ±17mV Compliance Window
Figure 25. ISL70001A_VCC_SOC_IO Rail 1.6A load step
with ±17mV Compliance Window Shown
Figure 26. ISL70001A_VCC_AUX Rail 1.5A load step
with ±30mV Compliance Window Shown
Figure 27. ISL73007_VCCO_50x Rail Steady State Ripple
at 3A with ±60mV Compliance Window Shown
Figure 28. ISL73007_VCCO_XPIO Rail Steady State
Ripple at 3A with ±60mV Compliance Window Shown
Figure 29. ISL70001A_VCC_SOC_IO Rail Steady State
Ripple at 3.5A with ±17mV Compliance Window Shown

R34UZ0015EU0102 Rev.1.02 Page 19
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
Figure 30. ISL73007_VCC_PMC Rail Steady State Ripple
at 0.5A with ±17mV Compliance Window Shown
Figure 31. ISL70001A_VCC_AUX Rail Steady State
Ripple at 4.2A with ±30mV Compliance Window Shown
Figure 32. ISL73007_VCC_PSLP Rail Steady State
Ripple at 0.5A with ±17mV Compliance Window Shown
Figure 33. ISL73007_VCC_PSFP Rail Steady State
Ripple at 1.5A with ±-17mV Compliance Window Shown
Figure 34. ISL73847_VCCINT Rail Steady State Ripple at
50A with ±17mV Compliance Window Shown
Figure 35. ISL73007_VCC_AUX_SMON_PMC Rail Steady
State Ripple at 0.5A with ±30mV Compliance Window
Shown

R34UZ0015EU0102 Rev.1.02 Page 20
Feb 7, 2024
ISLVERSALDEMO2Z Demonstration Board Manual
Figure 36. ISL73007_GTY_AVCC Rail Steady State
Ripple at 1.7A with 10mVpp Compliance Window Shown
Figure 37. ISL73007_GTY_AVCC_AUX Rail Steady State
Ripple at 0.5A with 10mVpp Compliance Window Shown
Figure 38. ISL73007_GTY_AVTT Rail Steady State Ripple
at 2.8A with 10mVpp Compliance Window Shown
Figure 39. Current Sharing Accuracy of 4-Phase
ISL73847_VCCINT Rail at 20A Load
Figure 40. Current Sharing Accuracy of 4-Phase ISL73847_VCCINT Rail at 100A Load