Intertec data systems Superterm User manual

0~1-

C\i(\.

--

Super-Term

Maintenance

Manual

#11100500-00

Coytdght

1f78

. .

tatei:wc Cata

9rst~.s

CorporatiOn

All

rlgj\hJtaserved.

TABLf!OF

CONTENTS

SECTION

1:

General Description

ancUJpeclflc:atlOlls

...•..••

r

•••••

,

••••

Page1

1.1

lntrodUctlon

1.2 Generat:Specifications

1.3 Technical Specifications

SECTION

2:

lnslaltatlon and Operation

..............................

Page3

2~

1 lnstallatlon/Cable Connection

2.1.1 A.C. Line Cord

Conn~lon

2.1.2

Input/Output

(110

Cable Connection)

2.2 Operation .

2.11

Gemnt

Procedures

:tu

Ribbon Installation

2.2:3 Paper Loading·

SECTION

3:

ln1erla~ng

..............••........••..•.........•.......

Pau•

5

:u·

~rat

Information · ·

3.2 Interface-Specification$

3.2.1 RS-232C/Sell 202C Interface.::·

3.2.3 Parallel

tnferfm::e

SECTION

4~

Internal

Opetatfott<

...........•...•...••......•.•..

;

....

Page5

4.1

General

~w

4.2 Power Supply

4.2.1 RecUfief/FiHer Section

4.2.2

Regulator

section

4.2.2.t

PCB

~bly

#11310004l't

4.2.2.2

PCB

Assembly

#1131-~1-Rev.01

4.:J

AnalogPower

BOliin:I

t113()0Qi()..Q2

4.3.1

Ova'Yiew

4.3.2

Par,ler~

Drive

4.3.3

Card$t

Servo

Drive

4.3.4

Print-Wire

Solenoid

C>riVe

4.3.5

Volt•

MOl1ft'dt

4.3.6

RibtfCSft

Ori'/$,

4.3.7

pea

A$sftnbly

~ISion

History

4.3.7.1

PCB

Asserffl:)Jy #

11~

4.4 Digital

Card

PCB

A$aembly

#1132001..00

4.4.t

Overview

4.4.2 Power C>lstribution and Filtering

•">•a•_•

.-,.

·.,.

•

·•·

• •

'•-.

'"•

l'i•'

0<1

4.4.3

Mlcroprocessor'/Sy~Slii:'Sus

and Control

tbg'icf

'..

,.

4.4.4

Memory/1/0

Gatlng:60gic:·

-'"

i

~·

·'

;.

r,,

I

,.

;.c<1;4,.,4.~;~

~Y~~.@lj9..

RAM•.1'

)''

·~

..

,.,

•

,,'·

:,

...

'.

,r

..

1:'.·:

: •

~;4:6

'

system

ROM

...

' .

.·

. .

,

\ii.t4.l4•T'•

OJ)tion'DeebdiAg

L.~lc!

: •;j

.;,

·'.~'.

I

vi'

"J·

.'~,:'

4.4.8 System

1/0

4.4.9 Servo/Head Control

Logic

4.4.10 System Timers and Interrupt Control

4.4.11 Serial Interface Logjc..i

t"'

·.

:.

"

-·"

.:1.

·

·'';.

4.4.12 Current Loop Interface and Control ...

._

4.4.13 Parallel Interface

Logic

. · ·

4.4.14 PCB Assembl'y'."Revisiam.History :

:.

-

.~.4.14;1

PCB Asseroply,#1132000-01 .

'

..

,,

-:u:14.2'

'Pcs

ASsembly #1132000-02 "

4.4.14.3 PCB Assenst>ryl#1132000-02.;Rev.

01

4.4.14.4 PCB Assembly

#113209.Q-02·~~v.

02

4.'5

EPROM CARD PCB

Assemblyilf'l'1~

foplion)

4.5.1 Standard

Fi"'!IY!~~

9@~.figuration

·,

.'.·

..

· ·

4.5.2

Custom

ECO COnf,tpurations .. .

4.6 Converter

Card'·

._,1:~'.

·•

·

'..1'.'

•'

;•!·

..

-:

·

:.

4.6.1

Function

4.6.2 PCB Assembly Revision.Histor.y

..

4.6.2.1 PCB Assembly #1134000

~:;,,

.t·

·•·

:

::·:_·

..

·~4-..6;2;-2-..PCB::AssemblY·:#.H~1····

·:

::-·

·:

·

4.7 Keyboard PCB Assembly #1140000-00

· • 4.7·:1··-aeneral·Oiscussion

..

4.7.2 PCB Assembly Revision

History

4.7.2.1 PCB Asserhbly.11140000-00

4.7.2.c?

PCB Assembl.y·'#t140000-01

4.8 Printer Assembly · · ·

4.8.1 Printer Frame Assembly

#111ooep.-O()

..

4.8.2 Carriage Sub-Assembly #111100d-00

4.8:3 Print-:Heail-S\Jl>.Assemt>ly #111200o-0D

4J~:;_4..

·Printer

Cowr

Assemblyj#1-160000-00 •

4.9 Internal Cabling ·

.....

.

...

,

·.

.

...

·

..

4.9.1 Analog-to-Digital Card (long).#1150101-00

4.9.2 Analog-tcr.DJgltal Card (short)

#n50100-00

4.9.3 Converter4o-Analog · •·

4

•.

914;/.KeyJx>ard,Pable.#1150200-0Q·•

::S:~.

~~~ri~~e;,~~rd.>

#1_150300-00

5:9':7

RS-232C

1ntert.iee:

eabie

#1.150500-00.

4.9,&~

Cu.1$ent

·.L'QoP-.

lntertace'.Cable ·

4.9,.9

.ear:aHet

Interface.Cable . .

4.9.10 Power

supply

·1:i81'fless

4.9.11 D.C. Power-Distribution Harness

SECTION 5: . . . , ,

..

::

..

.

Maintenance ,

........................................

Pl,l98

22

5.1

Gefteral Maintenance Techniques . ·

5.1.1 G,eneral Maintenaooe fi!equirements • ·

5.1.2,General Ma.inten•nce Instructions.

5.1.3.General Maintenance Precautions''· ..· . .

5.2 Maintenance Levels, NeceS'sary Equipment, Spare Parts

5.2.1 Maintenance Levels

5.2.1.1 Level

1':;

5.2.1.2 Level 2

5.2.1.3

L.evel

3 '

,•

.

5.2.2, Required Tools, Equipment, and Parts

)·~a.2.~

..

~-1.

•.

'·''"

,~~.

5.2.2.2 Level 2

5.2.2.3 Level 3

5.3 Preventive-Maintenance (Level -

.1)

. . $.3.1

PIM.Philosophy

....

5.3.2

P/M

Procedures

5.3.3 Cleaning and

ln!pectlon

' . ·

(.~.::

.·

"·~

· 5.3.3.1 Printer Cover

...

~

.

..

.

5.3.3.2 Printer Assembly, .

5.3.3.3

KeyboStd'

.

~:-'""'·

•

•·

5.3.4

Lubrication

..

.

....

..

: ·

:;

C

·~·

5.3.5;1 Carriage Rails. . . ·

.··

•

5.3A:2

~rr!a~e

1

Assembly 88arinQ°s:·.....

:

..

5;3.4:3'Ccin:lagelSelt•TensiorfAssembly

..

·.

• 5.4 Corrective Maintenance

(Lev~I

-·2). j .. ,.,., ·;.

5.4.1

C/M

Philosophy · . ,.

..

5.4.2

C/M

Level - 2 Test atid Adjcistment Procedures

.!i4;a•1.

Car.rlaoe~Drjvei-Belt

.fnspection.

_5.4.?.2

P~.

l".F~

l;lri~

JnspfJCl_l.9"

..

5.4;2:3 RlbbOtl

'Drtve-

lnspeCtion··~:

..

·

..

:

5.4.2.4 Keyboard Inspection

"•

' .

'.'

f . .

5.4.2.5 Print

Quality

Inspection

···5;4:2.6·

Print

Quallty·Ad;ustment ·

5.4.2.6.1 through 5.4.2.6.9 Detailed adjustment

procedure.

~:

.

~~

-

~

~~.\;. ~~-

5.4.3 Level - 2 Module R &

~-

Proci!rcfures

5.4.3.1 Removing SuperTerm

from

Cover

•

\·;t."•;~.4.3.2

Prlnt-Hsal~•·;•

.".\'-.;:J:'.'~3

...

':

..

:i:'h·F~'i

5.4.3.3 Analog Power

Board

5.4.3.4 Digital Card

5.4.3.5 Converter Card '

~.::L;:;.c·

"'.'

··

";I

~

.

·~

..; . 5.4.3.6

PQwer

Supply

R90-.;_latOfio~

.

,:

.

~~J~

~~

'

~·:

.•

1 5.4.3.7 Keyboard

•..

•

•.

.

i;

,..,

1

· ·

,,, 5.'4.3.8 EPROM Card (Opt,IO}l) . .

'"

•

..

__

'{

\;.

5.5

Correctlv~.

Maintenance (Levei.:at

'.

· ·'.,'

5.5.1

C/M

Level - 3 Objective

·'

1<J

1'-

·

..

"

5.5.2 M$chanlcal Assembl)i:R·

&-~R

Procedl.1te ,

->··

•

·'

5;5;2.1 Carria,?e

Sel!C)·~Qtqr-AsserQblyl.

_:~

.•

.q:-

..

_.

5.5.2.2 Papef-Feed

S.t~P,per

Mqtor

.. . ,

11

.

-i

.

fll't1

~

5.5.2.3 Ribbon-Drive

Mbtor

0 • · • ' •

~

..

5.5.2.4 Paper-Feed Tractors

5.5.2.5 Carriage Drive

Belt

5.5.2.6 Paper-Feed Drive Belt

5.5.2.7 Print-Head Spring-Cable Assembly

5.5.3 Electronic Troubleshooting Procedures ·

!!'.

SECTION 6: - ·

-.

. J

'£

,.

Accessories

and

Options

...••••..•••.....•••

;

.••

,.;,:

::

•••

-Page

28

~·

·.

6.1

General Information ;

..

~.

t.

.

6.2 The Basic SuperTerm Data

Communications

Terminal

6.3 Accessories ·

6.3.1 Ribbor:i.Cartridge (6-pack) #11901()(),!lff · . .

6.3.2 Stand

(accom~tes

bottom

feed)..#11qoo,.pD

·'

6.3.3

·Operator-~

ManllaH#1100100-00 . .

··~

· ·

'.

6.3.4 Malnfenilnce.Manual #11bosoo-oo, -

'\':';\\

\

..

6.4

Options

•

,,.-

·-·

~

,,.,,.

·

6.4.1 Option Package A

6.4.2

Option.fackage

B

6.4.3 Option Package C

6.4.4 Option Package D

6.4.5

APL/

ASCII

6.4.6 1200Baud

6.4.7 1800 Baud

6.4.8 Current

loop

Interface

6.4.9 Parallel Interface

6.4.10 Data Concentration

6.4.l0.1

DTR Technique ·

,.-

,.

6.4.'10.2.CNTL

s,a

Techniqtle- ·

6.4.11 IBM 2740/41 Emulation ·: '

6.4.12 Bell System 202C Interface ·

6.4.13

Sel~ive

Add~sing

6.4.14

Non-S~~ndard

Character Set

.,.

6.4.15 Automatic· Reverse

Printing

(ARP)

6.4.16 Re-programmed Keypad

~·I

6.4.17 Re-programmed Escape Character

(Po~n)

.

6.4.18

Auto

Echo , . "

6.4.19

Here-is~SeQ.1,1ence

.·.

· ., ;

6.4.20 32 User:t=c>nt-Programmable

C_h&r,aeters

~.

-..

. .

,,.

-

SECTION 7: ·

,_._,

.';,;( ·

~·i;,

. .

(lllJ>..

Circuit Diagramsand LogicConventions . : .::':

••••••

-

.•

..

:

..

~-

.

7.1

General Information ·

·r·

! «

7.2 Signal Nomenclature .

:-

.){,

. e

\;.,

.,

7

.,3

Integrated

Circuit

,Device

Listing

Dlll.$1rams

. . .•

1.4

SuperTerm Schematic Diagrams ·

·~.

· ·

.,

) ··

7.4.1 Module Interconnection .

7.4.2 Power

SupP.IY

Rectifier/Filter

Sectien :

,,::

,

7.4.2.1

·st~~

Configuration ·· ,

7.4.2.2

Optlorial

Configurations

7.4.3 Regulator

e&id'.

. .

'.f'

·

._

· 7.4.3.1 PCB .Aasembly #1131000-01 . , .; .

..

· ., 7.4.3.2 PCB

A•l'!lt>IY

#1131000-01-REV.Q'I

'Fi

::

7.4.4 Analog Power

Board

7.4.5 Digital Card

..

.. ..

·-

,,

.

··-

- -

7.4.6 Converter Card

..

'

7.4.6.1 PCB Assembly #1134000-00'

7.4.6.2 PCB Assembly #1134000-01

··

SECTl0Nr8: · ·

)f

·"·

Appendices

•••.••........••••••.....••••.•••...•

;"';

..

;;:

J•a0~4s

-·-:

;.:-··

8.1

Appendix A: SuperTerm Parts Lil!lt : .

.:;

7

8.2 Appendix B: USASCll Code Chart .

8.3 Appendix C: IBM Correspondence/EBOD Code

Chartrfnt

· !""I

8.4

Append.i)!:«D:

Typewriter/BIT fl•rkilg Code

..

Charts

..

iiCJ.

...

1 ·

8.5 Append!x

E:_

Control/Function

1$,Y_

lnde~

..

.

...

. .

,,

..

~·..

:

8.6 Appendix F: ECO's ·

·'

· - ·

i.

.->

..

~

..

i

..

8.7 Appendix G: Addendums To Manual

8.8 lntertec Warranty Information

S_ection 1:.

.

....

.

•

~

....

:..:"'-

• •

~

t. • •

~~··~

: ' •

,,.,

' \

GENERAL DESCRIPTION AN

.,

- ·PECIFICATIONS

1.$.

· . .

•.

-

·"..'

.

·

-,

1.1

Introduction

.......

..

. .

..

t'.he

lntertec

SuperTerm D

ta

CommtJ .·cation Terminal

is a

highly

flexible,

fu11¥

.

pro

.grammable, .

data

te

minal

I

line

printer

for

use in

computer

applica

.

itons

requiring

hard-copy,

impact

printed

~~

output.

lts

"'

wid

,

~

.range

of

features were designed

to

:

ml'ake

SuperTerm easy

to

use

and

compatible

·With

.

virtual

_

l,X

"

~~Y

computer

·

system

or

ata

communications

·

netwQ

·

~

,

.

. . ., I

:~_,_~~~::::

1

.!;i;~.,

..

.

· ~·

:·.

·~

1..:-··-,.;:::~

·

...

..

·

..

FIG.

1.1

TheSuperTerm Data Comrriun.

ications

Terminal

TheSuperTerm

employ~

state-of-the

art

rni~roprocesor

technology

which

is

tiig-

hly

reliable and.:..easy

to

service

and

maintain.

Moving

parts

are few· and necessary

cleaning and

lubrication

.

may

oftef'1

.:·

be.carried

out

by

he

user

thereby

minimizing

expensive. field service

calls.

The

electronic

modules

in

_·;

.S

.

up

.erTerm were

designed -for a

long

service Iife allowi'ng the user

to

operate

the

terminal

for

extended

·

~

.:

Be

.

riods

of

time

without

any

da

.

rn~ge

or

overheafi

.

~

;

_,~·

Should

any

module

fail,

minimum

downtime

is

required

to

effect

a

repair

since

all

modules

were designed

for

easy access

d.n

_

Q&Jick

replacement.

,;·~

~

1.2 General

Specifications

't

f ..

,:

...

·-

,.

The lntertec SuperTefm may be ct.istom

configured

fer

differing

applications.

Special

options

are available

that

allow

each

terminal

to

be tailorecfJto meet

specific

· ser requirements. These

optio11.¢

~

:

.

~re

discussed

in

detail in Section

6.

The basi.c

S~p

.

erTerm

has many

standard features found

only

as.-,

.expensive

options

on

other

machines. These

featureS

·

ar:e

~

·

listed

in Table 1-1.

.......

TABLE

1-1

STANDARD

FEATURES

1:

•..

~

·

Microprocessor

Control

.

'•

• 60, 30, 15 and 10 Characters Per Second Pri.

J:it

Rate

• 128 Cl1aracter

ASCl{Set

• 7 x 7 Dot

Matrix

Impact f>ri'nting •. .

•

Cartri~ge

:

Ri

_

QPQA

. .

.';._

..

-~::

..

•

Adjustable

--

Head·

for

.P;rinting Up

to

8 Copies

• Upper and

Lower

Case ASCII Charaeters

;-

ll,

•

~

:.

·~

~

.

·'

..

.

~

,,..

.

...

. :··

'·'

·

.....

·,

. I

Page 1

•

Adjustable

Forms

Tractor:

1"

to

16"

Wi

de

•

10

C~~r~~ters/

_

i_

nch:

H?~~OFJ~~l.

~:>:

~

<.t:>"·

..<

,..,

·,_~

r:.~.

~

..

• 6

Characters/inch

: Vertical-.

.-

.

-r

~

·

.:

..:

...

:;

:

~_.

\

...

i

~

·

.::

-. '

-·

. ':\ '

• Selectric Configured Keyboard

\l'

t

.

~

N

_

~

~Y

.

Rollqver

.

,1·

,,_

•.

- ,

...

..

J".

{

'll.1•

·

v'

• 22-Key

Numeric

Pad

With

:.

Ge.ar

~

hifted

~:

PuAotion

Keys ·

··

· ·

··

·. · ·

--~

··"

·

~

-

;·

,

• Repeat Key .

_,

,

-~

:~.

:

~~.

~

,

~:-

~,'

-

~

-

<~

_

..

·>

_·-.-~<>

·

;-

~'.

.-·:·

~;.

~

• Last Character Vfs'it:)ility

°K

·

e

y

. ~_

·

;

: :.

·:

:

·-

...

·

-

-~

~:

:·

.·:··.

,.

. . .

"

~

-

~...

. ' ; . '

_.,,,

:

~

..

~

".:

'

~

...

'

~

'

!,.

• Paper Advance Key

··

.j

· :: ·

:-~

...

~

~-

~·:

~

·- .·,

;,.

:

~

.

--~

-

~

·

~

• "

I•

•L.

~

'

l'•

.

't..J.

~

.J

'

· '

• Parity Selection (odd, even·:

,:

ri

one

)

..

~:

..

. ·

...

:--

• Mode

Selectiotr

:(half

,

dupt~x

-

~

;

Ju11

·

7

d

.

~pte4C,

~

tocal)

• 1,000 Chara

ctef'Print

Buf

f

er

·:

,.

./',

/

~: :':

··

· ·

:~--<

• RS-232C I

n-terf~ce

~

'

~

:'

:·

.''.

~

.-·

·:

...

,:-·

:..

.:

.

+.

•

Text-Optimized

PrintiA§

,.

·~ ~

,.

_·

.j

..

!

..

~

...

··.

'.

·: . ;

.,

:.

·1

,:

.~

--

.

:..:

.:

·

l .

•

Auto

Line

Feed On

-

~

-

~

ri

<

a9,e

R

'

EEt~rh

::_

.

-:~·:>>~

,?

~

• PortabiUty: Self-contained, besRtop · .

-~:

·

·,

.

.-.·~.>.

..

•

Bottom

Feed

:·

~}

1:)

_--

..

·

r.~-

•

Quietizing

Packag~

-

~

t

·

~

{

:

~

..

~-

..

_

-

·

--

~

~-

-:~·~-

·,·

~ ~

.-,

:

~

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~

1:

-

~

t'

'

~

·

.•

-.,

: ; .

,..

TA~LE

t

~

2

>

.,.

..

·

USER

-

OPTION

PACKAGES

';

. . ' _ _, .

.'.':

...

.

...

~

·.

~--

P PTION ._PACKAG_E A:

l~~-"

.

'-

'

.'

' · ' • ' ,. c

~

-

~

..

•

..

Forward an

<t.;.

;

Re~erse

~

Ho

r:

izQntal; "Tabs,

··

Vertical

Tabs~

-

~

..

Keyboard

..

~

Lock

•

out

v

<

Fixed

Horizontal

10

Tabs, Top

of

form

..

~

'

(:·

·:---..

:

~--

·. ·

.

-..

:-

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JNS!AL~TION

ANQ'OPERATION

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:·?.·:·1

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,·~

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2.1

-'lf\

~alladbn/Cable

con_rieetion

lnst

~Jf

~

J

io~~f

the

SuperT~r

"·

is

quite

simple

_arid. may

be.P~

~

r~~

.by

a~y

~~er

.

...

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(.)ne

only

needs

to

. find a

su1~t:t1Jle

..

l

.

o~t1on,

(1.e.

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-

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.-

art

atmosphere free

of

high

conc;e

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t~tion~

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of

dµ·

st

and that has an

~

$cceptable

~mbi~t1~

·

fe,m

..

p·erature·

.

rang

·

~,)

connect the power

··

and

1nterf$p~

cables and

t.h~

·-

installation

is

complete. No

furthe

-~

~

~jus~f!!ent

or

..

con!1ection is necessary. Once

t~e

Sup~

r

re

.

~m

\~:

s

setuJ?,

_"

'l~

;

1s

capable

of

running

indefi-

nitely

witl'l~

fi

lY

·the peribdic preventive maintenance

discussed in Section

5.s.-

· . .

2.1.1 A.C. Line Cord

Connection

"

•.

...

•"

,.

• • J • " "

••

'°

~

~ ~

•-

~

•

~

I

4"

" '

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••

• •

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•

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• .

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The SuperTerm

is

supplied

with

a durable

3-conductor

A.C.

line

cord 9feet

(2.

74m)

in length.

All

machines are

shipped terminated

with

~

a-

:

U

~

S

{

$t~nEtpJd

·

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1115

'.

VAC.

at

15A

p~

.

y.g,

Thos~

.

mach~

.

n~s

.r.

~~~u

,

i(~.(lg~O

_.

~VAC.

must

have tti1s plug

cut

off

and·a proper

b~e

-.

~ostalled

to

meet local requirements. ··

.,

1 .

..

The

power

requirements

for

the partfc..utar>SlfperTerm

being installed

mu.st.

:

be

_

p~~FD;

l

~~~

.

~r.1d

.

the;A.C.

Une

cord properly terminated.

After

1nsunng the [POWER]

switch

is in the

"OFF"

positien,

:

Jhe

machine:

r:nay

be

plugged

into

a~

.

putlet

RrovidfQ'g

,

J

l;le

;

prgp~(.~oltage

as

specified in Sett.ion·

t

.:

3

:

~

:

,

,k

..

_-:

· . _.,

:t

. . •

".

..:

.c ·

' f

~

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\,

,.

;

,

~

;

-;

I;, - .

:;

I :

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' • ••

-

~

>;

2.1.2

Input/Output

(-110)

.

ca

le

.,

CoflnectionL.

The SuperTerm

i-ncorporates~h~

51A

.StaA ard RS-232C

interface as a standard feature. However, the cable

must

either

be purchased as

an

acc~sscii'};

.:·

·(Order

#1150500-00),

or

supplied by

the

,

user

...

··

The Intertec S1JperTerm i$

a1s

·o·

a"a1Jabl&:.

1

with

optional

Current Loop

·

(btde

r

·

#

~

11720004l0)

'

antl

il?arallel (order

# 1173000-00) interfaces.

If

the

appropriate cable is

specified at

time

of

order,

the

machine.

will

be.shfpped

with

the

cable installeq.·

~

·

If

the cable is pur-chasedrse·parately

or

i$•

tJSer

supplied;

it

must

be

connSF.t~

to

the~u(ler.Ter~

-

by

removing

the

printer

from

its

..

cover in

orc;Jer

to

plug,

rn.

,

the

interface

cable. The

proper

-:

r~mov~1

·Pf9cedure

is

=

~iscussed

in

Section 5.4.3.1. A

description

.

of

..

tJie

·i11tefface cables

and

their

connection

to

SuperTerm ·can

be

found

in

Section 4.9.6, Section 4.9.7 and

Sec~ie.n

~-~

.,

a

~

..

Assuming

that

the

i:nterface cable .,

is

inte

r

nally

con-

nected

to

the SuperTerm,

~

tbe

free ·

end.

:-·

must

be

con~

·

nected

to

a modem,

the

I/

0

f'ott

of

a

h

1

0~t

CO!Tlputer,

or

other

data

communications

line. "

the

,·-

user

mus

't

"

'"'

·

,;

..

""'t.

-(

("'fl"

.

ascertain

the

compatib

li.ty

of

the· interface he has

chosen and

the

device

to

which

it

is

to

be connected.

Specific

information

on the interfaces can·be found ih

Section 3.

The factory standard length

for

atl interfacecables

is

1O

feet (3.05m).

For

cables

of

longer lerigth, eleqtrical

noise and losses in the cable

must

be considered.

For

informatio

n feg·

arcHng

special interface cabfes, consult

your

local·

lntenec

Repres~nt~tiv

e

. .:.:-

:.~

__

,:

2.2 Operation

....

fi

"

:-;

\

i

....

'

2.2.1 General Procedures

~'

I

.1&

•

l)~._.

:\•~:

::

..

In

this

section,

no

attempt

is

made

to

g.ive an

exhau~t-

'

ive

discussion

on

the

use and\

..

.

i

of)~ration

r

..

1.?J

.the

SuperTerm

D~~

·

~

-

;

CO~f!1unicatjon

_

~>

Terr:n~q~t.

Outffried

bet

ow

are the

m9~~

bas1q

,procedures

need$'.J

to

·operate

any

SuperTerhi

~

,,

..:

For

l •.

·

campl~te

·~

9

.

E?

l

t9H~,

.

consult

a

SuperTerm

~~.r~~·,-m~o

'

i

·

~ati9

·

ns

~

r~rin'r

.

nal

Qperator's

Manual#

1106100~

~

:_,.

:-'

, ·\.

.!

.•

\

-·'·

.

..1Uh<':.

:

··

.

?t/

1C.J

;

~

·

~

· · · J:

:1

J~

_,

A.

Powering.:·On! :

"·

..

~

.-

:·~~(-

..

:.··:?

~;.

·

·"'

1.

Flip

thef

POWE

;

R]

·

~witch

-

~

.~

,q~~f~d

:

j~st

under the

right

hand side

of

the keyboard,:

to

the

"ON"

position.*

(See

FK3

[

~

~.

~

..)·. ·.

·./

('

·

:.:~

.·

N

~

6r~

j

Tb

-

~J

R

'

~~o~

.

J:

~~

q

ei!

~~~~

~Hi

illumi~ate

mom

e

ntan~y

·

cfn

tf

th

'

e

tarnag~

·

Jlf

:restore

itself

by

slewirig

slowly

to

the

true

1e f

1

~

ma

r

gin.

2.

The terminal

is

absolutely

quiet

when

not

printing.

tj"'"Ji~.li°'·,<·"·

~;!,

.

'.~~·-'td.~~:~

~:.~·

.;"'

3.

Note that all terminal conditions

are

reset

to

their

default value5.

ff

tabs'-0r margins·

have

been

set

pd~

to

th~

t~rrnJnat~ing

powered. pff, these

rT'!l;JStJ;)e,.i;~s~~·

"·l

,,.,

'J:l

. .«

..•

Ji')'..

...··.,

....

~·,·

,·

:.:;.

·7•

· ··:1°

1·.

/"

:'

r•'

,";•-.

.r,'"'

· ;

_~f

•.

*

11·

ttie' carriage

slams

i_nt_o

.the end-stop during

power-on, Tum the-maChine OFF 1MMEDIATELY and

call your service representative. .

:1

B. Powering-Off:..

,.,

.

..

. .

-.I

..

' ·. "

1

~

i:ne,termip~I

f:nay

b~.'power~

off

at any time with-

•

QµtJ~I"

~ff~,c~;'.,ttc?w~yer.~

.ttJ.~re

is

np

han:n

done by

1¥~\'?Q.

!1.Powered

o~,,f~[~X~~nded

periods.

2.

wtle'n

'1ett

power9d-ori,

...

the

terminal will retain any

p~grammed

settin~s

indefinitely.

3.

To power off, merely flip the [POWER] switch

to

the "OFF'' position. (See FIG. 2.1.).

C.

ON·LINE OPERATION:

In

order

to

allowthe terminal

to

communicate with a local storage unit

or

the

central computer

syst_em,

theterminal must

be

in the

"ON-LINE" mode.

.,

'·

·~

To go "ON-LINE":

,

~

. Insure

m.at

_the

[LOCAL] switch, (FIG.

2.1

.) is not

·

.·

·depressed· ("OFF").1

1f

the switch is depressed,

·

:.·.,Qe_p.~~

t~e

swi~C?h

aga!rf

an~;tit

;will return

to

the

..

·uP..

C'OFF?)

pos1t1on

and thereby place the

;' ''lermil'lal

11

0N-LINE'\ ..

'~2;~AnY·f~ndibh

or

control keys may now

be

depressed fo specifically configure the terminal

to

be

compatible with the host

syst.ern.

NOTE:

Speed

·-selection'must

be

made In local mode.

3.

When the terminal senses the carrier signal from

the host-system, the[READY] -indicator will illum-

inate, signaling the operator that the terminal is

ready

to

communicate.

D

•.

LOCAL·OPERATION:.This feature is used when

it

is

necessary

to

set up functions, program operations,

.

feed

paper,.

ortype material not

to

be

transmitted

to

the

hos~

system.

To

go "LOCAL":

1. Depress the [LOCAL] switCh, FIG. 2.1) until

it

stays in the detent position ("ON"). The [

READY]

indicator should illuminate.

2.

The

Terminal may now .operate in LOCAL.

. i . . , ·

...

,

::

...

-~,·

.

~-t

'

2..2.2

..

:

R•b~fl

lr.astalla~iQn

.

..

. . . .

..

, ,

..

The·

Sqp~rT~rm·

printer

_µ~es

~-lnterteq•s'"own'.

snap-in

ril:>~.n"

cartr~dge,

(Seec

FIG

...

~;2).,

.,w.hict,I.·

.provides

approxim~t~~y

..

three.qu~ers

ota

miUion tiigh quality

characters~

per cartridge. It may be quickly and easily

changed and the user's hand

need

never touch tbe rib-

bon. Outlineq below is the simple procedure followed

rhe,~

.insta11~~9-~or,;t~1.af

!~R:a

-~~~~on

~.~r1a~e.

-

...

·•.

"'.

.

~

..

,.

.

·.

. .

(.':;

•.

.

...

.

·.

'

~

...

":"

..

•

.·

..

·.

' .. . .,

::

1:

Remove

the

tertni11at·~~ace~s

co~~r_

wt)i.ct)

·protects

the carriage

area.

·· · · ·

~

· ·

··

·

:.:,_

\t

. ,

..

··:.

2.

Insure that the

expo&.eQ

rib6on~in

the

new

cartridge

is taut by winding the small post on the upper right

side

of

the

cartritlge~

Ulu$trated in FIG. 2.2. (If

ribbo~

clip has

been

sprung outward, pinch

cartridg~

clips inward.) · .

:,f!J'\ii'

'

~-Thread

the ribbon around the print-head and.place

the ribbon cartridge in the

..

cartridge:Jlolder, gently

pressing downward until It snap& into plactt,•A brass

post on either side of the forward.

edgE:t

:

of

the

carriage will insert into holes in

thE;t.

bottol"Q

of

the

ribbon cartridge holding

it

rigidly in

p,lace.

A

ribbo~

·

is shown being installed in FIG. 2.3:

·,

RIBBON REMOVAL

·-

\.

1.

Remove

the terminal's access cqver which protects

-the cartridge

area.

''.

·.,

..

'"'>~

"

~

-

2.

Gently press downward on the two tabs located on

eitherside of the ribbon cartridge (FIG. 2.3) allowing

the cartridge

to

pop up slightly. '

3.

Grasp the cartridge, removing

it

from the two brass

posts,

and

lift

it

away

from the carriage. A new rib-

bon

may

now

be

installed

and

the access

~ertA.

replaced. .

~.::

,

~;

·

2.2.3.Paper Loading

The

SuperTerm printer is capable

of

feedi~g

paper in

two modes: top feed and bottom feed. ·

When

top-feeding, the paper is

brougnfin

'from the

rear

of the machine

and

inserted behind the platen,.,

much like

an

ordinary typewriter. When ¢ontinuing to

·push

the paperthrough,

it

will thread·its way under the

platen and exit in front of the platen.

\The

paper is then

pulled forward and up around the platen and then

placed in the forms tractors maintaining alignment

between the paperholesand the tractor sprockets.

The~

tractors

are

then closed and adjusted

to

keep

the paper

taut and against the platen. There is a clutch lever on

the outer side

of

each

tractor which allows the tractors

to

be

positioned

as

needed

and then locked into place.

When

this lever is in the "UP" position, the tractors

are

locked: When in the "DOWN" position, the tractors

are

free

to

move horizontally. Figure 2.4 shows a

top-feet-~

machine.

~

When

bottom feeding,

it

is necessary that the

SuperTerm

be

in~talled

on a special-table-or stand with

clearaccess to thebottom feed slot in the printer cover

(lntertec's optional roll-a-round stand #

119030o-Oo

is

an

excellent choice).

ta-

When

using bottom-feed, the paper is fed through both

aslot in the cover and aslot in the bottom

c.>f

the printer

chassis. The paper isthen pulled up and

fed

behind the

small guide rod just under the platen, ·up.,past the

platen, and is then placed in the forms tractors and

adjusted as noted above. Figure 2.5 shows a machine

being bottom-fed. . - _

···

,

~

IMPORTANT

NOTE:

All paper loading should bedone with the

carriage at the true left margin. ..

,.,_

.

~\'.('"i'

. ·:"J

.:

·

.•.

Bottom feeding will yield best results when:opei'ating

with high volume throughpur·using fanfold-paper.

.

·-::.

~

-~

Page4

·•

'·

i .

Section

3

I,

.,

"

::;,

r

:·•INTERFACING

·~

'!'"'':;

..

~.

t

~;··

..

·::-:

3.1 General

lnfonnation

The three intef.'faces available

for

SuperTerm enable

if

to

becompat1ble

with

virtually any data processing

or

data

cornmunicatioos system. All interfaces are

compatitih!~witli'currerit

industry

standardsignal levels.

. This sectibh. :details all ' interface specifications. A

~echnical

discussion

on,.

the

interface

circuitry

is con-

tained

in

Section 4.4. ·

•wow

..

•-·•••

•

3.2

lnterfa~

S~ifications

3.2.1 RS-232C Interface/Bell 202C Interface: The

..

Electronic fndustries"Association (EIA) has released an·

·"""RS-232C Sl?ecification which details the requirements

for

a standard.interface between data communications

equipment and data processing equipment. RS-232C

specifies

the

type and the number

of

conductors

to

be

used as well as

the

voltage levels

to

be used. lntertec's

SuperTerm employs

this

specification

for

its

standard

interface... ,

~!.

--r~

Bell

S~tem

202C interface· is an

option

(#1176655-00) on

the

SuperTerm.

It

is

covered· here

because

it

uses the same line receivers/drivers

but

with

a different

timing

setup

for

communications.

Machineswhich have

this

option

installed may operate

using

only

the,RS-232C interface

if

the

202C feature is

f!lll\deselected. The interface cables are identical.

Table

3-1

outlines

the

signal names and pin connect-

ions

for

the.RS-232C/Bell 202C interface.

.

~

. Table3-1

RS-232C/BELL 202C INTERFACING

0

.,

·\

e"'~

G>

r-..

i!

....

c:

E

....

.,, 0

.,,

·-

(/)

ci

.

i~,.

QI()(.)

z

~~-'

c._

l(l

!:!:!.:Z"

~~~

iii.

I

O::z•

·J~8!l'

•<;f .

C:'

a:iw_

c:s~~-

""'.E'w

Cl

owa.: ·w-$.o·

(.)

.....

(.)

:.:::

0

Ill

c;;

-"

2 BA

..

103 4 Transmitted Data /&3

3 BB 104 1 Received Data

'"~

4·

CA

105

5 Request

to

Send

/IP~

5

CB

106 3 Clear

to

Send /tJ{>

7

'.

AB 102 7 Slgnal Ground /()

z_

8 CF

109

2 Rec'd Line Signal Detector

It'!

11

·scA/SA

120

8 :Secondary Request to Send

12

..

~SCF/SB.

122 6 Secondary Rec'd Line Signal

.,,

....

' ·eetector

3L""

·CD

108.2 9 Data Terminal Ready '0

8/A.

•There

is

a discrepancy between

RS-232C

and

Standard assignments on a Bell System

202

modem; I.e.,

202-name

202Pln#

RS232name RS232Pln#

SA

11

'

SCA

19

SB

12

SCF

12

We

have

chosen

to

use

RS232

signal names and a

plnlmlii~ment

for·scA/SA

In

accordance with

Bell:~~-

~odems~

" "

•·

.

.•••

,

....

,.\

"f"

. t

....

:.;:..

t,.~

.....

....

••

,r-,..1 ;

1/

i r .

3.2.2 Current Loop Interface

···:··t·

•.:~~

~

r.

·

~

.

;~

;"'

i .

;·

·:

1 .::

~·

...

~··:.~

~-,i~

:~~,1

'···

· NOT

Y.:e'r

A'VAil.ABLE, ,

..

,~,_)

Thismaterial

will

be

diS$emin~tea

in

the

f6¥tir<

of

a technical bulletin.

For

your

denveritens~f'

·

enter

the

bullet

in numberbelow

for

future reference.

,,

TECHNICAL;BJLGET1N#::.

;:~

.\·

..

:.·;::;

:.·~

-

..

;···

.:

.').

.:

•···

!:

·•1.;~

• ,

....

,,\r

- - I

•·

~1·

3.2.3 Parallel Interface

..

· · ' · "

~

··

NOTYETAVAILABLE

.

.'C···;::-

..

"

\"

:-.

·;

' .

~

1 .

.•

...

' •

~

••.

' , •

..

......

••

This material

will

b~

dJsserni/l~ted;

ir('.th~

·~oi-t;r(df

,a

technical

bulletin:

Fo~.y0i,ir:

cojiy~nf~ce,

~n..t~r':

the

bulletin

numberbelow

for

future

·referenc~.

TECHNICAL BULLETIN#: :

.'

. '

..

-

..

·;

'.(

. . '

.\

....

-~.

.·

....

i r

Section

4

·:~.-

.

.,

.

~-

-

.•

...

•f

,_,

INTERNAL

OPERATION

"'j

4.1

General Overview

"'

lntertec's SuperTerm Data Communications

Te.r.minal

is a state-of-the-art

d~~ign

utilizing·· !he. hi,ghly

acclaimed and field proven 8080 ·mlcrocomputer

system. This 8080system

isthehearfoftheSupe(rerm,

controlling

all

functions

and data manjpulation. Figure

4-1

shows a basic

block

diagram

of

_th~

51.lPf?rt'~rpt~'

{'

MECHANICAi.

SYSTEM

(Printe1

Assembly)

'

~

..

'-!t

!.:·

....

r--"'-'---"'"--t'

".

·•

POWER

DIGITAL

CARD

(8080

System)

.

ANALOG

i.-.--~

:;>

1

~fR

BQtRQ,

,·

S,U!'l'\-Y

·

...__

__

__.

1,

-

..

'·

l

··~-..··'

;;

·.

K~SOARO:

,.;."

:-f

;:1

,

1

.·

~

'.

:~

·;>.,"

•

,..

.

1.'f'

I

FIG.

4-1

SuperTerm

Block

Diagram

Each

of

the

blocks.

in

the above

diag~am

w'J.tfbe~t1roken

down and

·disct.iss~d

·in

ctEitail

~rf:th•s

sedtioh-. ·While

some

particular

(fircutts may

b~fsHowri.

fi:ft

iltustratioi'f,

complete sct\Elniatics·

are

a:vaU~olEf'lli

··sedtlon 7.

··~

·~

··

·

'1

..

' • :

:'

:·r-

•.;~"

·~

,1

"r!

:o:~

·...,

''.'~(

•

,•7

~·,~

q',·,·

...

, ' .

·~

~~.

"~

...

•

4.2 Power Sll'pplY ·

·i

~-

.,

'4·

••

:"··

•..

:::

-'

..

•·

..

·•

The

Sup~rTerm.

po~~~

1

suppJy

f99.!J!at~s

a1T.~~h~ges

~a·nd

is

of

conventional linear design empfoying solid-state

voltage regulators-. ·

...

- -

~·

·-

-- ·- ... · -

..

·

..

·

..

For:

...

p_µrp.o.ses

...

oC~btr&rui

3

~ide.6tthealiQn_

-~od.

err9r

red!)ction.,, a

.s!arJd.~r.d

colqt

cop~

.i.~.-1;1.~~

.W

Sup~,rT,erm.

Thfs1 color·cotle

ts

·1tsted·1h'iabfe

~1.

1

···

.,

~

· · •

'·

·

•

·:;

:~~;·-'

'9~>~

'•,

~I

~'·•

~

............

·

~-

-

.

····

..

:·_·

-·

....

S:tl

perTerm

.....

-_

.....

-·.

·

:=-

·

,..--,,

,.,

..

.

~

-

~~-

POWER

bi'S

.TR

f'

BUTION

COLOR CODE

''

,

..

_r

;

__

.,., •

~

•

:::.:

~~

•·

' .

~;

" r

.,..

'"·

•-•

-.;

'',

; -

\1-"

~'f'

""'·

..-t

~

.....

.

__

+.

-s

·.

voc

\:

___

..

,:.~~

:~

.

·-

· ·

·".'.~

..

~

Logic Ground

·:

+ ·

12VDC

\:

±12.

v.

R.etu

tti

.

~.:~

-

..

1

-12

.\

lDC

.

+

~

48

:-

VOC

.

+i

48

V.

Rett.

i

rll'

...

..

+,

24VOe

. ·

;·

+

..

24

V..

__

Return "

"».

""

..

i..

..

.

..

...

~

24

V.DC

.--

..

_.,..

...

P-

.•

•

Orange

Black

Purple

Gray

Blue

Red

White

Green

Brown

Yellow

..

· - ·

";

.

--

·

..

-·

.

--

~

Table

4-1

.

. ) . . \

,.

.·

The power supply is divided

into

two

sections:

the

rectifier/filter

section and the regulator section.

"

4.2.1 Rec

·"

fie·

r/Filter

Section

·.

\,

..

~,

-

The_

rectifier/

f

ilter

section of the power

supply

steps

q!?wn

th

e

A.e.

line voltage

to

levels required

for

the

S-

~

1perTerm.

The A.C. line fuse is located in

the

"hot"

sj

de

of

th

.e

po

_

1ertransformer"primary

circuit.

The three

(3) s99ondaries

of

the powe.r transformerare connected

to

three (3) encapsulated bridge type rectifiers

mounted

to

the

.chassis as shown

in

figure 4-2.

_

flG.

4-2 _SuperTerm

~owerSupply

The

output

s

of

the bridge rectifiers go

to

a bank

of

filter

cap~c

i

t~rs

~ou~ted

~n

the

ce~ter

~

(t

he

power supply

section

of

the·chassis. These·

filte

r capacitors remove

any ·

.A.C

. component

fr<?m

the rectified voltages and

provide.·

a nea

r.

pure D.C.

input

to

·thevo-ltageregu:ators.

A

com

'plete schematic of

.t

hi

s.-section .of:the power

supply

.

is

available in Section

7

~

6.2.

1•

;.

: \ •

...

4.2.•2 Regulator Section . : · .

4.2.2.1 Regul

ator

PCB

..

,Assembly

#11'31000-01

Th

is.

~egul

~

tor

:

~

card

was used

-·

in

··

~he

,

~rly

SuperTerm

terminals. ·It

..

,s

n~

.longer ..beihg produced but is

included

to

aid··in

troub

lesho

oti

ng

early rriachin.es.

T~~

regul.

ator

~rd

c~

n

tai~~

:·

t

~

he

.

~

.i

r

9

ui

t

ry

~9r

a + s

voe

.

regulato~

~nd

.

a

·_

± _1·

~

YDC

regu_l.

C:l

to

r.

·These are·the

~nly

regula ed

··

voltages· 1h the

Su

p

erT~

r

m.

+"

24

VDC and

tt:~

.

~c

p~s~

}~r

Oug

tj

~

t

he

r

eg

~~ator

~rd

but

Only

tor

•

s;·

...t•

,. ,, .

~

..

•,

...

. •

..

.(

. 1

':!

~

·.}

l3

l 2

,

-~

:

"

r---G

1_0

__..

1 G

....

o

_..-..........ai:..i-.:o.-.....;,T;...

3

.....,.

,..

..

t;.:.;;,;

Hi

'

;..._:.

T2~

,

iii..

'

....:,T

~

t

.

.....,:T~

5

·

~

:;....

·

_.,.

..

\

"'

\

0

FIGURE 4-3 -

Figure 4-3 shows the layout

of

the card and the com-

ponent locations. This view is taken from the

component side

of

the card.

The + 5

voe

regulator

circuit

receives +13 VDe,

unregulated, and using a series pass transistor (01)

and a + 5 V. regulator (Z1),

outputs

+

5.

yoe

(+

250

mv.) at T4. 01

is

used

to

carry the

outpu

.:

l,qad

.:

cu

"lt

white

Z1

monitors

the

output

voltage at terminal T4.

L1

controls the base bias current on 01 · d he.reby

regulates the

output

voltage. 01,

02

and

03

pr

ovide

transient protection

for

01 and

Z1

. . _.

C1

and

C2

provide bypassing and

R1,

R2

and

R3

set up

the base bias on 01 . The

output

of the + 5

VOC

regula-

tor

circuit

is taken across terminals

T4

and

TS.

CAUTION

T5

is logicground and should NEVER be connected

to

earth ground (Chassis)! Erratic operation

of

the

terminal may result due

to

hig·h

levels o.f electrical

noise on Earth ground.

The +

12

VDC regulator

circuit

uses a tracking design

such

that+

12

Vis

always

within

a few

mil!ivolts

of

the

-12 V line. The

circuit

is configured such that the -12 V

regulator receives -24 VDC, unregulated, from the

rectifier

/filter

section and using a - 12 V reg,ulator (Z3),

outputs -

12

voe(+ 600 mvG) at T1. . - .

.'

. .

...

The + 12

voe

regulator receives +

24

V

OC

,

,.

unrc

::J

...1-

lated, from the

rectifier/filter

section and using

a+

5V.

regulator (Z2),

with

its

ground reference input floating

above ground due

to

02

,

outputs

+ 12V. (+ 600

mv.)

at

T3.

RS

and

R6

form a precision voltage

divider

~

and

develop a tracking-error voltage on the base

of

03.

03

is a

simple

error ampI

ifier

used

to

control 02.

Transistor

02

is used

to

control the floating.reference

input on

Z2

. If the 12V. output starts

to

drop,

03

conducts more heavily pulling

02

toward

cu~-off.

Z2's

reference is forced

to

a higher potential ,causing the

regulator

output

to

rise back toward 12V. If the +12V.

output starts

to

rise, exactly the opposite

r~C?tion

occurs. If the absolute·value

of

the + 12 and

_·

...

12v.

outputs

are equal, t

he

voltage on the base

of

03

.-

is

equal

to

zero (OV.).

04,

05,

06

and

07

provide transient protection

to

Z1

and

Z2G

e3,

C4, C6 and

e1

proyide bypassing while·

CS

is used

to

prevent oscillation in the tracking ciroui

t-

.:

R4

is.

simply

for

biasing.

"

'(Yr

·~·.,:

. :

Outputs

for

the +

12

voe

and -12

VDC

regula

·cpr

crrs

uit

are

take

n

~

from T3 and

T1

respectively

with

referen

c-e

to

T2 .

~)

_

• • ' I-:.'

,,

,.

..

·

Page

·6·

~

·

-·

-'-

+

24,VDC

comes onto.the.card from the rectifier'/fllter.

~tion,

is fused by

F2

and is output at

TS.

-24

VOC..comes:

onto~tf:le

..

card from the rectifier/filter

. section, is

fosec:r

by

F3'-·ahd

is output at

T1

o.

;

·~utputsJor

·+

24

vec

-anu-24

voe

are

taken from

TS

:

and

TtO.

:respectively,

_with

reference to

T9.

+48

voe

comes

o"nto

the card from the rectifier/filter

sectionds

fused by:F4, and is output at

T6.

Output for +

48"VDC

is taken from

T6

with reference to

T7.

..

-~

NOTE:

None of the outputs from the regulator

card

have

common references except for

±

24

v:

return

an.d

±12

v.

return.

""4.2.2.2 Regulator PCB

Assembly

#1131000-01-Rev.

01

This board differs from the previous board in that

it

does not contain a tracking regulator circuit

for

+12

voe.

·

Instead ofthe t.racking circuit, this board uses

an

inde-

pendent+

12V. regulator for Z2.

02

and

03

have

been

-cl~

as'"have

R4,

R5,

R6

and

C5.

·

"·

...

:

:~.~:

r·.,..~

·.~

A jumper

':has

been

added from the collector to the

emitter pads

of

the former

02

location.

The revised board is shown from thecomponent side in

Figure 4-4. ·

flllll

4.3

Analog

Power Board #1130000-02 ·

4.3.1 Overview

The Analog Power Board receives commands from the

Digital card; provides the necessary digital-to-analog

(D/

A)

conversion, and drivesall moving components of

/ilil!,the

printer assembly. It mounts on the bottom of the

printer

chas~is

as

shown in Figure 4-5.

Figure4-6 shows a block diagram of the Analog Power

Board with interface lines to the Digital

Card

and the

Printer Assembly. Complete schematics of the Analog

Power Board

are

available in Section 7.6.4.

t911n

the remainder of Section 4.3, each of the five

(5)

·

ci~its

shown on the block diagram will

be

broken

dc~

...

-1

and.Gf'Scussed

in detail.

:

.:-ni,·

·· :

4.3.2

Papar

Feed

Drive

The··

Paper

Feed

Drive··

circuitry receives two

(2)-::

...,incoming signals from the Digital card

and

provides

precise paper movements and positioning accuracy to

within 1/48" (0.529 mm).

The

Paper

Feed

Drive circuitry consists of two (2)

identical constant-current, bipolar amplifiers with

negativ_!!

feedb~ck

closed-loop cor:itrol.

The

Paper

Feed

..-motor

ts

a

2!

stepper motor with each phase being

driver( by one of the two constant current amplifiers.

· Figure

4:.7

shows a simplified schematic of one phase.

With no incoming command from the Digital Card, the

Paper

Feed

(P.F.) Drive continuously sources current

through the

P.

F. stepper motor. (The

P.

F. stepper

~motor.ds.-located

on

the right end-plate of the Printer

Assembly

as

shown in Figure 4-8). This steady-state

CUf'l'.'~'b

~.fQl!gt:l-

the motor is termed its "holding

curr~n~!\-:'typical

P.F.

hoJc:$lng

current in the

Sup~rTerm

is 200

ma.

0

Suoerterm

d.c.

OOWtf'

FIGURE

4-4

....

"

T5

Regulator

PCB

Assembly

#1131000-01-REV.

01

' )

......

~

.:.,.:

...

FIGURE4-5

>I

~

..

·

.~-.~·~··

';~

~;

.-·- ·

1

~r

~;

/'·

..

'.k~

..........

-.

A stepper motor with a steady

DC

currentdloWfh..{;f in

each

ofits

phases will not turn

and

is said to

be

in

"detent". Forastepper motorto turn, one of

its

phases

must ·transition, changing the magnetic field. The

steppermotorwill then rotate until the magnetic fields

are

agai.n

aligned. This constitutes one "step" and, in

SuperTerm, results in the advancement

of

the forms

tractors by 1/48" (0.529 mm). The transition pulse

amplitude is

termed·

the "operating current" and is

typically 2 amps.

...

~c.

~

...

,.

NOTE:

The

ceropenents

being!eferen~d

.in

..

,;

·

this

diSCl:JS$.ion

111~Y

b~jfo~md

jn"'either .

1:>.'

,'

Figure

4-7

orthe :;chernat1cs

in

s~t.•o!'l,7.fS.4.,::'.

-"'"

...

-..

-

:=.fl:.~~·;

~i

·~

•.

···"

...

,;j·:

.........

;.

Assuming::ste~dy-state

conditior.is,·the

lnvertimg·

input·

of the OP-AMP

(ZS)

seesreither~~

200m'l'.

or·

;.20Qmv.

·

depending

on

the status- ot:the; digital ·input., 'This

voltage is set up by

R13,

R14

and a resistor located in

pull-up package Z6(10). This steady-statewoltage

.on'·

the input mode

of··

ZS

is ourfconttol loop:·reference

voltage, V

REF•

The..Polarity

of

V

,REF

Js-d~t~n;nmed

Qy;·

the

sta.t._us

of

th~digit~f

;!_n,E_~t

l_ine,.

lf_.the

9iqital

:ll'lpu.

qs_

.'

HIGH,

y.

REF·

w.ill

be

+~fP~;,)f

Jhe

dl:g1tal

lnP':!t

1$

LOW,

V

REF

will_.be.~200r:nv

.....

· , ._ r . • ,

,.

.·.·

·

Since OP-AMP

(ZS}

is~o'!ng

'C?P1!n:icio.p

with.

eXtreme-

ly highgain,

i&.

satf.ir:ates..;.~Qd

~qur~e§J'.l~~

ourr:ent

for

01

O

if

positiv~y9r

q11.

;:.11

neg~~1ye.,r11

..

~

•.

SjitLtrat~s.

positiveand in tum drives 010 into saturation,

01~

WJIL

Pag(f].

7t.

·'·

·

~

...

..

!·

·,

.·

til'

••

·:

~

••

+av··;.,·

•

.:.

-24v

+48v

RET.

---------.

:!:24

..._

__

FROM--PO-WE_R

_su_PP-LY

_

__.~

+24v

RET.

+~.0---------1-1-----.

1

'~".'-

.......

•'>

.-12

•.

0-

.......

------1-1---.,

:·:

...

··

....

,.

.

..

·'.

t.

···.

...

.':·

..

~

,.

i.~

··~

,

~.~

-,

.·

·.'

'.

;+12v.0----

....

---t-t----::i.

WLTAGE

MONITOR

PRINT

HEAD

CONTROL

CARRIAGE

SERVO

.

CONTROL

14

PRINT

WIRE

DRIVE

.

}

CARRIAGE

SERVO

DRIVE

·.··

..•

,::

r ...

-

>·

l

..

r:~r

..

·'"

RIBBON

RUN/sroP

RIBBON

MOTOR

CONTROL

l-----f

..........

-0}

RIBBON

DRIVE

FIGURE~

Analog PowerBoard -Block Diagram -

+:!k.

...

-~

'::

i

<7=1"

·.'

~;·

! '

,1'0

•.•

'.

.

lllC•I

'

t;;·

:.

:~

"

~"\.;'

ID

.

~·~2··

~!!

I

llDIOR=--

.....

'.

'~

'

~:>~~;.··

:•' · 1

llDTOI•

I A

......

~.~

·~

"··~·

·~

'~.

.,

.,~

......

~

.~

;,

.I .

-n..

, FIGURE4-7

.

.·

§.

cp

Of

Paper

Feed

Drive Circuit

PAPEIRID

llOltlll

C1'fl

·

be

driven into saturation and the P

.·F.

motor current

will

be

sourced by the

+.

24V.

power supply. If

ZB

saturates negative,

it

will drive

Q11

into saturation and

in tumdrive

Q13

Intosafuration. This condition causes

the P.F. motor 9urrent

to

be

sourced by the

-24V.

power supply.

Since thesteppermotor

is

an

inductive device, It takes

a finite amount of rise-time

for

the current, lmotor,

to

begin to flow. As lmotor increases, the voltage across

Page8

thecurrent-sensing resistor,

R34,

begins

to

rise. When I"'·

lmotor reaches

200

ma,

(typical holding current) the · ·

voltage across

R34

is

200

mv. This voltage is fed back

to

the V

REF

node and nulls the reference voltage

causing the output

of

Z8

to

return

to

OV.

When this

occurs, the output drivers,

Q10

and

Q12,

or

Q11

and

Q13

are cut

off

and lmotor begins to. decrease. The

/91

feedback loop senses this at

R34

and causes

ZIU....o

·,

saturateagain. Knowing that

Z8

is running aquite

tr

) 1

open-loop gain and that

Q12

and

Q13

~'.:

tilgh-gain

Darlington type transistors, response time around the

control loop

is

quiteshort. This fact, coupled with the

dynamic characteristics

of

the stepper motor,

produces

an

oscillating control loop.

~

Because

of

this oscillating control loop, we are able

to

maintain our ·desired lmotor, but at the same time

reduce heat dissipation in the active devices. This

results

In

lower power consumption and increased

component life. .

To

step the P.F. motor, the digital Input must

reverse

,_.

its status. The edgeofthetransition

ls

differentiatedby :

A12

and

C14

producing a pulse at the V

REF

nodEit.

The -

polarity of the pulse is determined by the direction

of

the transition on the digital input. This pulse causes a

momentary increase in V

REF

and ·the control loop

obliges by momentarily Increasing the motor current

while reversing the direction

of

the current. As the

~

.

pulsedies away, the voltage returns

to

Its steady-state

level

of

200mv.

and the control loop returns the motor

current to itsnormal

200ma.

holding current. Note that

""

the current flow has now changed direction.

·- Figures 4-9, 4-10-and

4-11

show input and

·outpur··

·-

..

--

..

~

..

waveforms

for

the Paper Feed Drive. As the

P.

F.

phases are identical, all information in

this

section

applies

to

both circuits.

,,.,

The purpose

of

the

+CLAMP

and -CLAMP inputs

will

be discussed

in

Section 4.3.5.

FIGURE4-8

PaperFeed Stepper

Motor

FIGURE4-9

P.F.

~<I>

Input (Slew Mode)

-·

r

Page9

-

FIGURE4-10

P.F.

~

cj>

Output

(1

Step)

FIGURE4-11

P.F:.

~~Output

(Slew Mode).

4.3.3

Carriage -Servo Drive

The

~\

earrfage

'

~

.

Servo

-

D~ive

circuitry receives eight. (8)

incoming signals from

"·

the Di'gital Card and

pro~1d~s

precise carriage position_ing

with

,accuracy

to

w1th1n

1/100"

(0.254 mm). < ·•·

The CarriageServo Drive consists

of

a

D/

A conve!1er,. a

constant-speed servo drive, and a tachometer

c1rcu1t.

The

servo

motor

is

·-

1ocated on the right end-plate

of

the

Printer Assembly as shown in Figure 4-12.

. '• : .

,.

t

, .

'.

•,

..

FIGURE 4-12 Carriage Servo

Motor

2

I

. FIGURE 4-13 Carriage Servo Drive

VELOCITY

REF

.

VOLTAGE

,,

. NOTE: The components being referenced in

this

discussion may be found in either

Figure4-13

or

the schematics in section 7.6.4.

The

D/

A converter receives an octal coded command

from the Digital Card and converts the octal code

into

an

analog voltage level. The output

of

the DIA conver-

ter (DAC) is fed into a unity-gain, inverting amplifier

{Z12)

which is biased such that the output of the

OP-AMP

(Z12-1) swings between +

SV.

and

-SV.

This

DAC

circuit

output

becomes

the

VELOCITY

REFERENCE VOLTAGE (VEL. REF.).

Table 4-2

DAG-AMPLIFIER OFF-SETTRIM RESISTOR VALUES

OFF-SET

VOLTAGE TRIM RESISTOR VALUE

10mv. 5.

98

meg.

15mv

. 3.99 meg.

20mv. 2.99 meg.

25mv. 2.39 meg.

30mv. 1.99 meg.

35mv.

1.71

meg.

40mv. 1.49 meg.

45mv. 1.

33

meg.

~

50mv. 1.19 meg.

55mv. 1.

08

meg.

60mv.

998

K

65mv.

921

K

70mv. 855 K

75mv. 798 K

80mv. 748 K

85mv. 704 K

90mv. 665 K

95mv. 630 K

100mv. 598 K

+24v.

-CLAMP +

CLAMP

R

61

DYNAMIC

FEEDBACI<

-24v

.

+sv

Page

10

'

..

Accumulation

of

component tolerances may cause the

DAC AmpIifier

to

produce

an

error voltage

of

sufficient

amplitude to tum-on the servo power amplifier

even

with a zero-velocity command. To counteract this

,-,effect, a trim resistor may

be

added to the

OAC

Ampli-

fier summing node at Z12(2).

The

free

end

of this trii:n

resistor is connected to either + 12V

or

-12V. This

supplyvoltage polarity should

be

the same

as

the error

voltage polarity.

Table 4-2 shows the appropriate trim resistor value for

~a

given error voltage measured at Z12(1), the output

of

the

DAC

Amplifier.

The Tachometer Circuit provides VELOCITY FEED-

BACK. This Velocity Feedback is originated by the

OPTICAL SHAFT

ENCODER

which is attached to the

rear of the carriage servo motor.

(See

FIG. 4-12).

The

encoder produces a 2-phase output from which is

"""available both speed and directional information.

These outputs,

~A

and

~B,

are

routed to the Digital

Card where the signal waveforms are shaped into

uniform pulses using Schmitt Trigger devices and a

one-shot multivibrator. These processed signals

are

labeled

"+

TACH"

and

"-TACH" and

are

routed to the

.-,A~g

Card

as inputs

for

the Tachometer circuit.

Th~

Tachometer Circuit uses a unity-gain OP-AMP

(Z12)

as a linear integrator. When a pulse train is input

on

either+

TACH or-TACH, the Tachometer integrates

the pulses

to

obtain a D.C. voltage at

Z12,

7,

which

is the TACH output

or

VELOCITY FEEDBACK.

NOTE:

It

is important

to

know at this point

that + TACH and -TACH are gated on the

Digital Card such that thetwo signals may never

appear simultaneously.

An input

on

+ TACH will produce a negative D.C.

,ti!\)

voltage at the TACH output. An input of -T

ACH

will

produce a positive D.C. voltage at the TACH output.

Since the pulses are so conditioned as to

be

of uniform

amplitude and width, the only variable is frequency.

The pulse frequency is determined by the speed of the

servo motor. The faster the servo turns, the higher the

pulse frequency

and

the higher the VELOCITY FEED-

,.,,

BACK voltage. The polarity of the VELOCITY FEED-

B~K

is determined by the direction of servo rotation.

(1

•.••

s reverses the phase relationship of the Encoder

outputsand determines whether

+TACH

or-TACHwillt

be

gated,into the Tachometer Circuit).

The outputs ofthe

DAC

circuit

and

the

TACH

circuit

are":

,....,

tied together at

Z12,

9.

This junction is termed the

"summing node".

The

VEL.

REF.

Voltage, summed

with the

(negativ13

feedback)

VELOCITY

FEEDBACK

voltage, produces

an

"errorvoltage" which is amplified

by

the

ERROR

AMPLIFIER.

The

error amplifier output,

Z12,

8,

sources the

base

current for 025

and

026.

~The

remainder

of

the circuit works much the same

way

as

the Paper

Feed

Drive output stage but with one

major exception.

~:

The control loop for the Carriage Servo

Drive

does not

oscillate. The "dynamic feedback" loop formed

by

R68

and

C30

cancels out any oscillation tendencies and

maintains linear mode operation.

The(CRG] switch,

SW-2,

allows the servo drive circuit

to

be

manually disabled simply by grounding the out-

put

of

the error amplifier.

Page

11

The

purpose of the + CLAMP and -CLAMP inputs:will

be

discussed in Section 4.3.5. ··

··

4.3.4 Print-Wire Solenoid Drive

The

Print-Wire Solenoid Drive receives·

·eight

(8)

incoming signals from the Digital Card and provides

constant-current control of lntertec's

seven

(7)-wire

Print Head.

The

Print-Wire Solenoid Drive circuitry consists

of

a

reference voltage divider,

an

enable circuit,

and

seven

(7)

constant-current solenoid drivers. The reference

voltage divider and the enable circuit, shown in.Figure

4-14,

provide outputs that

are

common toall 7

s~lenoid

drivers. ·

As in the previous two circuits,

VREF

is used as a

reference

for

the control loop. As shown in Figure 4-15,

the solenoid drive circuits are similar in principle but

less complex than either the Paper

Feed

Drive

or

Car-

riage Servo Drive.

.foCLAMP

HEAD

ENABLE

+-12v.

DU

0-H:::'.l+--...---f"---~

HEAD

ENABLE

.·

DI

R3

SW-I

'"PRr'

FIGURE4-14

(a)

Print-Head Enable Circuit

RI

R 2

FIGURE·4

..

14

(b)

Print-Head Reference Voltage

PRINT

WIRE

SOLENOID

YREf

..,_

__

__,

FIGURE

4-15

#1

Print-Wire Solenoid Drive

: .i

i·-.

:-

.',

-

·,

'•

..

'

,.

•

Fotthe,wire

to

be

able

to

fire, both HEAD ENABLE and

PRINT-WIRE(P.W.) SELECT must be active. With

this

condition,

Z1

will switch high and saturate Q2, allow-

ing the solenoid

to

be activated..

R4

is

the

current-sensing resistor

for

the feedback loop. Once

again, the control loop does oscillate, maintaining a

low duty-cycle in the solenoid coil and active devices.

When HEAD ENABLE isactive, (See Fig. 4-14 (a))

Q1

is

cutoff, allowing

Q2

to

be driven. At all other times,

Q1

is saturated, grounding the base

of

Q2, (Fig. 4-15).

The

PRT

switch, SW-1, allows the Print-Head Solenoid

Drive

to

be

manually disabled by shorting

Q1

.

The purpose

of

the+

CLAMP input, (Fig. 4-14 (a))

will

be discussed in Section 4.3.5.

4.3.5 Voltage Monitor

The Voltage Monitor monitors the three regulated volt-

ages, +5V., +12V., -12V. from the Digital Card and

prevents movement

of

the carriage, forms tractors,

or

print-wiresduring powering-ON, powering-OFF, and in

the event

of

a Power Supply failure.

· Figure 4-16 shows the Voltage Monitor Circ-uit and

its

two

outputs,

+CLAMP

and -CLAMP.

FIGURE 4-16. Voltage

Monitor

The CLAMP outputs connect

to

the carriage Servo

Drive, the Paper Feed Drive, and the Print-Wire

Solenoid Drive and are polarity-protected by the local

diodes ·in· each circuit. The purpose

of

the CLAMP

outputs is

to

ground the driving signal

for

the output

stage

of

each circuit. Figure 4-6 illustrates how the

Voltage Monitoris connected

to

thecircuits

it

controls.

When the terminal

is

powered-ON,

Q21

and

Q22

come

up in the saturated mode.

C20

is

charged through

R37

by

the + 5V. lineuntil the potential on

C20

is

sufficient

to

tum-on Q18.

Q18

in

tum

forces

019

and

020

to

tum-on. When

Q20

turns on,

Q21

is starved

for

base

current and turns off, forcing

Q22

into

cutoff. At

this

point, ± CLAMP are allowed

to

float and all circuits

may operate.

When.the terminal is powered-OFF,

an

additional

portion of the circuit comes

into

play. Assuming that

the terminal has been powered-ON and operating

properly,

C19

has been charged

to

one diode-drop less

than+

5V., causing the output

of

Z11

to

remain high.

When the terminal

is

powered-OFF

and+

5V. begins

to

drop,

C19

remains charged, holding Z11,

3, high.

When the voltage on Z11, pin

2,

drops below that on

pin 3, the output of

Z11

switches low, pulling all

of

the

charge from C20. This causes

Q18

to

cut

off

and start

the chain reaction

to

saturate

Q21

and

022,

pulling

+ CLAMP and -CLAMP

to

ground level.

Ifeither + 5V.

or

±12V. is lost due

to

any malfunction,

021

and

Q22

are forced

to

saturateand pull the CLAMP

lines

to

ground.

L2,

L3, and C18,

C21

provide input filtering

to

prevent.-,

clamping action due

to

noise transients.

4.3.6 Ribbon Drive

The Ribbon Drive circuit receives only one

(1)

incoming

signal from the Digital Card and provides ribbon move-

ment

for

every printable character received by the .

terminal.

,..,

The Ribbon Drive circuit is quite simple, as shown in

Figure4-17.

The+

12V. line

is

dropped

to

approximate-

ly 9V. by

D24.

C22

and

C23

provide brush-noise filter-

ing and

D25,

transient protection. A HIGH on the base

of

Q24

will

saturate

it

and cause the ribbon

motor

to

run. A LOW on the base

of

Q24

will

cause the ribbon

<'91

motor

to

be

cut

off.

024

K7·19

+12v.

O----t:::J-....--...---1t--<:J

~

23

D

25

I

:g:~_·

~-

c

22

r---

K7·21

K9-ll o,..;R....

1e

...

eo

...

N

-----t

FIGURE4-17 Ribbon DriveCircuit

4.3.7 PCB Assembly Revision History

4.3.7.1

PCB

Assembly

#1130000-01

• C28

is

piggy-back with

R74

•

C29

is

piggy-back with

R73

•

027

base and emitter leads reversed

•

Q28

base and emitter leads reversed

•

R38

is

piggy-back with

Q18

•

K5

pin 12

is

bused

to

11

-

no

other connection

,a.

to

12

r')

Refer

to

Section 7.6.4 for component positioning.·

4.4 Digital Card

PCB

Assembly #1132000-03

4.4.1 Overview

fllt'.

The Digital Card contains a complete digital

micro-computer system

with

memory and interfacing.

Utilized is thehighlyacclaimed and proven

8080

micro-

computer system, with reliable MOS and TTL peri-

pherials

for

interfaceand control. The system monitors

all

I/

O portsand generates the necessary responses for

fllt'.

all

inputs

from either the keyboard

or

host computer

or

.

from within the system itself. Since the

8080

CPU

is

under stored program control,

it

is

possible

to

repro-

gram the system

for

special customer requirements.

(Contact your lntertecrepresentative

for

information on

this feature as· special software development cost

maybe involved.)

f"".

Figure 4-19 shows a simplified block diagram

of

the

SuperTerm's 8080 system. There are three basic buses

over which system information travels; the data bus,

the address bus, and the control bus.

Page

12

.ff"'.·

The

Data

Bus originates at the

CPU

and

is buffered by

the

8228

System Controller.

The

data bus is bi-direct-

ional, allowing

d~ta

to flow into and out ofthe

CPU

and

. any otherdeviceconnected to it. The data bus contains

IMleight

(8)

lines which the

8080

CPU

utilizes

as

an

8-bit

word which connects to the system memory, data

lines,

and

all

1/0

ports.

The Address Bus also originates at the

CPU.

This bus

contains sixteen

(16)

lines

and

enables the

CPU

to

directly address up to 65,536 8-bit bytes of data from

memory or

I/

O devices.

The

address bus is also

,,.,buffered using tri-state devices which provide extra

drive and allow the system bus to

be

floated for pur-

poses of external control, etc.

The Control Bus originates at the

8228

System Control-

lerand consists of status and timing signals from the

CPU

and the

8224

Clock generator. This bus controls

lilll!READ,

WRITE and

1/0

operations.

The

8080

micro-computersystem and its functions will

be

broken down and discussed in the remainder of

Section 4.4.

Complete schematics and component placement

diagrams may

be

found in Section 7.6.5.

/Sl\T~1igital

Card

and

its locati.on

are

shown in Figure

4-lo.

FIGURE4-18

4.4.2 Power Distribution and Filtering

The

Digital Card receives +

5VDC,

Logic Ground

and

+ 12VDC, -12VDC, ±12V

RET.

from the Regulator

PCB

Alllvia

the D.C. Power Distribution Harness. These con-

nections

are

made to the power-tab cor:mectors located

along the right edge of the card.

The

-5V.

Substrate

Bias for the 8080

CPU

comes from the Analog Power

Board

and

is input

on

K6,

pin 14. All of these voltages

are regulated and should

be

within 5% tolerances.

.-,All power buses are heavily filtered. Across the input

connectors

are

electrolytic and ceramic bypass capaci-

tors

on

each

bus with "the +

5V

bus being filtered

additionally by distributed electrolytic capacitors.

In

addition to these bus filters,

each

l.C. is bypassed by a

0.1

ufd ceramic capacitor.

181

4.4.3 Microprocessor System Bus and Control Logic

The

8080

CPU

(Z10)

controls every operation performed

in the SuperTerm. It accesses memory via the Address

Bus, receives programmed instructions via the

Data

Bus and outputs commands over the Data Bus.

The

CPU

is a dynamic device and therefore requires

clocking signals to time

and

coordinate its operations.

The

8224

Clock Generator

(Z22)

provides these timing

signals in addition to providing automatic power-on

reset of the system

and

system synchronization. The

!P2

(TTL) output of the

8224

is

fed

to a divider,

(Z14)

which produces 1MHZ,

500

KHZ,

and

7

.81

KHZ signals

for timing of the Servo/Head Control circuitry and

Serial Interface circuitry.

The

8228

System Controller

(Z35)

interfaces with the

8224

and the8080 to produce system control signals

on

the Control Bus. These signals control memory

opera;..

tions and

1/0

operations throughout the system. The

8228

also provides bi-directional buffering for the

CPU

Data Bus. This gives the system a higher

fan--Out

capacity and also enables the Data Bus and Control

Bus to be allowed to float for purposes

of

external

control,

OMA,

etc.

The

CPU

Address Bus is also buffered using the

74367

tri-state buffers. These devices,

(Z36),

(Z37)

and (Z21)

isolate the

CPU

Address Bus to allow a higher system

fan-out and to provide the ability to float the Address

Bus.

Access to all bus lines is available on connector (K3)

for connection

of

special options

and

system config-

urations. Other lines available provide for external

control

of

the

CPU

and

timing synchronization of peri-

pheral equipment. • :

The

device

(Z50)

shown connected to the data bus is

simply a pull-up resistor pac which insures a

..

true

logical HIGH

on

the bus lines when they are active.

4.4.4 Memory/1/0 Gating Logic

This circuitry is shown in Figure

4-19

as

three blocks

labeled MEMORY

PAGE

DECODER,

1/0

STROBE

GENERATOR, and

1/0

CHIP

DECODER.

The MEMORY

PAGE

DECODER

receives Address lines

BA10 through

BA15

and

decodes chip select informa-

tion used to access the

RAM

or

any given section of

ROM.

The MEMORY

PAGE

DECODER

is

(Z24)

and is a

74LS138

one-of-eight decoder.

One

of

the decoder

enable inputs is available

on

(K3)

for external disabling

.et

the system memory.

The.Jl2

STROBE

GENERATOR

receives Address lines

BAO

through

BA3

and generates control signals

for

the

Servo/Head Control Logic (Section 4.4.9)

and

the

SYSTEM TIMERS AND INTERRUPT CONTROL

(Section 4.4.10). Additional signals from the

1/0

STROBE GEN.

are

available on connector (K3) for

handshaking with peripheral equipment

and

for

sy-stem

expansion. The

1/0

STROBE GENERATOR

(Z11)

is a

74154

4-line to 16-line decoder.

The

1/0

CHIP

DECODER

receives address lines BA4

through BA7 and generates chip select signals for the

three

8255

programmable interface chips (Section

4.4.8) and tne

8251

USART (Section 4.4.11). An 110

FLOAT line is input from

(K3)

to allow all

1/0

to

be

di.sabled and two additional CHIP SELECT lines are

output to

(K3)

to

allow for system

1/0

expansion. The

1/0

CHIP

DECODER

(Z23)

is a

74LS138

one-of-eight

decoder.

4.4.5 System

RAM

(Read/Write Memory)

The

SuperTerm's internal system

RAM

consists of

eight

(8)

type

2102

1024-bit static

MOS

RAM'S organ-

ized into a

1024

x 8 architecture.

The

RAM

provides

an

operational stack for

CPU

status and data, and storage

for programmable system parameters.

Page

13

Th{

RAM

is 'enabled·

by

the

RAM

cs output of the

MEMORY

PAGE

DECODER

(Section 4.4.4) and

addressed by lines

BAO

through BA9 of the Address

Bus.

Read

or Write mode is selected by MEMR

and

MEMW of the Control Bus. Data

I/

0 is over the bi-

directional system Data Bus.

·System

RAM

consists of, from LSB

to

MSB,

Z61, Z59,

Z27, Z28,

Z26,

Z60,

Z58

and

Z62.

·4.4.6 System

ROM

(R~d-Only

Memory)

As previously mentioned, the system

CPU

is under

stored-program control. The standard SuperTerm

operating software is contained in

(Z51)

through

(Z55)

which

are

mask-programmed

ROM

devices.

The

ROM

chips

are

individually enabled by

CS

signals

from the

MEMORY

PAGE

DECODER

(Section 4.4.4).

ROM's

are

addressed by

BAO

through BA10 of the

Address Bus and accessed by the

MEM

R line of the

Control Bus. Data output is

on

the system's Data Bus.

4.4.7 Option Decoding Logic

Some of the options available

on

the SuperTerm

are

implemented via firmware and are not available in the

standard operating software package.

Firmware options,

are

also implemented using

ROM

devices and are included

as

such in Figure

4-19.

Option

RO

Ms

are

(Z38)

through (Z45).

~

2

(Ill)

EXTERNAL

llMING

GENERAlOR

8224

CLOCK

GEN.

KEYBOARD

The 8255's interface directly to the system's

bi~direct

tional Data Bus and receive data

and

status information

from the·

CPU

over this bus. Any information being

input

to

the system by

an

8255

also travels

on

this bus.

The 8255's

are

individually enabled by CHIP 1, CHIP

2,

~·

or CHIP 3 signals from the

1/0

CHIP

DECODER

(Section 4.4.4).

Read

orWrite mode is selected by the

f70:R

and the 1/0-W lines of

'the

Control Bus.

Each

8255

accommodates three

(3)

I/

O

port.s,

of 8-bits each,

addressed by

BAO

and

BA1

of the Address Bus.·

Figure

4-19

illustrates the circuitry with which each

~.

8255

interfaces.

CHIP 1 handles the dot-matrix pattern being transmit-

ted

to

the Analog Power Board. The dot pattern

for

each

column to

be

printed is brought out

and

latched

by

two

(2)

74174

hex D-type flip-flops. Thls section is

synchronized by the HEAD

STROBE

signal from the

~·.

Servo/Head Control Logic (Section 4.4.9).

(Note that provision is made in the hardware on both

the Digital card and the Analog Power Board

to.

accommodatea nine

(9)

wire print head. This leaves an

open door for future development and improvement.)

CHIP1 also handles the two

(2)

output lines for

con!l;Q.11

f1"I\.

of the Paper

Feed

Drive on the Analog Power

Ber

''i

(Section 4.3.2), eight

(8)

baud-rate selection lines out-

put

to

the BAUD

RATE

DECODER

(Section 4.4.11), one

ROM

RAM

ftll'.,

FIGURE

4-19

Digital card Block Diagram

4.4.8 System

1/0

Interface between the internal micro-computer system

and

its various inputs and outputs is handled by three

(3)

8255

programmable interface chips. These

are

designated

as

CHIP 1 (Z23), CHIP 2

(Z29)

and CHIP 3

(Z30).

(1)

line to the keyboard [READY]

LED

(Section 4.7.1),

one

(1)

line to enable the BELL circuit and one

(1)

line

for the

DATA

TERMINAL

READY

signal

to

the Serial

Interface Logic (Section 4.4.11).

Page

14

The BELL circuit receives a

7.81

KHZ square wave from

the

74393

EXTERNAL TIMING GENERATOR

(Z14)

and

divides

it

by four·(4) using a

7474

dual D-type flip-flop

Z46.

The

7474

is enabled from CHIP 1 and turns tran-

,.,,

sistor

(Q1)

on and

off

at 1.95 KHZ. Transistor

(Q1)

sinks current through the loudspeaker to produce the

BELL tone. Resistor

(R9)

establishes the necessary

load resistance for

(Q1)

and

(CR2)

suppresses trans-

ients from the speaker's voice-coil.

CHIP 2 handles the keyboard interfacing. Alpha-

. numeric characters are received from

(K1

), the key-

'*'

board connector,

as

an

8-bit code. All function keys

and the KEYBOARD STROBE signal are received on

dedicated lines from

(K1

). In addition, the KEYBOARD

INTERRUPT

R~QUESTsignal

is generated by the

8255.

The keyboard (READY] switch

is

also brought in from

(K1) through a 74LS14

(ZS)

Schmitt Trigger device and

""""

differentiated by

(C25)

andfR3).

Transistor

(Q2)

is

pulsed

"on"

and a

CPU

RES

T signal is transmitted

to

the 8224 CLOCK GENERATOR which initiates a reset

sequence

within

the CPU.

CHIP 2 also receives the CARRIER DETECT and

CLEAR-TO-SEND, lines from the Serial Interface line

•

lliil1

~iver

(Section 4.4.11).

0..•P 3 handles interfacing

for

the servo velocity com-

mands, servo position, servo direction, DIP-SWITCH

register and priority codes interrupts.

The

SERVO

VELOCITY COMMANDS are output from

CHIP 3 to connector (K6) over six

(6)

lines. The

bit

pattern on these

·1ines

determine the speed and

""""

direction

of

the carriage travel.

Servo position information is generated by the

COLUMN COUNTER in the Servo/Head Logic (Section

4.4.9) and is input to CHIP 3

as

a

4-l;>it

BCD count over

the lines CELLO, CELL 1, CELL 2 and CELL

3.

Servo direction information is generated by the

.-,..

DIRECTION HOLD flip-flop in the Servo/Head Logic

(Section 4.4.9) and is input

to

CHIP 3 via a single line.

The status

of

this

line, HIGH or LOW, enables the

CPU

to

determine the current direction

of

carriage travel.

The DIP-SWITCH register is also interfaced by CHIP 3.

Switches 1 through 8 are ·pulled up

to

insure a true

"""

logic

HIGH by pull-up resistor pac

(Z47)

and

are

·

~nected

to

1/0

port B

of

CHIP

3.

The remaining term-

ihttl

of

each switch is connected

to

LOGIC GROUND.

Note

that~

the DIP-SWITCH lines are active LOW. If a·

switch is selected or turned on,

it

will pull its corres-

ponding CHIP 3 input low. Switch 8 is a spare.

"""'

IMPORTANT: The

CPU

reads the DIP-SWITCH register

..

only during a power-on reset sequence. If a switch is

• changed while the SuperTerm is powered on, a power-

on reset must be executed

to

make the system aware

of

the change.

Priority Coded Interrupt information is generated by

the INTERRUPT PRIORITY ENCODER (Z49), (Section

"""

4.4.10). This information is in the form

of

a 3-bit

number representing the particular device requesting

an

interrupt and a single status line that signals the

presence

of

an

interrupt request. This information is

input to

1/0

CHIP 3

for

interface

onjo

the system data

bus. ' ·

,., An additional linefrom

CHIP~.

port A, bit 6, is used

to

select open

or

closed loopcontrol

of

the carriageServo

Drive. This enables the

CPU

to

open the VELOCITY

FEEDBACK path

to

obtain t!iefull speed

of

thecarriage

servo. This feature is used qn such operations

as

a

carriage return when the carriage has

to

be moved a

considerable distance in minimum time. This signal is

output

to

the Servo Head Control Logic (Secti.on 4.4.9).

Port A,

bit

7,

of

CHIP 3 isconnected

to

(KS),

pin 16 and

is a spare.

4.4.9 Servo/Head Control Logic

The Servo/Head Control Logic receives PHASE A and

PHASE B outputs

of

the OPTICAL SHAFT ENCODER

and processes these two signals

to

determine the

carriage position and direction of movement. The

processed signals are fed back

to

the Analog Power

Board as input

to

the Tachometer Circuit. PHASE A

and PHASE B of the encoder are input on connector

(K6)

to

a Schmitt trigger

(Z5),a

74LS14, which insures

a clean square-wave pulse.

Thes~

square-wave signals

are input

to

a dual D-type flip-flop,

(Z6)

which

deter'."

mines the direction

of

carriage· travel by decoding the

leading encoder phasECThii"nformation is latched In

the DIRECTION HOLD

fli~fl

nd{46)

is

reset and the

COLUMN COUNTER

clockeq_t:j

.

the~

flip-

flop. This action

occurs

on

every encoder pulse so that

the COLUMN COUNlER,. (Z33, a

74190)

is clocked at

every cell the carriage passes through.

NOTE: A cell is a sub-column within a character. the

OPTICAL SHAFT ENCODER generates 100 pulses per

linear. inch

of

carriage travel yielding 100cells per linear

inch.•This also allows the carriage positioning

to

be

accurate

to

within 1/100

of

an

inch.

The COLUMN COUNTER interfaces

with.

the micro-

processor system via

1/0

CHl~,3

and informs the

CPU

of

the current relative carriage position.

;

I-~

•

The COLUMN COUNTER overflow is used

to

clock the

SERVO

INTERRUPT

REQUEST

flip-flopjThis

flip-flop

sends a servo interrupt request to the INTERRUPT

PRIORITY ENCODER (Z49). After

the~

interrupt has

been acknowledged and serviced, a CLEAR SERVO

signal is sent

from

the

1(0

STJ;lOBE

GENERATOR

(Z11)

to

clear the SERVO INTERRUPT , REQUEST

flip-flop. .

The COLUMN COUNTER also receives a reset line from

the

1/0

STROBE GENERATOR. During a [READY]

or

POWER-ON RESET

execution,

the

servo

is

commanded

to

move toward the

left

true margin at

approximately two

(2}

inches per second. When the

carriage reaches the left end-stop,

it

ceases

to

move

and the OPTICAL SHAFT ENCODER ceases

to

generate pulses. The system moriitors the encoder

pulses and, if none are received

for

a specified period

of

time, the

CPU

assumes that the carriage is at the

true l'eft·margin and resets the COLUMN COUNTER

with the COL

RESET

output

of

the

1/0

STROBE

-.

~ENEB~JOR.

.

---

I

~P~ASE

A and PHASE B, after waveshaping by the

Schmitt triggers, are also input to the FREQUENCY

QUADRUPLER, (Z17), a

74C86.

The output

of

the

quadrupler triggers a

74LS221

one-:shot multivibrator

(Z18}. The one-shot is enabled by

lhe

OPEN

ICLOSED

LOOP output from

1/0

chip

3.

When enabled, the

one-shot produces

33

µs

pulses which are gated onto

the +TACH and -TACH outputs, depending on the

direction

of

servo motion. +TACH and -TACH provide

the Analog Power Board with velocity feedback. When

the one-shot is disabled, no velocity feedback is

generated, allowing maximum servo speed.

Page

15

The encoder pulses are also used to time the firing of

the print-wires.

The±

INC

PULSE

signal from

(Z7),

8,

is used to trigger the print

head

one-shot multivibra-

tor, also in

(Z18),

which is enabled by the HEAD-ON .

output

of

1/0

CHIP

1. When enabled, the print-head

one-shot generates a

400

~s

pulse each time the carri-

age

moves through a cell. This

400

µs

pulse is inverted

and output to the Analog Power Board

to

fire the print-

wires alreadyselected by

1/0CHIP1.

This is the HEAD

ENABLE strobe.

In

its non-inverted state, this signal is

named the HEAD

STROBE

and is used to clock the

HEAD

INTERRUPT

REQUEST

flip-flop (Section4.4.10).

4.4.10 System Timers and lntenupt Control

This circuitry receives interrupt requests and generates

a

MASTER

INTERRUPT

REQUEST

signal

to

the

CPU

and

an

interrupting -device identification code

to

be

interfaced onto the system Data Bus via

1/0

CHIP

3.

The

INTERRUPT

PRIORITY

ENCODER

(Z49)

receives

interrupt requests from up

to

eight

(8)

devices.

It

receives the

SERVO

INTERRUPT

REQUEST

from the

SERVO

INTR.

REQ.

flip-flop (Z40), the KEYBOARD

INTERRUPT

REQUEST

from

1/0

CHIP 2, the

USART

INTERRUPT

REQUEST

from the

USART

(Z31)

(Section

4.4.11), the

25

ms INTERVAL TIMER interrupt request,

the

5ms INTERVAL

TIMER/HEAD

INTERRU.PT

request,

and

three external option interrupt requests.

All

of

these inputs are active LOW.

The

INTERRUPT

PRIORITY

ENCODER

gen~rates

an

identifying 3-bit code for

each

of

the interrupting

devices.

The

l.D. codes

are

listed in order

of

priority in

Table 4-3.

-TABLE4-3

INTERRUPT

PRIORITY

CODES

DEVICE

l.D.

1. Servo

000

2.

5ms/Head

..

001

3.

Option

010

4.

Tape (Opt.)

011

5.

USART 100

6.

25ms

101

7.

Keyboard 110

8.

Parallel

Data

111

The5ms INTERVALTIMER iscontrolled by the

CPU

via

the

1/0

STROBE

GENERATOR

(Section 4.4.4). The

ENABLE 5ms line activated the timer which outputs to

the

·5

ms INTR.

REQUEST.

flip-flop,

(ZS).

The output of the 5ms INTR.

REQUEST

flip-flop is

ORed

with the output of the HEAD INTR.

REQUEST

flip-flop. This signal is the 5ms/HEAD INTERRUPT

REQUEST.

The CLEAR 5ms output of the

I/

0

STROBE

GENERA-

TOR

clears the timer, .the 5ms INTR.

REQUEST

flip-flop, and the HEAD INTR.

REQUEST

flip-flop.

The 25ms INTERVAL TIMER is also

CPU

controlled. It

is activated by the ENABLE

25ms

output of the

1/0

STROBE

GENERATOR

and outputs to the 25ms INTR.

REQUEST

flip-flop. The output of this flip-flop, also in

(ZS),

Is the 25ms

INTERRUPT

REQUEST.

The timer

and

the flip-flop are both cleared by the CLEAR

25ms

output of the

110

STROBE

GENERATOR.

Note that the three external option interrupt request

lines are input

on

connector

(K3)

and

are

pulled up by·

pull-up

pac

(Z47)

to insure against false interrupts

on

these lines.

4.4.11

Serial Interface Logic

General information

and

specifications for the·.

RS-232C/BELL

202C

serial interface

are

given in

Section

3.

/f/l'I

Communication over the serial interface

is

controlled ,-. .

by

the

8251

UNIVERSAL SYNCHRONOUS/ASYN-

CHRONOUS

RECEIVER

-TRANSMITTER (USART),

(Z31

).

As shown in Figure 4-19, the

USART

interfaces

with the internal system

Data

Bus

and

BAO

of the

Address BujQ!Wut orOutput mode is selected by the

i'TO=Ff

and I lines of the system

Contr61

Bus. It is

enabled by the

USART

output of the

1/0

CHIP

.-;-

·

DECODER

(pection 4.4.4).

The

USART

is synchronized with the internal system by

the2MHZ

MASTER

CLOCK

signal from

~2

(TTL)

of the

8224

CLOCK

GENE.RATOR

(Z22).

The

communication rate of the

USART

is determined

by the BAUD

RATE

CLOCK

which is the output

of~

,_ .

BAUD

RATE

DECODER

(Z16)

and

(Z4)

which

are

74. •

synchronous 4-bit counters. These counters

are

clocked by the1MHZ output

of

the EXTERNAL TIMING

GENERATOR

(Z14).

The

BAUD

RATE

CLOCK.

frequency is determined by the data inputs

to

the

counters.

The

CARRY

OUTPUT

of

(Z4)

provides the

BAUD

RATE

CLOCK and reloads the counters

with

the

(9$1

data present on the

BAUD

0through BAUD 7 data input

lines. These lines originate at

1/0

CHIP 1 and their

status is under

CPU

control.

The

BAUD

RATE

CLOCK is input

to

the

USART

on the

TXC

and

RXC

inputs. The

USART

generates

an

interrupt request on its

RXRDY

output which is

~

inverted by a

7404

(Z32)

and output

as

the

USART

INTR.

REQ.

Serial communication

1/0

occurs at connector (K4).

Standard

RS232C

interface chips

are

used

as

line

receivers/drivers. The

MC1489L

(Z57)

is used

as

line

receiver. The

SUPERVISORY

RECEIVE

and SERIAL

DATA

inputs

are

received by the

USART

while tJJ§

"""'

CARRIER

DETECT

and CLEAR

TO

SEND

inputs n

interfaced onto the internal system Data Bus by

170

CHIP 2.

The

MC1488L

(Z56)

is

used as line driver. The SERIAL

DATA,

SUPERVISORY

TRANSMIT, and

REQUEST

TO

SEND

outputs

are

all generated by the USART. The

,.,..,

DATA

TERMINAL

READY

output is generated by the

CPU

via

1/0

CHIP 1.

Signal descriptions

and

pin-outs

are

given in Table 3-1.

4.4.12. Current Loop Interface and Control

NOT

YET

AVAILABLE

This material will be disseminated in the

form ofaTechnical Bulletin. Foryour

convenience, enterthe Bulletin no. below

forfuture reference.

TECHNICAL

BULLETIN#:------

page

16

Figure4-23

SuperTerm Keyboard

#1140000-00

4.8 Printer Assembly

4.8.1 Printer Frame Assembly #1110000-00

Th~

SuperTerm's printer is built around a one-piece

"""e>~ded

aluminum frame which provides a strong

and

rigid

base

for the terminal

and

allows

easy

assembly

with minimum hardware.

/Ill!'\

The SuperTerm Pfinter

has

few moving parts

and

few

maintenance requirements.

Printer maintenance is

covered

in detail

in

Section

5.

The

Printer itself contains no electronic circuitry but

provides a mounting

base

for all of the SuperTerm's

electronics except for the keyboard. Figure

4-2

and

Figure

4-18

illustrate the mounting of all electronic

modules

on

the Printer Assembly.

~

Should repair or

replacemf)!nt

of a printer component

,..,become necessary,

it

may

be

accomplished easily.

Figures

4-24

through

4-27

show exploded views of the

Printer Frame Assembly with Parts List references for

all components.

(A

complete Parts List for the

SuperTerm may

be

found

in

Appendix A.)

NOTE: Numbers correspond to parts list

section numbers (Appendix A).

L17

FIGURE4-24

SuperTerm PrinterLeft End-Plate Assembly

Page

19

1.21

I.JI

UZ UZ

NOTE: Numbers corresi:iond

to

parts list

section numbers (Appendix

A).

FIGURE4-25

SuperTerm Printer Right End-Plate Assembly

-·-6

-

1

I=-=--=-.:---_,.---=------=------------------~--'

-,

~-

-e

·-

----------------------

~-

-

:

•9

T"t?ICA.L

ENO-PLATE

c::::c..__

-.....

;

;!i,

-..OUNTINQ

l'IAACWAAE

NOTE: Numbers correspond to parts list

section numt:iers tAl)pendhr. A).

~101

FIGURE4-26

SuperTerm Printer End-Plate Mounting

NOTE: Numbers corrosiiond

to

pa111

li$1

eeclion

numDers

CAppend1x

A).

FIGURE

4-27

SuperTerm Printer

TractorRod/Carriage Rail Mounting

Right End-Plate

2.J0.09.0J

FIGURE4-28

Ribbon Drive/CarriageAssembly

4.8.2 Carriage Sub-Assembly

#1111000-00

The Carriage Sub-Assembly travels horizontally along

the carriage rails in the Printer Frame Assembly

providing a solid mounting for the Print

Head,

ribbon

cartridge

and

ribbon drive assembly.

The only field replaceable parts of the carriage

assembly

are

those of the Ribbon Drive Assembly.

Figure

4-28

shows

an

exploded view of the Ribbon

Drive

Assembly

and

its carriage mounting.

The Carriage Sub-Assembly

may

be

removed

from the

Printer Frame Assembly by removing the carriage-rail

"C" rings

and

sliding one of the carriage rails out

through one of the

end

plates.

The

carriage drive belt

clamp may now

be

removed

and

the Carriage Sub

Assembly is free.

4.8.3 Print-Head Sub-Assembly

#1112000-00

The

Print-Head is the heart of the printing mechanism

and

rides on the Carriage Sub-Assembly. It

can

produce one line of hard-copy impact printing per pass

across the

page.

..

"""'

The

SuperTerm Print-Head used a technique called the

"anvil" concept.

The

·technique is. so

named

because

the

head

solenoids do not directly drive the print wires

but instead drive "clappers" which impact with

tt~e

butt

ends of the print wires and project them toward the

platen where they impact the ribbon

and

paper to form

ra.

a character. . .

The

Print

Head

is illustrated in Figure

4-29.

FIGURE

4-29

SuperTerm Print-Head

4.8.4 Printer Cover Assembly

#1160000-00

The Printer Cover Assembly is a three-piece Noryl

structural foam acoustic cover which encases the

entire SuperTerm. It

has

been

designed for sound

-deadening

and

easy access

to

the terminal's interior.

The

Printer Assembly is held

to

the bottom cover by ~

four (4) bolts inserted ·from the bottom through

sound-deadening shock-mount feet. As illustrated in

Figure 4-30, a slot is provided

for

using bottom

forms-feed

and

an

exit hold for the A.C. line

and

interface cables.

FIGURE

4-30 Bottom Cover

The

top

cover

provides a mount for the keyboard,

as

"""'

shown in Figure

4-31,

and

fits snuggly over aliparound .

~

the top

edge

of the bottom cover. A latch on either side

of the interior of the top cover fastens the two cover

halves together, completely encasing the SuperTerm.

Page20

Intertec Data Systems SuperTerm User manual

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