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Technical Report
Transmitter Module Model NET-ZS75
FCC ID# BRWNETZS75
3.2 Block Diagram
(Reference is made to Figure 5.1)
The (up to) four control potentiometers are at the upper right
side of the schematic drawing.
The control potentiometer, which is mechanically coupled to the
control handle and trigger,is supplied with the regulated 5.0V
voltage.
The wiper on this pot is exactly centered in the neutral control
handle and trigger position. All analog processing is performed
as deviations from this center (reference) voltage.
After the mixing of each channel, control voltage is changed to
Pulse Train, through encoder circuit.
The Q11(2SC4519)is an LC-type VCO(Voltage Controlled Oscillator),
which is designed to oscillate with about 75.650MHz. Its output is
led to amplifying stage for transmitting through a buffer(Q12),while
it is also led to the PLL through a buffer(Q13). The pulses generated
by the CPU are transferred to the VCO so as to modulate the radio
wave. this part is strictly shielded from electric/magnetic noise.
The IC3(BU2630F)is a PLL(phase Lock Loop).
Exact 13.000MHz is generated by an internal crystal oscillator, and
divided by 5,200 for 2.5kHz.
VCO wave is also divided by a definite number, which is 30,260
in case of 75.650MHz,for getting 2.5kHz.
Two 2.5kHz’s are compared in the phase and the VCO is so controlled
that the error gets minimum, while the modulation is so fast that
the filter between the PLL and the VCO cancels an error fluctuation.
Frequency data is stored in the IC1(MC68HC908QY1/CPU) as an
above-mentioned dividing number, and transferred to the PLL as the
serial data while the transmitter is in normal operation mode.
Frequency data can be changed only in system set-up mode with the
power of the RF section being cut.
Directly after it has turned on normally, though the CPU starts
sending the PLL the data. Then, supply the power to Q1 via Q8(2SC4738)
and Q7(2SA1298) to start oscillation.
