Kenwood Z919 Building instructions

Z919
CD/MD-CH DSP CONTROL CD RECEIVER
SERVICE MANUAL
C2000-5 PRINTED IN JAPAN
B51-7635-00 ( N ) 1694
Panel assy
(A64-2119-02) : K type
(A64-2120-02) : M type
Front glass
(B10-3229-02) Knob (FM,AM,FWD,REV)
(K25-1114-03)
DC cord
(E30-4737-15)
Remote controller assy
(RC-601)
(A70-2006-05)
Sub panel assy
(A22-2803-13) : K type
(A22-2857-03) : M type
Size AAA battary
(Not supplied)
Panel escutcheon
: K type only
(B01-0887-05)
Screw set
: K type only
(N99-1694-05)
Screw set
(N99-1559-05)
Mounting hardware
(J21-7673 -05)
Mounting hardware assy
(J21-7596 -02)
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TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299

2
BLOCK DIAGRAM
DRIVER
IC11
SPINDLESLED
OPTICAL PICKUP
SLED SW
SERVO DPS&ROM DECODER
IC2
uPD67324B
DRAM
IC6
IC10
AMPLIFIER
RF MATRIX
ROM : 128K
M30620MC-XXXGP
IC1
RAM : 10K
(DMA)
SW
IC3
SIO (DMA)
IICBUS
IC5
STA013
MP3
DECODER
DAC
PCM1716
IC9
IICBUS
PROCESSOR UNIT (X32-4800-00)
SYSTEM COMPUTER
MULTIPLEX BUS
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4
BLOCK DIAGRAM
3
Z919Z919
SYSTEM u-COM
SRV AVR
T8V AVR
D5V AVR
P CON
B.U DET
ACC DET
SMALL DET
ANT CON
5V SW
FM8V SW
AM8V SW
ILLUMI
PANEL u-COM
5V SW
KEY VFD
VOL MUTE TONE SEL
INPUT
SEL
ISO
NC,MPX
PWR AMP
MUTE
I/F
MZ-BUS
I/F
I/F
MAIN
CD MECHA
DXM-1701
VDD DET
REMOCON
RST SW
BUZ
MUTE
L-R MIX
AMP
E VOL, TONE, NC, MPX
CN
MZ-BUS
A1
IC3
IC2
IC6
IC20
IC16
A2
IC4 IC3
17,18
Q22
Q9
Q8
Q19
Q25
Q26
Q27
IC12
Q42-47
BZ1
IC9
IC13
Q11
Q13
ED1
MZ-BUS
IC1
ANA SW
VOL
BAL
FAD
E P ROM
IC5
S6 DRIVER
DC/DC
AMP CON
Q21
Q57,59
HPF MUTE
HPF,LPF,VOL
IC17
VOL MUTE LPF MUX /INV
N-INV
IC24
A8V AVR
TC4W66F
Q14,15
F/E
DRIVER
IC21 MOTOR CONT
IC23,
SPEED
M
OPEN SW
CLOSE SW
Q34
PANEL MECHA
D40-1112-35 Q11
MB90583BPFV110
CN1930M
HA12187
LEVEL
DET
W02-3221-05
14V SW
ILLUMI
Q24,63
14V
M 5V
IC25
IC19,Q39
IC4,Q35
IC26
784215YGC-038
SW
AVR
Q32
NJM4565M
ISO
IC10,11,14,15
TDA7400 TDA7401
TDA7386
W02-3119-15
S-24C01BFJA
UPD74042BGT
FRONT IN
REAR IN
AUDIO I/O
BUS +
BUS -
BUS ON
BUS OFF
RESET
MUTE
ILLUMI
B.U
GND
RELAY
B IRQ
B DIC
B DCOM
B CLK
B RST
B C/D
E CLK
E DATA
RESET
SYS ON
ON REQ
SYS OFF
OFF REQ
PLL CLK
PLL DATA
PLL CE
FSD
FM SD
CD LO/EJ CD MOTOR CD SW1 CD SW2 CD SW3 CD MUTE CD STOP CD RST CD CLK CD DATA G ILL
BEEP
SVR
P STBY
P MUTE
MUTE
BU DET
ACC DET
SMALL
ANT CON
P CON
P ON
FM
AM
ILLUMI
SC CON
MC CLK
SC DATA
SC REQ
P RST
REQUEST
FM DET OUT
AM DET OUT
CE
FM SD
FSD
CLK
DATA
AM ANT FM ANT
PON 5V
COM +B
FM +B
AM +B
AUDIO OUT
M SW 5V
AUD +B
B.U 5V
LO/EJ
MOTOR
SW 1
SW 2
P CON
ANT CON
SMALL
ACC
B.U
GND
B.U DET
ACC DET
SMALL
ILLUMI
PON 5V
B.U 5V
FM +B
AM +B
B.U 5V
REAR
SP OUT
FRONT
SP OUT
B.U
B.U 5V
+B
FAC
PRE OUT
FRONT
REAR
CD:
379mV
AM:
160mV
498mV
939mV
900mV
1500mV
FM
AM
ANT CON
B.U 5V
400mV
FM:
LEVEL
913mV
1522mV
505mV
953mV
AMP CON AMP CON
REQUEST
SW 3
A MUTE R
M STOP
M RST M CLK
M DATA
DIAG
1507mV 1486mV
850mV
888mV
1417mV
1404mV
470mV
SRV +B
AUDIO +B
364mV 600mV
200mV
763mV
379mV
340mV
T CTRL
MOTOR-
MOTOR +
SPEED
OPEN DET
CLOSE DET
SW 14V B.U 5V SRV ON
M SW 5V
COM +B
P ON
DIAG
P CON
AMP CON
SW 14V
2
MD,CD:
TAPE: FM: AM:
TV:
MD,CD-CH:
MD,CD:
MD,CD-CH:
AM:
FM:
TAPE,TV: AM:
MD,CD-CH:
TAPE,TV:
MD,CD:
FM:
MD,CD:
TAPE,TV:
FM:
AM:
MD,CD-CH:
FM:
AM: 572mV 189mV
MD,CD-CH:
MD,CD:
TAPE,TV: 566mV
358mV
343mV MD,CD: MD,CD-CH:
TAPE,TV:
225mVAM:
FM:
409mV
674mV
682mV
427mV
PON 5V
PON 5V CD DET
A MUTE L
SRV +B
PRE OUT
NON-FAD
PRE OUT
SWITCH UNIT (X25-8530-11)
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5
COMPONENTS DESCRIPTION
Synthesizer Unit (X14-6260-xx)
Ref. No. Components Name Application / Functions Operation / Condition / Compatibility
IC2 UPD72042BGT MZ-BUS Interface IC MZ-BUS Communication Interface
IC3 784215YGC-038 Microcomputer System Microcomputer
IC4 M5237ML Regulator IC Tuner+B
IC5 S-24C01B E2PROM Tuner Adjustment Data Memory
IC6 TDA7400 Electronic Volume EVOL, LOUD,TONE, BAL, FAD, FMNC, MPX
IC7 TC7W02F Logic IC (NOR) Logic circuit for muting
IC9 S-80830ANNP Power source detection System Microcomputer Reset
IC10 NJM4565M-TE2 Ope Amp (2 enclosed) Isolation Circuit (DSP Input Lch)
IC11 NJM4565M-TE2 Ope Amp (2 enclosed) Isolation Circuit (DSP Input Rch)
IC12 L9820D013TR P-CON P-CON, ANT-CON output control
IC13 TC4W66F Analog Switch Switch for head and slave unit switching
IC14 NJM4565M-TE2 Ope Amp (2 enclosed) Isolation Circuit (DSP Input Lch)
IC15 NJM4565M-TE2 Ope Amp (2 enclosed) Isolation Circuit (DSP Input Rch)
IC16 NJM4565M-TE2 Ope Amp (2 enclosed) Reference voltage output, level meter circuit
Ic17 TDA7401 Electronic Volume HPF, LPF, VOL, MUTE
IC19 M5237ML Regulator IC Audio+B
IC20 TDA7386 Power IC Power amp for speaker output
IC21 BA6219BFP-Y Motor Driver Panel mechanism motor control
IC23 NJM2130F Ope Amp (1 enclosed) Panel mechanism motor control
IC24 LM2675M-ADJ Switching Regulator Servo+B
IC25 BA05T Regulator IC 5V switch for CD mechanism
IC26 M5278D05 Regulator IC Backup 5V
Q1 DTC144EUA Illumination switch ON when Micon 56 pin is “H”
Q2 DTA144EUA for BUS communication (BUS communication illumination output)
Q3 DTA144EK Switch for head ON when Micon 84 pin is “H” (When outputting own source)
and slave unit switching OFF when Micon 84 pin is “L” (When inputting other source)
Q5 UMC2N DC/DC+B switch ON when Micon 56 pin is “H” (DC/DC+B output)
Q6 DTC124EK AM+B switch ON when Micon 7 pin is “H” (AM+B output)
Q7 DTC124Ek FM+B switch ON when Micon 8 pin is “H” (FM+B output)
Q8 CPH3105 AM+B switch ON when Micon 7 pin is “H” (AM+B output)
Q9 CPH3105 FM+B switch ON when Micon 8 pin is “H” (FM+B output)
Q10 DTC124EK Buzzer switch ON when Micon 87 pin is “H”
Q11 DTC114YK Switch for guide illumination ON when Micon 49 pin is “H” (Guide illumination lights up)
Q12 DTC114EK Switch for head ON when Micon 84 pin is “H” (When outputting own source)
and slave unit switching OFF when Micon 49 pin is “L” (When inputting other source)
Q13 DTC144EK Reset Switch ON when panel reset request is “H” (Resetting action)
Q14 UMG2N System ON/OFF Request Switch ON when Micon 95, 96 pin is “L” or slaves BUS
ON/OFF request (each requelsing system ON/OFF)
Q16 DTA124EK Mute Switch ON when Micon 74,75 pin is “H”, backup detection,
and reset request from panel (Mute ON)
Q17 UMA2N System ON/OFF Switch ON when Micon 95, 96 pin is “L”
(Each requesting system ON/OFF)
Q19 2SB1277(Q,R) Antenna Control ON when Micon 3 pin is “H” (Antenna control output)
Q20 2SV2412K
Q21 DTA123JK External Amplifier Control ON when Micon 83,75 pin is “H”
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6
COMPONENTS DESCRIPTION
Ref. No. Components Name Application / Functions Operation / Condition / Compatibility
Q22 DTC124EK Level Meter Mute Swtich ON when “H” at Q16 ON (level meter mute processing)
Q23 DTC144Ek Navu Mute Switch ON when nave mute is “H” (mute processing)
Q24 2SC4081 DC/DC+B Switch ON when micon 56 pin is “H” (DC/DC+B output)
Q25 DTC144EK Samll Detection ON when small signal is “H” (Dimmer processing)
Q26 2SC2412K ACC Detection ON when detecting ACC, OFF when non-detecting ACC.
Q27 2SC2412K B,U Detecton ON when detecting B and U, OFF when detecting instant diminishing
Q28 DTC144EK IC17 (Electronic Vol.) Mute Switch ON when “H” at Q16 ON (IC17 mute processing)
Q29 DTC144EK Panel Mechanism torque control switch ON when micon 51 pin is “H” (Weak panel mechanism torque)
Q30 2SD2114K Switch for Head and ON when micon 84 pin is “H” (When outputting own source)
Slave unit switching OFF when micon 84 pin is “L” (When inputting other source)
Q31 DTC144EUA Pre-out mute switch ON when Q31 is ON and and “L” (pre-out mute actoin)
Q32 DTB123YK P_ON 5V switch ON at time of micon 100 pin “L” (P_ON 5V output)
Q33 DTA124EUA Pre-out mute switch ON when Q16 is ON and and “H” (pre-out mute actoin)
Q34 DTC114YK Panel Mechanism speed control switch ON when micon 57 pin is “H” (Panel mechanism actoin, low speed)
Q35 2SB1184 Tuner+B switch On when micon 7 or 8 pin is “H”(Tuner +B output)
Q39 2SB1184 Audio +B switch ON when P_ON 5V is ON (Audio +B output)
Q40 DTA124EK Tuner+B switch On when micon 7 or 8 pin is “H”(Tuner +B output)
Q41 DTA124EK Audio +B switch ON when P_ON 5V is ON (Audio +B output)
Q42 DTC343TK Audio mute front Lch ON when Q33 ON and “H” (Mute processing)
Q43 DTC343TK Audio mute front Rch ON when Q33 ON and “H” (Mute processing)
Q44 DTC343TK Audio mute in rear Lch ON when Q33 ON and “H” (Mute processing)
Q45 DTC343TK Audio mute in rear Rch ON when Q33 ON and “H” (Mute processing)
Q46 DTC343TK Audio mute nonfender Lch ON when Q33 ON and “H” (Mute processing)
Q47 DTC343TK Audio mute nonfender Rch ON when Q33 ON and “H” (Mute processing)
Q49 DTC144EK Tuner+B switch On when micon 7 or 8 pin is “H”(Tuner +B output)
Q50 2SC2412K Illumination switch ON when micon 56 pin is “H” (Panel illumination is ON.)
Q53 DTC114YUA Power IC SVR control switch ON when micon 91 pin is “H” (SVR discharge)
Q54 DTC144EK Audio+B switch ON when P_ON 5V is ON (Audio +B output)
Q56 UMC2N Switch 14V ON when micon 56 pin is “H” or P_ON 5V is ON (SW 14V output)
Q57 2SC4081 Switch 14V ON when micon 56 pin is “H” or P_ON 5V is ON (SW 14V output)
Q59 CPH3105 Switch 14V ON when micon 56 pin is “H” or P_ON 5V is ON (SW 14V output)
Q63 CPH3105 DC/DC+B Switch ON when micon 56 pin is “H” (DC/DC+B output)
Switch Unit (X25-8530-11)
Ref. No. Components Name Application / Functions Operation / Condition / Compatibility
IC1 HA12187FP BUS-IC IC for BUS communication
IC3 MB90583BPFV110 Panel micon IC for panel control
IC4 RS-171 Remote control light receiving IC Output 2 pin pulse when receiving remate control
Q5 DTA144EUA Swotch for PANEL 5V ON when base is “L”
Q10 DTC114EUA VFD 5V control ON when base is “H”
Q11 DTA144YK VFD 5V SW ON when base is “L”
Q12 DTC114EUA FL+B detection SW ON when base is “H”
Q13 DTC114EUA VFD blanking control ON when base is “H”
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MICROCOMPUTER’S TERMINAL DESCRIPTION
System Microcomputer 784215YGC (X14-6260-xx : IC3)
Pin Pin Name Function I/O Description Processing Operation
1 P120/RTP0 DIAG I PCON-IC excess voltage & current detection terminal L: Abnormal / H:Normal
2 P121/RTP1 P_CON O P-CON control output terminal L: Off / H: On
3 P122/RTP2 P_ANT O Power antenna control output terminal L: Off / H: On
4 P123/RTP3 BU_DET I Back up detection terminal L: Back up on detection
5 P124/RTP4 ACC_DET I ACC detection terminal L: Acc On detection
6 P125/RTP5 O Not used
7 P126/RTP6 AM+B O Tuner AM power control terminal
8 P127/RTP7 FM+B O Tuner FM power control terminal
9 Vdd Vdd – 5V potential
10 X2 X2 – Main system clock oscillation terminal (12.58MHz)
11 X1 X1 I Main system clock oscillation terminal (12.58MHz)
12 Vss Vss – GND potential
13 XT2 XT2 – Sub-system clock oscillation terminal (32.768KHz)
14 XT1 XT1 I Sub-system clock oscillation terminal (32.768KHz)
15 RESET RESET I System reset input L: Reset / LÆH: Processing begins
16 P00/INTP0 BIRQ I Communication request from K-Bus Request at rising edge
17 P01/INTP1 O Not used OPEN (L-fixed)
18 P02/INTP2 O Not used OPEN (L-fixed)
19 P03/INTP3 PN_SC_REQ I Communication request from panel micon Request at rising edge
20 P04/INTP4 O Not used OPEN (L-fixed)
21 P05/INTP5 O Not used OPEN (L-fixed)
22 P06/INTP6 REF_CON O A/D port reference voltage control terminal
23 AVdd AVdd – Connected to Vdd
24 AVref0 AVref0 – A/D port reference voltage terminal
25 P10/ANI0 FSD I S-meter detection terminal (Adjust to) FM: 2.85V at ANT 35dBµ
Voltage at AM: ANT 35dBµ
26 P11/ANI1 OPEN I Panel mechanism open switch L: Panel full-open
27 P12/ANI2 CLOSE I Panel mechanism close switch L: Panel full-close
28 P13/ANI3 CD_DET I CD in place/not in place detection terminal L: Disk in place / H: Disk not in place
29 P14/ANI4 I Not used Connected to GND
30 P15/ANI5 I Not used Connected to GND
31 P16/ANI6 SEL1 I Changed according to destination SEL1, SEL2 / H, L M-type
SEL1, SEL2 / H, H K-type
32 P17/ANI7 SEL2 I Changed according to destination Refer to 31 pin
33 AVss AVss – Connected to Vss
34 P130/ANO0 ST_SEL0 I IC2 III (TDA7400) Roll Off Comp setting terminal SEL0, SEL1 / L, H Change1
SEL0, SE11 / H, L Change2
SEL0, SEL1 / H, H Change3
SEL0, SEL1 / L, L Initial setting
35 P131/ANO1 ST_SEL1 I IC2 III (TDA7400) Roll Off Comp setting terminal Refer to 31 pin
36 AVref1 AVref1 – Not used Connected to VDD
37 P70/RxD2/SI2 I Not used Connected to GND
38 P71/TxD2/SO2 PLL_DATA O PLL-IC data output terminal
39 P72/ASCK2/SCK2 PLL_CLK O PLL-IC clock output terminal
40 P20/RxD1/SI1 BDIC I K-Bus data input terminal
41 P21/TxD1/SO1 BDCOM O K-Bus data output terminal
42 P22/ASCK1/SCK1 BCLK O K-Bus clock output terminal
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Pin Pin Name Function I/O Description Processing Operation
43 P23/PCL O Not used Open (L-fixed)
44 P24/BUZ O Not used Open (L-fixed)
45 P25/SI0/SDA0 CD_DATA I/O CD mecha control data I/O terminal
46 P26/SO0 O Not used Open (L-fixed)
47 P27/SCK0/SCL0 CD_CLK O CD mecha control clock I/O terminal
48 P80/A0 O Not used Open (L-fixed)
49 P81/A1 G_ILLUM O Guide illumination power control terminal L: Off / H: On
50 P82/A2 O Not used Open (L-fixed)
51 P83/A3 T_CTRL O Panel mech torque control terminal L: Strong / H: Weak
52 P84/A4 PN_SC_CON O Panel micon wakeup control terminal L: Off / H:Wakeup
53 P85/A5 PN_SC_DATA I Panel micon data input terminal
54 P86/A6 PN_MC_CLK O Panel micon clock output terminal
55 P87/A7 PN_RST O Panel micon reset outputterminal L: Panel micon reset
Actiononly when reset releasing
56 P40/AD0 ILLUM O Key illumination power control terminal L: Off / H: On
57 P41/AD1 MOTOR_SPD O Panel mechanism processing speed control terminal Highspeed: L / Lowspeed: H (Angle adjustment: Lowspeed)
58 P42/AD2 O Not used Open (L-fixed)
59 P43/AD3 CD_MUTE I CD mechanism mute detection terminal L: Mute requested.
60 P44/AD4 CD_RST O CD mechanism reset contorl terminal L: CD mechanism micon recet
L→H:Action start
61 P45/AD5 O Not used Open (L-fixed)
62 P46/AD6 CD_STOP O CD mechanism control wakeup contorl output terminal L: Off / H:Wakeup
63 P47/AD7 CD_SW2 I CD mechanism switch2 (8cm/12cm) L: 12cm disk
64 P50/A8 CD_SW1 I CD mechanism switch1 (Loading start) L: Disk in place
65 P51/A9 CD_SW3 I CD mechanism switch3 (Down & limit) L: Loading complete
66 P52/A10 O Not used Open (L-fixed)
67 P53/A11 O Not used Open (L-fixed)
68 P54/A12 O Not used Open (L-fixed)
69 P55/A13 O Not used Open (L-fixed)
70 P56/A14 CD_MOTOR O CD mechanism motor control terminal MOTOR, LOEJ / L, Hi-Z stop
MOTOR, LOEJ / H, L loading
MOTOR, LOEJ / H, H eject
MOTOR, LOEJ / H, Hi-Z brake
71 P57/A15 CD_LOEJ I/O CD mechanism loading/eject control terminal Refer to 70 pin
72 Vss Vss – GND potential
73 P60/A16 O Not used Open (L-fixed)
74 P61/A17 P_MUTE O PWR-IC mute control terminal L: Off / H: On
75 P62/A18 MUTE O Mute control output terminal L: Off / H: On
76 P63/A19 BC/D O K-Bus comand / Data control terminal L: data / H: Command
77 P64/RD BCS O K-Bus CS control terminal
78 P65/WR BRST O K-Bus reset control terminal L: BUS-IC reset
79 P66/WAIT MOTOR+ O Panel mechanism motor control (+direction) M+, M– / L, L stop
M+, M– / L ,H reverse
M+, M– /H, L forward
M+, M– /H, H brake
80 P67/ASTB MOTOR– O Panel mechanism motor control (–direction) Refer to 79 pin.
81 Vdd Vdd – 5V potential
82 P100/TI5/TO5 SRV_PN O Servo power control output terminal H: Servo +B On
83 P101/TI6/TO6 AMP_CON O External amp basss boost level control terminal
MICROCOMPUTER’S TERMINAL DESCRIPTION
8
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Pin Pin Name Function I/O Description Processing Operation
84 P102/TI7/TO7 RELAY O BUS-AUDIO switching control terminal L: Other source inpout
H: Own source outpout
85 P103/I8/TO8 PLL_CE O PLL-IC CE output terminal
86 P30/TO0 FM_SD I FM SD detection terminal L: No station / H: Station in place
87 P31/TO1 BEEP O Beep output terminal L: Off / H: On
88 P32/TO2 REQUEST O Seek control terminal When seek: L / When receiving: H
89 P33/TI1 TEST (Not used) O Temperature protecton control terminal (not used) When in test mode: L / Other: H
90 P34/TI2 STBY O PWR-IC pwer cotnrol termianl L:Off / H: On
Rising: 400ms after PON
Falling: Same as PCON
91 P35/TI00 SVR_ON O SVR control terminal L: Normal
H:When discharging After STBY falling
H within 5 seconds
92 P36/TI01 OFF_REQ I K-Bus Off request detection terminal L:System Off request detection
93 P37 ON_REQ I K-Bus On request detection terminal L: System On request detection
94 TEST/Vpp TEST – Direct connection with Vss
95 P90 SYS_OFF O K-Bus Off request output terminal L: System Off request detection
96 P91 SYS_ON O K-Bus On request output terminal L: System On request detection
97 P92 EVOL_DATA I/O Electronic voluem data I/O terminal
98 P93 EVOL_CLK O Electronic voluem clock output terminal
99 P94 SMALL I SMALL detection terminal L:On / H: Off
100 P95 P_PN O P-ON control output terminal L:On / H: Off
Panel Microcomputer MB90583BPFV110 (X25-8530-11 : IC3)
Pin Pin Name Function I/O Description Processing Operation
1 P22/A18 KR3 I Take in key, Key Return3
2 P23/A19 KR3 I Take in key, Key Return4
3~8 NC O Not used
9 Vss – GND
10~15 NC O Not used
16~18 – O GND
19 P43/SIN1 P_ON O Power control on ambient IC’s L: On / H: Off
20 P44/SOT1 VFD_DATA O VFD (Illumination tube) serial data output terminal
21 Vcc – 5V
22 P45/SCK1 VFD_CLK O VFD (Illumination tube) serial clock output
terminal(Z)(M)(D) 2.10MHz, (J)(MZ) 1.57MHz
23,24 NC O Not used
25 C C 0.1µF condensor connection pin
26 P71 SC_DATA O When EFECT/SOURCE key is pressed when
ACC/POWER Off, send key code to system micon
27 P72 SC_REQ O By active change (“Lo→Hi”), send
transmission request for key code to system micon
28 DVRH – 5V
29 DVSS – GND
30 P73/DAO0 NC O Not used. Open
31 P74/DAO1 REF_CON O AVD port refeence voltage control terminal
32 AVCC – 5V potential
MICROCOMPUTER’STERMINAL DESCRIPTION
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Pin Pin Name Function I/O Description Processing Operation
33 AVRH – AD port reference voltage input terminal
34,35 AVRL – GND
36 P50/AN0/SIN3 LEVEL_M I HEAD spec analyzer signal input terminal
37~39 NC O Not used
40 Vss Vss GND
41~44 NC O Not used
45 P80/IRQ0 SC_CON I System performance condition detection terminal
46 P81/IRQ1 NC O Not used Open
47 MD0 Vcc I Chip mode selection terminal (Hi) Pull up (5V)
48 MD1 Vcc I Chip mode selection terminal Pull up (5V)
49 MD2 Vss I Chip mode selection terminal Pull down (GND)
50 HSTX HSTX I Hardware reset terminal H: Reset
51 P82/IRQ2 KR0 I keyreturn 0 (Effective key during STBY)
52 P83/IRQ3 NC O Not used Open
53 P84/IRQ4 MC_CLK I Due to active change (clock),
key data is sent to the system micon
54 P85/IRQ5 NC O Not used Open
55 P86/IRQ6 SYS_ON O HA12187FP STBY terminal L: STBY
56 P87/IRQ7 VFD_ON O VFD 5V control terminal "H": on "L":off
57~61 NC O Not used
62 P65/CKOT VFD_LAT O VFD latch control terminal L→H for latching
63 TX TX O IE Bus output
64 RX RX I IE Bus input
65~68 NC O Not used
69 P94/TOT1/OUT0 VFD_BLK O Duty is switched by blank output control
(Lo: Blank ON / H: Blank OFF)
70 P95/TOT2/OUT1 NC O Not used Open
71 P96/PWC REMOCON I Remote control signal input terminal
72~77 NC O Not used
78 X0A X0A Connected to GND
79 Vss Vss GND
80 X0 X0 Main clock input terminal
81 X1 X1 Main clock input terminal
82 Vcc Vcc 5V
83 P00/AD00 NC O Not used Open
84 P01/AD01 Pull up 5V I For flushing 5V
85~90 NC O Not used
91 P10/AD08 KS0 O Keyscan 0 for outputting keyscan signal
92 P11/AD09 KS1 O Keyscan 1 for outputting keyscan signal
93 P12/AD10 KS2 O Keyscan 2 for outputting keyscan signal
94 P13/AD11 KS3 O Keyscan 3 for outputting keyscan signal
95 P14/AD12 KS4 O Keyscan 4 for outputting keyscan signal
96~98 NC O Not used
99 P20/A16 KR1 I Keyreturn 1 for taking in key
100 P21/A17 KR2 Keyreturn 2 for taking in key
MICROCOMPUTER’STERMINAL DESCRIPTION
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11
Mechanism Microcomputer M30620MCAA56GP (X32-4800-00 : IC1)
Pin Pin Name Function I/O Description Processing Operation
1~5 NC O –
6 BYTE BYTE I Switching Bus width 8Bit/16Bit H
7 CNVss CNVss I – L
8,9 NC O –
10 RESET RESET I Reset terminal L: Reset, H: Normal
11 Xout Xout O Clock output –
12 Vss Vss – – –
13 Xin Xin I Clock input –
14 Vcc Vcc – – –
15 P85/NMI NMI I L: Interrupt, H: Normal
16 P84/INT2 INT3 I Servo DSP (Processor section) interrupt terminal L: Interrupt, H: Normal
17 P83/INT1 INT2 I Servo DSP (Decoder section) interrupt terminal L: Interrupt, H: Normal
18 P82/INT0 INT1 I Servo DSP (ATAP section) interrupt terminal L: Interrupt, H: Normal
19,20 NC O –
21 P77/TA3IN DCS O DAC chip selection L: Select
22 P76/TA3OUT PD O Ambient IC resetting L: Rest, H: Normal
23 P75/TA2IN/W ML O DAC micon communication data latch line H: Latch
24 P74/TA2OUT/W MC O DAC micon communication clock line –
25 P73/CTS2/TA1IN/V MD O DAC micon communication data line –
26 P72/CLK2/TA1OUT/V NC O – L
27 P71/RxD2/SCL/TA0IN/TB5IN I2C_CLK I/O For mechanical control communication (Clock) –
28 P70/TxD2/SDAT/TA0OUT I2C_DATA I/O For mechanical control communication (data) –
29 P67/TxD1 MP3_I2C_DATA I/O For STA013 control communication (data) –
30 P66/RxD1 R O For flush writing L
31 P65/CLK1 MP3_I2C_CLK I/O For STA013 control communication (clock) –
32 P64/CTS1/RS1/CLKS1 W O For flush writing L
33 P63TxD0 MP3_DATA O For MP3 data transmission (data) –
34 P62/RxD0 NC O – L
35 P61/CLK0 MP3_CLK O For MP3 data transmission (clock) –
36 P60/CTS0/RTS0 MP3_REQ I MP3 data request –
37 P57/RDY/CLKOUT WAIT I Multiplex path wait terminal L: Busy, H: Ready
38 P56/ALE ALE O For muliplex bus –
39 P55/HOLD HOLD I For flush writing L
40 P54/HLDA HLDA O – L
41 P53/BCLK NC O – L
42 P52/RD RDM O For multiplex bus –
43 P51/WRH/BHE NC O L
44 P50/WRL/WR WRM O For multiplex bus –
45 P47/CS3 CS3 O M24B chip selection L: Select
46~53 NC O –
54 P36/A14 MUTE-R O Mute (right) terminal L: Mute
55 P35/A13 MUTE-L O Mute (left) terminal L: Mute
56 P34/A12 LDON O Laser On/Off terminal L: Off, H:On
57 P33/A11 MP3/CD O CD-DA/MP3 switching terminal L: CD-DA, H: MP3
58 P32/A10 PON O Ambient IC power control terminal L: Off, H: On
59 P31/A9 CDRW O RW switching terminal H: RW, L: Other
60 Vcc Vcc – – –
61 P30/A8 (/–/D7) NC O – L
62 Vss Vss – – –
MICROCOMPUTER’STERMINAL DESCRIPTION
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Pin Pin Name Function I/O Description Processing Operation
63 P27/A7 (/D7/D6) AD7 I/O Address/Data (7 Bit) Line –
64 P26/A6 (/D6/D5) AD6 I/O Address/Data (6 Bit) Line
65 P25/A5 (/D5/D4) AD5 I/O Address/Data (5 Bit) Line
66 P24/A4 (/D4/D3) AD4 I/O Address/Data (4 Bit) Line
67 P23/A3 (/D3/D2) AD3 I/O Address/Data (3 Bit) Line
68 P22/A2 (/D2/D1) AD2 I/O Address/Data (2 Bit) Line
69 P21/A1 (/D1/D0) AD1 I/O Address/Data (1 Bit) Line
70 P20/A0 (/D0/–) AD0 i/O Address/Data (0 Bit) Line
71 P17/D15/INT5 RFOK I RFOK interrupt terminal (Not Used) L: Interrupt, H: Normal
72 P16/D14/INT4 MSTOP I MSTOP etection terminal L: Interrupt, H: Normal
73 P15/D13/INT3 INT4 I L: Interrupt, H: Normal
74~78 NC O –
79 P07/D7 T3 I Test port for testing by those in charge of electricity L
80 P06/D6 T2 I Test port for testing by those in charge of electricity L
81 P05/D5 T1 I Test port for testing by those in charge of electricity L
82 P04/D4 EMPH I Emphasis On/Off L: Off, H: On
83 P03/D3 RFOK I RFOK terminal L: NG, H: OK
84 P02/D2 NC O – L
85 P01/D1 SW3 I Internal track detection switch L: On, H:Off
86 P00/D0 DETECT I Detrack amount L: DETECT
87~93 NC O –
94 P100/AN0 AGND – – –
95 Vss NC O – L
96 VREF NC – – L
97 AVcc AVcc – – –
98~100 NC O –
MICROCOMPUTER’STERMINAL DESCRIPTION
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13
MP3 DSP IC : STA013 (X32-4800 : IC5)
OUT SIDEVIEW
PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM
CLOCK GENERATION
LOW POWER CONSUMPTION: 85mW AT 2.4V
CRC CHECK AND SYNCHRONISATION ERROR DE-
TECTION WITH SOFTWARE INDICATORS
I2C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
10MHz,14.31818 MHz, OR 14.7456MHz EXTERNAL IN-
PUT CLOCK OR BUILT-IN INDUSTRY STANDARD XTAL
OSCILLATOR DIFFERENT FREQUENCIES MAY BE
SUPPORTED UPON REQUEST TO STM
Note Z919 : 10MHz
APPLICATIONS
PC SOUND CARDS
MULTIMEDIA PLAYERS
DESCRIPTION
The STA013 is a fully integrated high flexibility MPEG Layer
III Audio Decoder, capable of decoding Layer III compressed
elementary streams, as specified in MPEG 1 and MPEG 2
ISO standards.The device decoders also elementary streams
compressed by using low sampling rates, as specified by
MPEG 2.5.
STA013 receives the input data through a Serial Input
Interface.The decoded signal is a stereo,mono, or dual chan-
nel digital output that can be sent directly to a D/A converter,
by the PCM Output Interface.This interface is software pro-
grammable to adapt the STA013 digital output to the most
common DACs architectures used on the market.
The functional STA013 chip partitioning is described in Fig. 1.
SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORT-
ING.
Note (Z919 is guaranteed to the MPEG 1.0 Layer III.)
•All features specified for Layer III in ISO/IEC11172-3
(MPEG 1 Audio)
•All features specified for Layer III in ISO/IEC13818-3.2
(MPEG 2 Audio)
•Lower sampling frequencies syntax extension, (not speci-
fied by ISO) called MPEG2.5
DECODES LAYERIII STEREO CHANNELS, DUAL CHAN-
NEL, SINGLE CHANNEL (MONO)
SUPPORTING ALLTHE MPEG 1 & 2 SAMPLING FRE-
QUENCIES AND THE EXTENSION TO MPEG 2.5: 48,
44.1, 32, 24, 22.05, 16, 12, 11.025, 8kHz
ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COM-
PRESSED BIT STREAMWITH DATA RATE FROM 8 Kbit/
s UP TO 320 Kbit/s
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
ANCILLARY DATA EXTRACTIONVIA I2C INTERFACE
SERIAL PCM OUTPUT INTERFACE (I2C AND OTHER
FORMATS)
I
2
C CONTROL
SERIAL
INPUT
INTERFACE
BUFFER PARSER
MPEG 2.5
LAYER III
DECODER
CORE
CHANNEL
CONFIG.&
VOLUME
CONTROL
OUTPUT
BUFFER
PCM
OUTPUT
INTERFACE
10
11
95
26
828212012 2425
34
6
7
SYSTEM & AUDIO CLOCKS TEST INTERFACE
RESET SDA SCL
SDI
SCKR
BIT_EN
SRC INT OUT_CLK/
DATA_REQ XTI XTO OCLK TESTEN SCANEN
SDO
SCKT
LRCKT
Fig. 1 Block diagram: MPEG 2.5 Layer III Decoder hardware Partitioning
CIRCUIT DESCRIPTION (MP3)
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14
CIRCUIT DESCRIPTION (MP3)
Pin Connection
Pin Description
Pin No. Pin Name Type Function PAD Description
1 VDD_1 Supply Voltage
2 VSS_1 Ground
3 SDA I/O I2C Serial Data +Acknowledge CMOS Input Pad Buffer
CMOS 4mA Output Drive
4 SCL I I2C Serial Clock CMOS Input pad Buffer
5 SDI1 I Receiver Serial Data CMOS Input Pad Buffer
6 SCKR I Receiver Serial Clock CMOS Input Pad Buffer
7 BIT_EN I Bit Enable CMOS Input Pad Buffer with pull up
8 SRC_INT I Interrupt Line For S.R.Control CMOS Input Pad Buffer
9 SDO O Transmitter Serial data (PCM Data) CMOS 4mA Output Drive
10 SCKT O Transmitter Serial Clock CMOS 4mA Output Drive
11 LRCKT O Transmitter Left/Right Clock CMOS 4mA Output Drive
12 OCLK I/O Oversampling Clock for DAC CMOS Input Pad Buffer
CMOS 4mA Output Drive
13 VSS_2 Ground
14 VDD_2 Supply Voltage
15 VSS_3 Ground
16 VDD_3 Supply Voltage
17 PVDD PLL Power
18 PVSS PLL Ground
19 FILT O PLL Filter Ext. Capacitor Conn.
20 XTO O Crystal output CMOS 4mA Output Drive
21 XTI I Crystal Input (Clock Input) Specific Level Input Pad
22 VSS_4 Ground
23 VDD_4 Supply Voltage
24 TESTEN I Test Enable CMOS Input Pad Buffer with pull up
25 SCANEN I Scan Enable CMOS Input Pad Buffer
26 RESET I System Reset CMOS Input Pad Buffer with pull up
27 VSS_5 Ground
28 OUT_CLK/DATA_REQ O Buffered Output Clock/Data Request Signal CMOS 4mA Output Drive
Note : SRC_INT signal is used by STA013 internal sofrware in Broadcast mode only; in Multimedia mode SRC_INT must be connected to VDD.
In Functional mode TESTEN must be connected toVDD, SCANEN to ground.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD _ 1
VSS
_ 1
SDA
SCL
SDI
SCKR
BIT EN
SRC _ INT
SDO
SCKT
LRCKT
OCLK
VSS
_ 2
VDD
_ 2
OUT
_ CLK/DATA _ REQ
VSS
_ 5
RESET
SCANEN
TESTEN
VDD
_ 4
VSS
_ 4
XTI
XTO
FILT
PVSS
PVDD
VDD
_ 3
VSS
_ 3
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CIRCUIT DESCRIPTION (MP3)
Z919
■FUNCTIONAL DESCRIPTION
●Clock Signal
The STA013 input clock is derivated from an external source
or from a industry standard crystal oscillator, generating in-
put frequencies of 10, 14.31818 or 14.7456MHz.
Note Z919 : 10MHz
XTI is an input Pad with specific levels
Symbol Parameter Test Condition Min. Typ. Max. Unit
VIL Low Level VDD–1.8 V
Input Voltage
VIH Hight Level VDD–0.8 V
Input Voltage
• CMOS compatibility
The XTI pad low and hight levels are CMOS compatible; XTI
pad noise maegin is better than typical CMOS pads.
• TTL compatibility
The XTI pad low level is compatible with TTL while the hight
level is not compatible (for example if VDD = 3V TTL min
hight level = 2.0V while XTI min hight level = 2.2V)
●Serial Input Interface
STA013 receives the input data (MSB first) thought the Se-
rial input Interface (Fig. 2). It is a sirial communication inter-
face connected to the SDI (Serial Data Input) and SCKR (Re-
ceiver Serial Clock).
The interface can be configured to receive data sampled on
both rising and falling edge of the SCKR clock.
The BIT_EN pin, when set to low, forces the bitstream input
interface to ignore the incoming data. For proper operation
BIT_EN line shold be toggled only when SCR is stable low
(for both SCLK_POL configuration) The possible configura-
tions are described in Fig. 3.
●PLL & Clock Generator System
When STA013 receives the input clock, as described in “Clock
Signal”, and a valid layer III input bit stream, the internal PLL
locks, providing to the DSP Core the master clock (DCLK),
and to the Audio Output Interface the nominal frequencies of
the incoming compressed bit stream.The STA013 PLL block
diagram is described in Figure 4.
The audio sample rates are obtained diving the oversam-
pling clock (OCLK) by software programmable factors.The
operation is done by STA013 embedded software and it is
transparent to the user.
The STA013 PLL can drive directly most of the commercial
DACs families, providing the VCO frequency with a software
programmable dividers.
DATA
SOURCE
MPEG
DECODER
SERIAL AUDIO INTERFACE
RX TX
PLL IIC
IIC
FILT
µP
SDA
SCL
XTI
XTO
DATA _ REQ
SDI
SCKR
BIT
_ EN
SDO
SCKT
LRCKT DAC
OCLK
Fig. 2 MPEG Decoder Interfaces
DATA IGNORED
DATA IGNORED
DATA VAOLID
SDI
SCKR
SCKR
BIT
_ EN
SCLK
_ POL=0
SCLK
_ POL=4
Switching
Circuit
PFD CP
MVCO
X
S
N
XTI2OCLK
XTI2DSPCLK
FRAC
Update
FRAC
Disable PLL
XTI
CC
R
OCLK
DCLK
Fig. 3 Serial Input Interface Clocks
Fig. 4 PLL and Clock Generation System
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PCM output Interface
The decoded audio data are output in serial PCM format.
The interface consists of the following signals.
ADO PCM Serial data Output
SCKT PCM Serial Clock output
LRCLK Left/right Channel selection Clock
The output samples preciision is selectable from 16 to 24
bits/word, by setting the output precision with PCMCONF (16,
18, 20 and 24 bits mode) register. Data can be output either
with the most significant bit first (MS) or least significant bit
first (LS), selected by writing into a flag of the PCM-CONF
register.
Figure 5 gives a description of the several STA013 PCM
Output Formats.
The sample rates set decoded by STA013 is described
Table 1.
MPEG 1 MPEG 2 PMEG 2.5
48 24 12
44.1 22.05 11.025
32 16 8
STA013 Operation Mode
The STA013 can work in two different modes, called Multi-
media Mode and Broadast Mode.
In Multimedia Mode, STA013 decodes the incoming bitstream,
acting as a master of the data communication from the source
to itself.
This control is done by a specific buffer management, con-
trolled by STA013 embedded software.
The data source, by monitorng the DATA_REQ line, send to
STA013 the input data, when the signal is high (default con-
figuration).
The communication is stopped when the DATA_REQ line is
low.
In this mode the fractional part of the PLL is disabled and the
audio clocks are generated at nominal rates. Fig. 9 describes
the default DATA_REQ sigal behaviour.
Programming STA013 it is possible to invert the polarity of
the DATA_REQ line (register REQ_POL).
LRCKT
SDO
SDO
LRCKT
SDO
SDO
SDO
SDO
16 SCLK
Cycles 16 SCLK
Cycles 16 SCLK Cycles
16 SCLK
Cycles 16 SCLK Cycles
M
S
M
S
L
S
L
SM S
L
SM S
L
SM S
L
S
M
SL SM SL SM SL SPCM_ORD=0
PCM_PREC=16
bit mode
PCM_ORD=1
PCM_PREC=16
bit mode
32 SCLK
Cycles 32 SCLK
Cycles 32 SCLK Cycles
32 SCLK
Cycles 32 SCLK Cycles
M
SL S0M SL S0M SL S0M SL S0PCM_FORMAT=1
PCM_DIFF=1
M
SL S
0M
SL S
0M
SL S
0M
SL S
0PCM_FORMAT=0
PCM_DIFF=0
M
SL S
MSB M
SL S
MSB M
SL S
MSB M
SL S
MSB PCM_FORMAT=1
PCM_DIFF=0
M
SL S
00
M
SL S
00
M
SL S
00
M
SL S
00
PCM_FORMAT=0
PCM_DIFF=1
Fig.5 PCMoutputFormats
Table1 MPEGSamplingrates(kHz)
In Broadcast Mode, STA013 works receiving a bitstream with
the input speed regulated by the source. In this configuration
the source has to guarantee that the bitrate is equivalent to
the nominal bitrate of the decoded stream.
To compensate the difference between the nominal and the
real sampling rates, the STA013 embedded software con-
trols the fractional PLL operation. Portable or Mobile appli-
cations need normally to operate in Broadcast Mode. In both
modes the MPEG Synchronisation is automatic and trans-
parent to the user. To operate in Multimedia mode, the
STA013, pin nr. 8, SCR-INT must be connected to VDD on
the application board.
STA013 Decoding States
There are three different decoder states: Idle, Init, and De-
code. Commands to change the decoding states are de-
scribed in the STA013 I2C registers description.
• Idle Mode
In this mode the decoder is waiting for the RUN command.
This mode should be used to initialise the configuration reg-
ister of the device. The DAC connected to STA013 can be
initialised during this mode (set MUTE to 1).
PLAY MUTE Clock State PCM Output
X 0 Not Runnig 0
X 1 Runnig 0
DATA _ REQ
SOURCE SEND DATA TO STA013
SOURCE STOPS
TRANSMITTING DATA SOURCE STOPS
TRANSMITTING DATA
Fig.6
CIRCUIT DESCRIPTION (MP3)
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17
• Init Mode
“PLAY”and “MUTE”changes are ignored in this mode. The
internal state of the decoder will be updated only when the
decoder changes from the state “init”to the state “decode”.
The “init”phase ends when the first decoded samples are at
the output stage of the device.
• Decode Mode
This mode is completely described by the following table.
PLAY MUTE Ciook State PCM Output Decoding
0 0 Not Running 0 No
0 1 Running 0 No
1 0 Runnig Decoded Samples Yes
1 1 Running 0 Yes
I2C BUS SPECIFCATION
The STA013 supports the I2C protocol.This protocol defines
any device that sends data on to the bus as a transmitter and
any device that reads the data as a receiver.The device that
controls the data transfer is known as the master and the
others as the slave. The master always starts the transfer
and provides the serial clock for synchronisation.The STA013
is always a slave device in all its communications.
COMMUNICATION PROTOCOL
•Data transition or change
Data changes on the SDA line must only occur when the SCL
clock is low. SDA transition while the clock is high are used
to identify START or STOP condition.
• Start condition
START is identified by a high to low transition of the data bus
SDA signal while the clock signal SCL is stable in the high
state.
A START condition must precede any command for data trans-
fer.
• Stop condition
STOP is identified by low to high transition of the data bus
SDA signal while the clock signal SCL is stable in the high
state.A STOP condition terminates communications between
STA013 and the bus master.
• Acknowledge bit
An acknowledge bit is used to indicate a sucoessful data trans-
fer.The bus transmitter, either master or slave, releases the
SDA bus after sending 8 bit of data.
During the 9th clock pulse the receiver pulls the SDA bus low
to acknowledge the receipt of 8 bits of data.
• Data input
During the data input the STA013 samples the SDA signal on
the rising edge of the ciock SCL.
For correct device operation the SDA signal has to be stable
during the risng edge of the clock and the data can change
only when the SCL line is low.
DEVICE ADDRESSING
To start communication between the master and the STA013,
the master must initiate with a start condition. Following this,
the master sends onto the SDA line 8 bits (MSB first) corre-
sponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifier,
corresponding to the I2C bus definition.For the STA013 these
are fixed as 1000011.
The 8th bit (LSB) is the read or write operation RW, this bit is
set to 1 in read mode and 0 for write mode. After a START
condition the STA013 identifies on the bus the device ad-
dress and, if a match is found, it acknowledges the identifica-
tion on SDA bus during the 9th bit time. The following byte
after the device identification byte is the internal space ad-
dress.
WRITE OPERATION (see Fig. 7)
Following a START condition the master sends a device se-
lect code with the RW bit set to 0.
The STA013 acknowledges this and waits for the byte of in-
ternal address.
After receiving the internal bytes address the STA013 again
responds with an acknowledge.
• Byte write
In the byte write mode the master sends one data byte, this
is acknowledged by STA013.The master then terminates the
transfer by generating a STOP condition.
• Multibyte write
The multibyte write mode can start from any internal address.
The transfer is terminated by the master generatinga STOP
condition.
DEV-ADDR SUB-ADDR DATA IN
RW STOP
ACK ACK ACK
START
BYTE
WRITE
DEV-ADDR SUB-ADDR DATA IN
RW STOP
ACK ACK ACK
DATA IN
ACK
START
MULTIBYTE
WRITE
Fig.7 WriteModeSequence
CIRCUIT DESCRIPTION (MP3)
Z919
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
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TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299

18
READ OPERATION (see Fig. 8)
• Curent byte address read
The RTA013 has an internal byte adress counter.Each time
a byte is written or read, this counter is incremented.
For the current byte address read mode, following a START
condition the master sends the device address with the RW
bit set to 1.
The STA013 acknowledges this and outputs the byte address
by the internal byte address counter.The master does not
acknowledge the received byte, but terminates the transfer
with a STOP condtion.
• Sequential address read
This mode can be intiated with either a curret address read
or a rendom address read. However in this case the master
does acknowledge the data byte output and the STA013
countinuse to output the next byte in sequence.
To terminate the streams of byte the master does not
anknowledge the last receivesd byte, but terminates the trans-
fer with a STOP condition.
The output data stream is from consective byte address, with
the interminal byte address counter automatically incremented
after one byte output.
DEV-ADDR
DEV-ADDR SUB-ADDR
DATA
RWSTART
START START
STOP
ACK
RW RW STOP
STOP
RW=HIGH
ACK
ACK ACK ACK
ACK ACK NO ACK
NO ACK
DEV-ADDR DATA
DATA
NO ACK
DEV-ADDR
START
DEV-ADDR DEV-ADDRSUB-ADDR
START START
RW
ACK
RW STOP
ACK ACK ACK NO ACKACK
DATA DATA DATA
DATA DATA
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
Fig.8 ReadModeSequence
CIRCUIT DESCRIPTION (MP3)
Z919
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
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TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299

19
ADJUSTMENT
When changing FM/AM front end A1 or IC5 of the synthesizer unit, it is necessary to conduct adjustments.
Item Input side (SG) setting Tuner Setting Adjustment Method
FM
S-Meter 98.1MHz, 0 dev FM 98.1 MHz •Enter test mode and select FM source
35dBµ•Press Preset “3”key for 2 seconds or more
(Antenna input) Adjustment starts 98.1MHz
Normal completion of adjustment 98.1MHz
Writing adjustment value to the EEPROM 98.1MHz
End of writing
When adjustment is completed normally (2kHz beep x2 times) 11.1-C3
When adjustment was not completed normally (440Hz beep x4 times) 00.0-C3
AM
Seek 999kHz : M Type AM •Enter test mode and select AM source
Stop 1000kHz : KType 999kHz : M Type •Press Preset “3”key for 2 seconds or more
Level 0% mod 1000kHz : K Type Adjustment starts 999kHz/1000kHz
35dBµNormal completion of adjustment 999kHz/1000kHz
(Antenna input) Writing adjustment value to the EEPROM 999kHz/1000kHz
End of writing
When adjustment is completed normally (2kHz beep x2 times) 1111-C3
When adjustment was not completed normally (440Hz beep x4 times) 0000-C3
How to enter test mode
During power OFF, while pressing CLK key and Audio key, press Source key to power ON.
Or while pressing CLK key and Audio key, switch ACC from OFF to ON.
ReleasingTest Mode
By resetting, initial condition is achieved.
CIRCUIT DESCRIPTION (MP3) / ADJUSTMENT
1. A request for read (minute, second, frame) occurs in the
MP3 decoder control within the mechanical micon (IC1).
2. The mechanical control within the mechanical micon sets the
requested time on the ROM decoder and conducts search.
3. The data is accumulated in the DRAM (IC6) attached to
the ROM decoder (IC2.)
4. Loading is completed as
there is no ECC error.
5. The time when the error occurred
is set on the requested time.
6. Copying is conducted by one-sector (2048Kbyte) DMA from
DRAM (IC6) to internal RAM of the mechanical micon (IC1)
7. Copy complete is sent to the MP3 decoder control within
the mechanical micon.
8. MP3 decoder within the mechanical micon (IC1) begins serial transfer
by DMA to the MP3 decoder (IC5). The sequence goes back to 1 .
No error Error
MP3 Playing Procedure
Z919
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299

ABCDE
1
2
3
4
5
6
7
R31
R36
CP9
CP12
C15
CP7
CP8
CP1
C5
R1 R3
R34
CP6
CP5
CP10 C18
C19
L3
L4
R48
R49
R28
R27
R4
R25
R26
C1
R32
R35
R33
R30
C13
C14
C12
C11
R61
R43
R39
R37
R41
C16
R2
L2
R47
C3
X1
C4
CP11
C2
R53
C17
191
8
5
41
1
25 51
75
5026
76100
MD0
CLK
IN
RSTX
MD2
HSTX
OUT
P00
EB
EB
EB
EB
EB
P00
C15 EB
R61
C5
R41
R43
C16
R25
R1
R26
C14
R34
C13
CP11
R37
R53
R35
50 26
CP9
100
CP12
CP10
1
CLK
OUT
IN
L3
25
L4
RSTX
X1
76
75
CP8
51
R36CP7
CP5
MD0
4
C12
CP6
R30
R32
R33
1
R39
C1
5
R2
CP1
8
C11
HSTX
MD2
C17
R31
R47
L2
C2
R48
C18
EB
1
R4
C4
19
C3
E
R49
B
EB
EB
C19
R28
R27
R3
D3
D13
D1
Q11
D14
D18
D15
D16
D12
D2
D6
D17
D26
Q5
Q10
Q12 Q13
IC1
IC3
D5
D25
CN1
D15
D18
Q5
D17
D5
D16
IC3
IC1
D2
D6
D26
D25
D13
D1
D12
D3
CN1
D14
Q11
Q10 Q12
Q13
S3
S20
D11
S2
S19
S16
S17
D10
S18
S6
S7
S4
D7
D8
S21
D20
S13 S14
S12
S1 S15
S23
S5
IC4
X25-8530-11 (J74-1021-12)
S5
D10
S20
S3
D8
IC4
D7
S4
S19
S1 S21
S2
D20
S12
S13
S14S15
S23
X25-8530-11 (J74-1021-12)
S16
S7
D11
S6
S17
S18
C10
2
1
3 4
SRC
DOWN
12
EJE
345
6
S.A
DISP
S/S
AUD
UP
RST
CLK
ED1
AM
FM
13 44 52 55 57
31
DOWN
1
2
AUD
3 4
UP
S/S
445257 55
ED1
C10
SRC
123
45
6
FM
EJE
DISP
AM
RST
S.A
CLK
X25-8530-11
IC Q Address
14D
35D
46D
56D
10 3D
11 3D
12 3D
13 3D
Refer to the schematic diagram for the values of resistors and capacitors.
20
PC BOARD
X25-8530-11
IC Q Address
14B
35B
46B
56B
10 3B
11 3B
12 3B
13 3B
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299

21
FGHIJKLMNO
1
2
3
4
5
6
7
PC BOARD (COMPONENT SIDE VIEW)
C32
C86
R80
W1
CP8
CP9
C100
R59
R46R44
R48
CP5
C38 C40 R58R56
C46 R54R50 C48
R57
R53
R60
CP10
R200
R73
C101
R15
C52
C66
C19
L2
C49
R45
R43
C37
C34
R77
R78
C22
C81
C78
R99
R97
C80
R2
R104
R8
C79
R98
C77
R96
C4
C84
C5 C9
C1
C85
R1
CP6
CP7
R75
R76
R102
R100
R103
C83 C82
R109
R107
R110
R108
C76
C55
R63
R64
R66
C65
CP4
C31
C8
C7
C2
C3
C10
C13
R14
R10
R9
C68
C69
C70
R101R13
C29
C67
R42
C30
R79
R83
R19 R18
R23
R22
R21
R20
R38
R39
C15
R17
R16
C18
R35
C24
C26
C20
C25
R37
R36
R34
C23
C17
C74 R29
R95
R91
R41
R26
R40
R31
R25 R32
R28 R33
R24 R30
C21
C71
R81
R88
R82
CP3
C39
R47
C11
C33
R27
R86
R87
R12
L4
1
34
5
1
14
28
15
1
89
16
1
1415
28
1
45
8
O
G
I
1
22
1
3
6
4
43
16
SG
SG
SG
D
D
D
58
1
4
1
16
44
23 22
1
EB EB
CNVss
RESET
LRCK
3.3V
MSTOP
MO1
MD
ML
CS
MUTER
PON
LDON
SD
FD
TD
MRST
EMPH
MUTEL
MRST
DOUT
PD
FE
TE
GND
IOP-
IOP+
RF
Vref
E
F
SLED-
EJECT
SLED+
LOAD
ARF
SCK0
MCK0
MCK
SD0
D
CLK
LR
MCK
C
GND
LCR
ML
SPL-
B
SPL+
A
VC
MC MO
CS
BCK LRCK
DATA
PD
MCK MP3/CD
DMUTE
MC
MO1
MD
+5V
CE
EPM WC
R
T
T3
ER0
ERCK
T1
T2
SW3
MRQ
RFCK
EMPH
RFOK
DET
I2
I3I4
I1
NC RST
RW M/C
H-CK
H-DT
M-DATA
M-CLK
V3
SW2
RD
WR
WAIT
CS
ALE
SW1
PLCK
LOCK
DEF
MD SD
FD
TD
F-
T- T+
F+
F
E
GND
LD
VR
PD
Vcc
Vc
TBL
FBL
LBL
RFOK
MIRR 3TO
LE
TE2
ACVET
RF2
GND
Vcc
CN1
IC3
IC12
IC5
Q3
IC9
CN2
IC6
Q1
IC13
IC8
D1
Q2
Q4
Q7
Q6
Q5 IC7
IC11
IC2
IC1
S3
Q8
D2
IC10
IC4
X32-4800-00 (J74-1046-22)
C45
C50
R65
L5
C42
C72
R51
R49 C43
C41
R85
C54
W62
W61
C64
R67
C53
C58 1
W72
W71
C60
C61
R55 R94
C35
S2
C62
C63
X2
R68
C56
W70
R52
CP1
C36
L3
C27
CP2
C14
C28
C16
C75
R84
C12
X1
C73
C87
W69
L1
R89
R90
R5
R4
R7
R6
S1
40
81 120
121
160
41
80
1
18
19
36
125
51 75 76
100
26
50
1
34
6
13
4
5
1
14 15
28
1
ACVET
44
FBL RFOK
MIRR
3TO
RFCK
C37
R43
GND
Vref
TE RF
IOP-
RF2
IOP+
ARF
F
E
FD
SD MD
TD
23 C39
R47
FE
W1
C32
GND
Vcc
CP4
LBL
TBL
CP3
D1
B
CP7
C33
R45
C34
DEF
22
LOCK
PLCK
CP6 CP5
C31
EMPH
R75
R76
ER0
SW1
SW2
5
C49
TE2
LE
4R66
R63
R64
R57
C18
R91
R95
R73
WR
B B
T+
F-
8
16 1
C65
C55
VC
L4
PD
C
A
GND
LD
VR Vcc
Vc
T-
F+
F
EE
C69
EJECT
C68
SLED-
LOAD
C70
43
61
22
C11
R10
E
R9
SCK0 R31
H-DT R26
C22
C19
L2
R28
WAIT
ERCK
LRCK R33
R32
H-CK
R25
R24
M-DATA
M-CLK
DOUT
MCK0 R30
C21
GND
SPL+
V3
R109
C77
RL
R13
C3
R104
SLED+
R8
C2
C8
R101
R100
1
36 4
1
R108
C78
R99 R2
R110
8
C79
1
R98
C81
C80
R102
R97
4
5
R1
R96
R107
R17
SPL-
R38
R22
R19 R18
R23
G
G
S
S
D
D
R39
R21
R20
R16
1
R40
I
C7
LCR
CLK
MCK
O
G
C15
14
SD0
C74
C26
R37 15
C17
R34
MRST
MUTER
LDON
ALE
RD
CS
MUTEL
MRST
PON
R81
CP8
R88
M/C RST
NC
+5V
CP9
RW
R83 EPM
CE
RESET
C71
MSTOP
C67
I4 I2
T2 I1
I3 T3
T1
EMPH
4MD
MO1
3
C30
R82
R79 R78
R77
R80
WR
T
C
CNVss
3.3V
MRQ SG D
R42
C29
R12
CP10
RFOK
DET
SW3
MO1
R41
C100
R53
R29
C66
CS
R27
MC 28
5PD
ML
R44
R48 C38
SD
MD
R103
R60
R15
1
MCK
C85
C82
PD
C83
C84
R200
C101
C5
C86 1514
28
C4
1
C9
C1
MC MO
CS
LRCK
ML
DATA
BCK
R87
R86
C76
C10
9
C25
R36
C20
C24
R35
C23
8
DMUTE
MCK
R14
C13
161
MP3/CD
R56
C46
R50
R46
C40
R59 TD
C52
FD R58
R54 C48
CN2
IC6
CN1
IC13
Q4
Q3
Q2
D1
Q1
IC12
Q6
Q7
IC8
IC5
IC7 Q5
IC9
IC3
IC10
IC2
Q8
D2
S3
IC4
IC1
X32-4800-00 (J74-1046-22)
IC11
41
W69
W62
C42
36
C45
C50
S2S1
C64
C35
C36
81
80
CP2
C56
C63
C62
W70
W72
C60
C53 1
W71
C61
CP1
121
120
X2
R51
C41
C43R49
R55
R94
19
L1
C12
40
R52
18
R85
R67 R65
W61
C58
C54
6
43
1
L5
R68
C87
R5
R7
R4
C27
160 1
L3
R6
R90
R89
31
C28
R84
C14
5
4
C16
50
51
76 75
C73
25
26
C72
1
100
X1
C75
14
15
128
(FOIL SIDEVIEW)
X32-4800-00
IC Q Address
14I
25H
32H
43I
53I
65H
73I
IC Q Address
83H
92G
10 5G
11 2I
12 3G
13 4F
13G
IC Q Address
24G
34G
44G
53I
63I
73I
84G
X32-4800-00
IC Q Address
14L
25M
32M
43L
53L
65M
73L
IC Q Address
83M
92N
10 5N
11 2L
12 3N
13 4O
13N
IC Q Address
24N
34N
44N
53L
63L
73L
84N
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
TEL [phone] QQ 376315150 892498299 TEL [phone] QQ 376315150 892498299