Kontron VITA 57 User manual

VITA 57
Development Kit User's Guide
SD.DT.F79-0e - May 2011
If it's embedded, it's Kontron.

Development Kit User's Guidede
Preface
Page i SD.DT.F79-0e
Revision History
Publication Title: Development Kit User's Guidede
Doc. ID: SD.DT.F79-0e
Rev. Brief Description of Changes Date of Issue
0e Initial Version May 2011
Copyright © 2011 Kontron AG. All rights reserved. All data is for information purposes only and not guaranteed
for legal purposes. Information has been carefully checked and is believed to be accurate; however, no
responsibility is assumed for inaccuracies. Kontron and the Kontron logo and all other trademarks or registered
trademarks are the property of their respective owners and are recognized. Specifications are subject to change
without notice.

Development Kit User's Guidede Preface
SD.DT.F79-0e Page ii
Proprietary Note
This document contains information proprietary to Kontron. It may not be copied or transmitted by any means,
disclosed to others, or stored in any retrieval system or media without the prior written consent of Kontron or one
of its authorized agents.
The information contained in this document is, to the best of our knowledge, entirely correct. However, Kontron
cannot accept liability for any inaccuracies or the consequences thereof, or for any liability arising from the use
or application of any circuit, product, or example shown in this document.
Kontron reserves the right to change, modify, or improve this document or the product described herein, as seen
fit by Kontron without further notice.
Trademarks
This document may include names, company logos and trademarks, which are registered trademarks and,
therefore, proprietary to their respective owners.
Environmental Protection Statement
This product has been manufactured to satisfy environmental protection requirements where possible. Many
of the components used (structural parts, printed circuit boards, connectors, batteries, etc.) are capable of being
recycled.
Final disposition of this product after its service life must be accomplished in accordance with applicable country,
state, or local laws or regulations.
The Waste Electrical and Electronic Equipment (WEEE) Directive aims to:
>reduce waste arising from electrical and electronic equipment (EEE)
>make producers of EEE responsible for the environmental impact of their products, especially when they
become waste
>encourage separate collection and subsequent treatment, reuse, recovery, recycling and sound
environmental disposal of EEE
>improve the environmental performance of all those involved during the lifecycle of EEE

Development Kit User's Guidede
Preface
Page iii SD.DT.F79-0e
Conventions
This guide uses several types of notice: Note, Caution, ESD.
Note: this notice calls attention to important features or instructions.
Caution: this notice alert you to system damage, loss of data, or risk of personal injury.
ESD: This banner indicates an Electrostatic Sensitive Device.
All numbers are expressed in decimal, except addresses and memory or register data, which are expressed in
hexadecimal. The prefix `0x' shows a hexadecimal number, following the `C' programming language convention.
The multipliers `k', `M' and `G' have their conventional scientific and engineering meanings of *103, *106and *109
respectively. The only exception to this is in the description of the size of memory areas, when `K', `M' and `G'
mean *210, *220 and *230 respectively.
When describing transfer rates, `k' `M' and `G' mean *103, *106and *109not *210 *220 and *230.
In PowerPC terminology, multiple bit fields are numbered from 0 to n, where 0 is the MSB and n is the LSB. PCI
and CompactPCI terminology follows the more familiar convention that bit 0 is the LSB and n is the MSB.
Signal names ending with an asterisk (*) or a hash (#) denote active low signals; all other signals are active high.
Signal names follow the PICMG 2.0 R3.0 CompactPCI Specification and the PCI Local Bus 2.3 Specification.
For Your Safety
Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its
compliance with electrical safety requirements. It was also designed for a long fault-free life. However, the life
expectancy of your product can be drastically reduced by improper treatment during unpacking and installation.
Therefore, in the interest of your own safety and of the correct operation of your new Kontron product, you are
requested to conform with the following guidelines.
High Voltage Safety Instructions
Warning!
All operations on this device must be carried out by sufficiently skilled personnel only.
Caution, Electric Shock!
Before installing a not hot-swappable Kontron product into a system always ensure that your mains power
is switched off. This applies also to the installation of piggybacks. Serious electrical shock hazards can
exist during all installation, repair and maintenance operations with this product. Therefore, always unplug
the power cable and any other cables which provide external voltages before performing work.

Development Kit User's Guidede Preface
SD.DT.F79-0e Page iv
Special Handling and Unpacking Instructions
ESD Sensitive Device!
Electronic boards and their components are sensitive to static electricity. Therefore, care must be taken
during all handling operations and inspections of this product, in order to ensure product integrity at all
times
Do not handle this product out of its protective enclosure while it is not used for operational purposes unless it
is otherwise protected.
Whenever possible, unpack or pack this product only at EOS/ESD safe work stations. Where a safe work station
is not guaranteed, it is important for the user to be electrically discharged before touching the product with his/her
hands or tools. This is most easily done by touching a metal part of your system housing.
It is particularly important to observe standard anti-static precautions when changing piggybacks, ROM devices,
jumper settings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not
placed on conductive surfaces, including anti-static plastics or sponges. They can cause short circuits and
damage the batteries or conductive circuits on the board.
General Instructions on Usage
In order to maintain Kontron’s product warranty, this product must not be altered or modified in any way. Changes
or modifications to the device, which are not explicitly approved by Kontron and described in this manual or
received from Kontron’s Technical Support as a special handling instruction, will void your warranty.
This device should only be installed in or connected to systems that fulfill all necessary technical and specific
environmental requirements. This applies also to the operational temperature range of the specific board
version, which must not be exceeded. If batteries are present, their temperature restrictions must be taken into
account.
In performing all necessary installation and application operations, please follow only the instructions supplied
by the present manual.
Keep all the original packaging material for future storage or warranty shipments. If it is necessary to store or
ship the board, please re-pack it as nearly as possible in the manner in which it was delivered.
Special care is necessary when handling or unpacking the product. Please consult the special handling and
unpacking instruction on the previous page of this manual.

VITA57Development Kit User's Guide
Table Of Contents
Page v SD.DT.F79-0e
Table Of Contents
Chapter 1 - Introduction 1..........................................................
1.1 Prerequisites 1.....................................................................
1.2 Use cases 1.......................................................................
Chapter 2 - Development 2........................................................
2.1 FPGA Kontron Source Code 2.......................................................
2.2 FPGA Code Compilation 4..........................................................
Chapter 3 - Deployment 7.........................................................
3.1 Upload User Flash with Software Tool from Linux Prompt (Binary file) 7...................
3.2 Upload User Flash with JTAG Probe (mcs file) 7.......................................
3.3 Upload Flash on FMC 7.............................................................
Chapter 4 - Troubleshooting 8......................................................
4.1 Configuration Check 8..............................................................
4.2 FPGA Check 8....................................................................
4.3 FMC EEPROM Check 9............................................................
4.4 FMC IOs Check 9..................................................................
4.4.1 FMC GPIOn signals 9...........................................................
4.4.2 FMC TXn/RXn signals 11.........................................................
4.4.2.1 Enable buffers 12.....................................................
4.4.2.2 Test a channel 12....................................................
4.5 Low Level Debug with IO Command 14................................................
Chapter 5 - Additional Information 16.................................................
5.1 Loopback Connector on FMC-SER0 Front Panel 16.....................................
5.2 IO Routing with a VM6250 SBC board as FMC Carrier 18................................

VITA 57 Development Kit User's Guide Introduction
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Chapter 1 - Introduction
1.1 Prerequisites
>Knowledges and practices of the xilinx development and design tools like Ise Design Suite version 11.1.
>User’s knowledges and practices of Linux: the drivers and tests tools ( binaries and sources ) delivered as
examples, are available for Linux distributions and are coded in C and python language.
>Modifying some FPGA code IP’s like I2C, SPI is highly inadvisable. All modification will be done at customer’s
own risks. I2C and SPI IPs were dedicated to Kontron boards so any changes could break some
functionalities.
1.2 Use cases
This documents meet the following cases:
>New FPGA application development.
>New FPGA application deployment.
>New FPGA application test.
>Troubleshooting. All of those cases will be developed hereafter.

VITA 57 Development Kit User's GuideDevelopment
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Chapter 2 - Development
The following chapters will describe an example of a FPGA application development and how to use the tools
to generate an FPGA image.
2.1 FPGA Kontron Source Code
The VITA 57 project example file tree is the following:
The entry point of the Kontron source code is the file Topserial.v describing a VITA 57 implementation example.

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The following shows the FPGA sources files:
Now, you could add your Verilog files and libraries, modify the current files to match your application. You will
find hereafter the snapshot of the VM6250 VITA 57 project as example.

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2.2 FPGA Code Compilation
The following is an example of compilation based on VM6250 VITA 57 case.
>You will find hereafter the snapshot of the VM6250 VITA 57 project as example:

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>Open the ISE Design suite and select your project:
>Select your application dedicated file into the hierarchy window (here, Topserial.v), then right click on
“Generate program file” into the process window and click on “Run” or “ReRun” … to generate the “bit” or “bin”
or both files file (You can select to generate several kind of files using the processes properties into the
process menu).

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>The generation process is launched, if no errors appear, “bit” file will be generated into Worklib directory.

VITA 57 Development Kit User's Guide Deployment
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Chapter 3 - Deployment
On Kontron design, the Flash containing the FPGA code is fitted on the CPU Board near the FPGA chip. This
flash contains a rescue FPGA image used to check the health of the Flash/FPGA/FMC ensemble. The
development kit provides the same image as the sample user application. Once the customer application
generated, there are several ways to upload the flash.
3.1 Upload User Flash with Software Tool from Linux Prompt
(Binary file)
Uploading the flash from the development kit platform OS is done using a Linux command line tool. Refer to your
platform VITA 57 BSP for more information. This tool requires a binary file to upload. The ISE Design suite
generate mcs files used to upload flash with JTAG probe (see section 3.2 page 7). A tool is needed to convert
mcs file to bin files that can be uploaded; refer to your platform VITA 57 BSP for more information. The flash
upload is also platform dependant so refer also to Your VITA 57 BSP documentation for more informations about
it.
3.2 Upload User Flash with JTAG Probe (mcs file)
At first, a “mcs” image must be generated, so use the “Impact” tool from the ISE Design Suite to create a “mcs”
file from the “bit” file obtained by the image generation. This could be done only for rescue images in case of
troubleshooting.
Upload a FPGA image when the rescue mode is activated will break the rescue image
So to upload the user FPGA image using JTAG probe:
>Check first the user image is activated, then check the upload via JTAG is allowed: refer to the mother board
(SBC or Carrier) User’s Guide to set the jumper or dip switches.
>Plug the JTAG probe to the JTAG connector.
>Do not boot the board under OS, so enter BIOS/firmware/U-Boot.
>Using “Impact” tool from ISE Design Suite, upload the new image.
>Once done, power cycle the board.
3.3 Upload Flash on FMC
The VITA 57 standard also allows the flash containing the FPGA code to be on the FMC. Kontron Modular
Computers does not to implement flash on current FMC so this feature is not available in the kit.

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Chapter 4 - Troubleshooting
In case of troubleshooting, the user should first revert to the delivered configuration in order to check the health
of the VITA 57 kit.
>Plug the FMC (FMC-SER0) delivered with the VITA 57 package in the FMC slot.
>Activate the FPGA rescue image; to proceed, refer to the mother board (SBC or Carrier) User’s Guide. For
example, VME development kit using a VM6250 board, bit4 of switch5 shall be set to ON.
>Double check flash write protection. Refer to the mother board (SBC or Carrier) User’s Guide to
enable/disable flashes write protection through dip switches or jumper.
>Boot the board and get the user and password from the VITA 57 BSP documentation of the board and log in.
4.1 Configuration Check
This is a basic verification of the installed software:
# rpm −qa | grep VITA57
VITA57_BSP−1.0−2.6.25_10356.vm6250.fc9.ppc.smp.11004.ppc
# rpm −qa | grep kernel
kernel−smp−devel−2.6.25−10356.vm6250.fc9.ppc
kernel−smp−2.6.25−10356.vm6250.fc9.ppc
kernel−bootwrapper−2.6.25−09135.vm6250.fc9.ppc
kernel−devel−2.6.25−09135.vm6250.fc9.ppc
kernel−headers−2.6.25−10355.vm6250.fc9.ppc
4.2 FPGA Check
Launch the following command to check the FPGA presence:
# lspci | grep −i teknor
0000:04:00.0 Memory controller: Teknor Industrial Computers Inc Unknown device
9050 (rev 01)
If there is no output, the FPGA is not reachable; it means that some:
>The FPGA fails and could not fetch the rescue image from the flash.
>The rescue flash is not available.
>The rescue image might be corrupted.
>PCI Xpress accesses fail.

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4.3 FMC EEPROM Check
In order to access the FMC EEPROM run the following command to display the VPD:
# e2fmc−v−W
Product Name [My Board Product Name]
Serial Number [My Board Serial Number]
Part Number []
If the output is the following:
Cannot read eeprom !
The FMC EEPROM could not be reach and some configurations must have failed.
4.4 FMC IOs Check
This check will be done with a loopback wired connector plugged on the FMC-SER0 front panel in order to verify
the IOs available on this front panel (FMC GPIOn and FMC TXn/RXn signals).
4.4.1 FMC GPIOn signals
Set odd FMC GPIOs (GPIO1,3,5,7,9) as outputs, others as inputs:
# gpio −c 9 −s GPIO_Control −v 0x155
Set output GPIOs to 1:
# gpio −c 9 −s GPIO_DataOut −v 0x155
Check the GPIO levels: all must be at level 1 (because they are outputs at level 1, or because thay are inputs
connected to the outputs).
# gpio −c 9 −g GPIO_In
GPIO_In −> 0x000003FF
Set output GPIOs to 0:
# gpio −c 9 −s GPIO_DataOut −v 0x0
Check the GPIO levels: all must be at level 0 (because they are outputs at level 0, or because thay are inputs
connected to the outputs)
# gpio −c 9 −g GPIO_In
GPIO_In −> 0x00000000
#
Set even FMC GPIOs (GPIO2,4,6,8,10) as outputs, others as inputs:
# gpio −c 9 −s GPIO_Control −v 0x2aa

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Set output GPIOs to 1:
# gpio −c 9 −s GPIO_DataOut −v 0x2aa
Check the GPIO levels: all must be at level 1 (because they are outputs at level 1, or because thay are inputs
connected to the outputs).
# gpio −c 9 −g GPIO_In
GPIO_In −> 0x000003FF
Set output GPIOs to 0:
# gpio −c 9 −s GPIO_DataOut −v 0x0
Check the GPIO levels: all must be at level 0 (because they are outputs at level 0, or because thay are inputs
connected to the outputs)
# gpio −c 9 −g GPIO_In
GPIO_In −> 0x00000000
#
>To see the current value of all registers of a channel (binary and hex format), use the -u option. For
example:
# gpio −c 9 −u
****************************************************************
Channel: 9 => 10 GPIOs
****************************************************************
GPIO_Control XXXXXXXXXXXXXXXXXXXXXX1010101010 0x000002AA
GPIO_DataOut XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_In XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntMask XXXXXXXXXXXXXXXXXXXXXX1111111111 0x000003FF
GPIO_IntPolarity XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntMode XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntToggle XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntStatus XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
****************************************************************
GPIO_GlobalStatus 00000000000000000000000000000000
****************************************************************

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>it is also possible to set a register and read back the value of all registers in one command. For example
the following lines :
# gpio −c 9 −s GPIO_DataOut −v 0x2aa
# gpio −c 9 −g GPIO_In
GPIO_In −> 0x000003FF
can be replaced with:
# gpio −c 9 −u −s GPIO_DataOut −v 0x2aa
****************************************************************
Channel: 9 => 10 GPIOs
****************************************************************
GPIO_Control XXXXXXXXXXXXXXXXXXXXXX1010101010 0x000002AA
GPIO_DataOut XXXXXXXXXXXXXXXXXXXXXX1010101010 0x000002AA
GPIO_In XXXXXXXXXXXXXXXXXXXXXX1111111111 0x000003FF
GPIO_IntMask XXXXXXXXXXXXXXXXXXXXXX1111111111 0x000003FF
GPIO_IntPolarity XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntMode XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntToggle XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
GPIO_IntStatus XXXXXXXXXXXXXXXXXXXXXX0000000000 0x00000000
****************************************************************
GPIO_GlobalStatus 00000000000000000000000000000000
****************************************************************
>for more info on "GPIO" command:
# gpio −h
4.4.2 FMC TXn/RXn signals
These signals can be set for RS232 or RS422/485 mode.
On FMC-SER0 PCB B:
>the TXn buffers are enabled by the DXEN (for TX1 to TX14) and DXEN1516 (for TX15 and TX16) signals,
when set to level 1.
>the RS232 or RS422/485 mode is set by switches and can be overridden by software with LED1R_SW1
(TX1/RX1 to TX4/RX4), LED1G_SW2 (TX5/RX5 to TX8/RX8), LED2R_SW3 (TX9/RX9 to TX12/RX12), and
LED2G_SW4 (TX13/RX13 to TX16/RX16). Level 1 for RS422/485; 0 for RS232.
On FMC-SER0 PCB A:
>all TXn buffers are enabled by the DXEN signal when set to level 1 - DXEN1516 is called MODE and selects
RS232 or RS422/485 for all TXn. Level 1 for RS422/485; 0 for RS232.
The procedure below assumes that a FMC-SER0 PCB B is used.

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4.4.2.1 Enable buffers
Set DXEN abd DXEN1516 as outputs:
# gpio −c 8 −s GPIO_Control −v 0x3
Set DXEN and DXEN1516 to level 1 to enable all TXn outputs:
# gpio −c 8 −s GPIO_DataOut −v 0x3
the command above is suitable for FMC-SER0 PCB B. On FMC-SER0 PCB A, the RS232 or RS422/485
mode is controlled by DXEN1516 for all TXn/RXn:
>to set to RS232:
# gpio−c 8 −s GPIO_DataOut −v 0x1
>to set to RS422/485:
# gpio −c 8 −s GPIO_DataOut −v 0x3
4.4.2.2 Test a channel
The test below is done on channel 0: TX1/RX1, TX2/RX2. It must also be done on other channels (1 to 7) by
replacing the "-c 0" with "-c 1" to "-c 7".
Set TX signals as outputs (TX1 and TX2)
# gpio −c 0 −s GPIO_Control −v 0xa

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Check TX/RX signals when configured for RS422/485. The level set on TX1 must be also read on RX1, but
setting a level on TX2 does not change RX2 as we are in differential mode: TX1/TX2 and RX1/RX2 are the same
pair.
# gpio −c 0 −s GPIO_DataOut −v 0x8 # TX1=1, TX2=0
# gpio −c 0 −g GPIO_In # must read TX1=RX1=1, TX2=RX2=0
GPIO_In −> 0x00000009
# gpio −c 0 −s GPIO_DataOut −v 0x2 # TX1=0, TX2=1
# gpio −c 0 −g GPIO_In # must read TX1=RX1=RX2=0, TX2=1
GPIO_In −> 0x00000002
# gpio −c 0 −s GPIO_DataOut −v 0x0 # TX1=0, TX2=0
# gpio −c 0 −g GPIO_In # must read TX1=RX1=TX2=RX2=0
GPIO_In −> 0x00000000
#
Check TX/RX signals when configured for RS232. The level set on TX1 must be also read on RX1, and the level
set on TX2 must be also read on RX2 (TX1/TX2 and RX1/RX2 are independant).
# gpio −c 0 −s GPIO_DataOut −v 0x8 # TX1=1, TX2=0
# gpio −c 0 −g GPIO_In # must read TX1=RX1=1, TX2=RX2=0
GPIO_In −> 0x00000009
# gpio −c 0 −s GPIO_DataOut −v 0x2 # TX1=0, TX2=1
# gpio −c 0 −g GPIO_In # must read TX1=RX1=0, TX2=RX2=1
GPIO_In −> 0x00000006
# gpio −c 0 −s GPIO_DataOut −v 0x0 # TX1=0, TX2=0
# gpio −c 0 −g GPIO_In # must read TX1=RX1=TX2=RX2=0
GPIO_In −> 0x00000000
#

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4.5 Low Level Debug with IO Command
This command can be used to read/write FPGA registers. First, get the FPGA registers physical base address
using "lspci -x":
0000:04:00.0 Memory controller: Teknor Industrial Computers Inc Unknown device
9050 (rev fe)
00: 59 10 50 90 06 00 10 00 fe 00 80 05 08 00 00 00
10: 04 00 00 80 00 00 00 00 00 08 00 80 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 59 10 01 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 42 01 00 00
The 32bit swapped address is stored in BAR2 at PCI configuration offset 0x18. In the example above, the
address is: swap32(0x00080080) = 0x80000800
The examples below assume that FPGA registers are mapped at this address in physical memory.
When reading or writing 32bit data using "IO", the data has to be swapped. This does not apply to the
adress parameter; only to data.
Here is an example with TX1, TX2, RX1 and RX2 using a loopback connector on the FMC-SER0 front panel.
Set VADJ to 3V3 in "REGI0 general purpose" register at offset 0x380 (if not yet done) :
[root@localhost ~]# io −4 −w 0x80000b80 0x08000000
[root@localhost ~]# io −4 −r −l 0x4 0x80000b80
80000b80: 08000000
Set signals controlling buffer output enable as outputs by setting channel 8 "GPIO control" register at offset
0x200 :
[root@localhost ~]# io −4 −w 0x80000a00 0x03000000
[root@localhost ~]# io −4 −r −l 0x4 0x80000a00
80000a00: 03000000
Set signals controling TX1 and TX2 as outputs by setting channel 0 "GPIO control" register at offset 0x000
[root@localhost ~]# io −4 −w 0x80000800 0x0a000000
[root@localhost ~]# io −4 −r −l 0x4 0x80000800
80000800: 0a000000
Enable output of buffers by setting channel 8 "GPIO DataOut" register at offset 0x204:
[root@localhost ~]# io −4 −w 0x80000a04 0x01000000
[root@localhost ~]# io −4 −r −l 0x4 0x80000a04
80000a04: 01000000
If FMC-SER0 is configured for RS422/485:
Set TX1 to 1 by setting channel 0 ”GPIO DataOut” register at offset 0x004 −>
should reread TX1 = 1, but also RX1 = 1 because of loopback, in channel 0
”GPIO DataIn” register at offset 0x008
[root@localhost ~]# io −4 −w 0x80000804 0x08000000
[root@localhost ~]# io −4 −r −l 0x4 0x80000808
80000808: 09000000