LAPIS Semiconductor ML62Q1000 Series User manual

ML62Q1000 Series
ML62Q1300 Group
ML62Q1500 Group
ML62Q1700 Group
User's Manual
Issue Date: Dec 11, 2018
FEUL62Q1000-01

ML62Q1000 Series User's Manual
FEUL62Q1000 i
Notes
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illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account
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http://www.lapis-semi.com/en/

ML62Q1000 Series User's Manual
FEUL62Q1000 ii
Notes for product usage
Notes on this page are applicable to the all microcontroller devices.
For individual notes on each product, refer to [Note] in the chapters of each user's manual.
The description contents on this page take priority over those in the chapters if they are different.
1. HANDLING OF UNUSED INPUT PINS
Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong
operation or increasing the current consumption due to noise, etc. If the handlings for the unused pins are
described in the chapters, follow the instruction.
2. STATE AT POWER ON
At the power on, the data in the internal registers and output of the ports are undefined until the power supply
voltage reaches to the recommended operating condition and "L" level is input to the reset pin.
On the products that have the power on reset function, the data in the internal registers and output of the ports
are undefined until the power on reset is generated.
Be careful to design the application system does not work incorrectly due to the undefined data of internal
registers and output of the ports.
3. ACCESS TO UNUSED MEMORY
If reading from unused address area or writing to unused address area of the memory, the operations are not
guaranteed.

ML62Q1000 Series User's Manual
FEUL62Q1000 iii
Preface
This manual describes the operation of the hardware of the 16-bit microcontroller ML62Q1000 Series.
This manual is for ML62Q1300 group, ML62Q1500 group and ML62Q1700 group.
See other manuals for ML62Q1200 group, ML62Q1400 group and ML62Q1600 group.
The following manuals are also available. Read them as necessary.
nnX-U16/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U16/100 Core.
nMACU8 Assembler Package User's Manual
Description on the method of operating the relocatable assembler, the linker, the librarian, and the
object converter and also on the specifications of the assembler language.
nCCU8 User's Manual
Description on the method of operating the compiler.
nCCU8 Programming Guide
Description on the method of programming.
nCCU8 Language Reference
Description on the language specifications.
nDTU8 Debugger User's Manual
Description on the method of operating the debugger DTU8.
nIDEU8 User's Manual
Description on the integrated development environment IDEU8.
nEASE1000 User's Manual
Description on the on-chip debug emulator EASE1000.
nHTU8 User's Manual
Description on the ROM code data generation tool HTU8.
nMULDIVU8LIB Multiplication and Division Library for U8/U16 Accelerator User's Manual
Description on the MULDIVU8LIB Multiplication and Division Library.
nMultiple Flash Writer MWU16 User's Manual
Description on the Multiple Flash Writer MWU16.

ML62Q1000 Series User's Manual
FEUL62Q1000 iv
Notation
Classification Notation Description
♦Numeric value XXh, XXH, 0xXX Indicates a hexadecimal number.
♦Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
mega-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
♦Terminology "H" level Indicates high level voltage VIH and VOH as specified by the electrical
characteristics.
"L" level Indicates low level voltage VIL and VOL as specified by the electrical
characteristics.
♦Register description
"R/W"indicates that Read/Write attribute. "R" indicates that data can be read and "W" indicates that data can be written.
"R/W"indicates that data can be read or written.
MSB: The highest bit of 16-bit register
LSB: The lowest bit of 16-bit register
Registers that have a word symbol allow the word-access. If writing or reading the registers not using the word symbol,
specify the even number addresses.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Word FHCKMOD
Byte FHCKMODH FHCKMODL
Bit - OUT
C2 OUT C1 OUT C0 - SYSC 2 SYSC 1 SYSC 0 - - - - - - - HOS CM0
R/W R R/W R/W R/W R R/W R/W R/W R R R R R R R R/W
Initial
value 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Initial value after the system reset
Invalid bit: This bit returns "0" for reading and writing to this bit is ignored,
Bit symbol name
Word symbol name
Byte symbol name

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-1
Table of Contents
Chapter 1
1. Overvier..........................................................................................................................................................1-1
1.1 Features........................................................................................................................................................... 1-1
1.2 BLOCK DIAGRAM..................................................................................................................................... 1-16
1.2.1 Block Diagram of ML62Q1300 Group.......................................................................................................1-16
1.2.2 Block Diagram of ML62Q1500 Group.......................................................................................................1-16
1.2.3 Block Diagram of ML62Q1700 Group.......................................................................................................1-16
1.3 PIN...............................................................................................................................................................1-19
1.3.1 Pin Layout....................................................................................................................................................1-19
1.3.2 PIN LIST .....................................................................................................................................................1-37
1.3.3 PIN DESCRIPTION.................................................................................................................................... 1-87
1.3.4 TERMINATION OF UNUSED PINS.........................................................................................................1-94
Chapter 2
2. CPU and Memory Space.................................................................................................................................2-1
2.1 General Description..........................................................................................................................................2-1
2.2 CPU nX-U16/100 .............................................................................................................................................2-3
2.2.1 Wait mode and No-wait mode....................................................................................................................... 2-4
2.3 Coprocessor ................................................................................................................................................... 2-5
2.3.1 Multiplier/ Divider........................................................................................................................................ 2-5
2.3.2 List of Coprocessor General-purpose Registers............................................................................................2-6
2.3.3 How to Use Multiplier/Divider................................................................................................................... 2-11
2.4 Memory Space............................................................................................................................................. 2-12
2.5 Program Memory Space ..............................................................................................................................2-13
2.6 Data Memory Space .................................................................................................................................... 2-16
2.7 Description of Registers............................................................................................................................... 2-36
2.7.1 List of Registers..........................................................................................................................................2-36
2.7.2 Data Segment Register (DSR)....................................................................................................................2-36
2.7.3 Flash Remap Address Register (REMAPADD) .........................................................................................2-37
2.8 Remapping Function.................................................................................................................................... 2-38
2.8.1 Description of Remapping Function........................................................................................................... 2-39
2.8.2 Software Remap..........................................................................................................................................2-39
2.8.3 Code Option Remap .................................................................................................................................... 2-40
Chapter 3
3. Reset Function ................................................................................................................................................3-1
3.1 General Description..........................................................................................................................................3-1
3.1.1 Features.......................................................................................................................................................... 3-1
3.1.2 Configuration.................................................................................................................................................3-2
3.1.3 List of Pins..................................................................................................................................................... 3-3
3.2 Description of Registers.................................................................................................................................... 3-3
3.2.1 List of Registers.............................................................................................................................................3-3
3.2.2 Reset Status Register (RSTAT)..................................................................................................................... 3-4
3.2.3 Safety Function Reset Status Register (SRSTAT).........................................................................................3-6
3.3 Description of Operation .................................................................................................................................. 3-7
3.3.1 Operation of Reset Function..........................................................................................................................3-7
3.3.2 System Reset Mode .......................................................................................................................................3-8
3.3.3 Reset Input Pin Reset.....................................................................................................................................3-8
3.3.4 Power-On Reset.............................................................................................................................................3-9

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-2
Chapter 4
4. Power Management ........................................................................................................................................ 4-1
4.1 General Description.......................................................................................................................................4-1
4.1.1 Features.......................................................................................................................................................... 4-2
4.1.2 Configuration.................................................................................................................................................4-3
4.2 Description of Registers................................................................................................................................. 4-4
4.2.1 List of Registers.............................................................................................................................................4-4
4.2.2 Stop Code Acceptor (STPACP).....................................................................................................................4-5
4.2.3 Standby Control Register (SBYCON)...........................................................................................................4-6
4.2.4 Software Reset Acceptor (SOFTRACP)........................................................................................................4-7
4.2.5 Software Reset Control Register (SOFTRCON) ...........................................................................................4-8
4.2.6 Block Clock Control Register 0 (BCKCON0)............................................................................................... 4-9
4.2.7 Block Clock Control Register 1 (BCKCON1)............................................................................................. 4-10
4.2.8 Block Clock Control Register 2 (BCKCON2)............................................................................................. 4-12
4.2.9 Block Clock Control Register 3 (BCKCON3)............................................................................................. 4-14
4.2.10 Block Reset Control Register 0 (BRECON0)............................................................................................4-15
4.2.11 Block Reset Control Register 1 (BRECON1)............................................................................................4-16
4.2.12 Block Reset Control Register 2 (BRECON2)............................................................................................4-18
4.2.13 Block Reset Control Register 3 (BRECON3)............................................................................................4-20
4.3 Description of Operation ............................................................................................................................. 4-21
4.3.1 Program Run Mode...................................................................................................................................... 4-21
4.3.2 HALT Mode................................................................................................................................................ 4-21
4.3.3 HALT-H mode.............................................................................................................................................4-22
4.3.4 STOP mode.................................................................................................................................................. 4-23
4.3.5 STOP-D Mode.............................................................................................................................................4-24
4.3.6 Note on Return Operation from the Standby Mode.....................................................................................4-25
4.3.7 Operation of Each Function in Standby Mode.............................................................................................4-26
4.3.8 Block Control Function ...............................................................................................................................4-28
Chapter 5
5. Interrupts.........................................................................................................................................................5-1
5.1 General Description.......................................................................................................................................5-1
5.1.1 Features.......................................................................................................................................................... 5-1
5.2 Description of Registers................................................................................................................................. 5-2
5.2.1 List of Registers.............................................................................................................................................5-2
5.2.2 Interrupt Enable Register 01 (IE01)...............................................................................................................5-5
5.2.3 Interrupt Enable Register 23 (IE23)...............................................................................................................5-6
5.2.4 Interrupt Enable Register 45 (IE45)...............................................................................................................5-8
5.2.5 Interrupt Enable Register 67 (IE67)............................................................................................................. 5-10
5.2.6 Interrupt Request Register 01 (IRQ01)........................................................................................................5-12
5.2.7 Interrupt Request Register 23 (IRQ23)........................................................................................................5-14
5.2.8 Interrupt Request Register 45 (IRQ45)........................................................................................................5-16
5.2.9 Interrupt Request Register 67 (IRQ67)........................................................................................................5-18
5.2.10 Interrupt Level Control Enable Register (ILEN).......................................................................................5-20
5.2.11 Current Interrupt Level Management Register (CIL) ................................................................................5-21
5.2.12 Interrupt Level Control Register 0 (ILC0).................................................................................................5-22
5.2.13 Interrupt Level Control Register 1 (ILC1).................................................................................................5-23
5.2.14 Interrupt Level Control Register 2 (ILC2).................................................................................................5-25
5.2.15 Interrupt Level Control Register 3 (ILC3).................................................................................................5-27
5.2.16 Interrupt Level Control Register 4 (ILC4).................................................................................................5-29
5.2.17 Interrupt Level Control Register 5 (ILC5).................................................................................................5-31
5.2.18 Interrupt Level Control Register 6 (ILC6)................................................................................................. 5-33
5.2.19 Interrupt Level Control Register 7 (ILC7)................................................................................................. 5-35
5.3 Description of Operation ............................................................................................................................. 5-37
5.3.1 Maskable Interrupt Processing.....................................................................................................................5-40
5.3.2 Non-Maskable Interrupt Processing ............................................................................................................5-40
5.3.3 Software Interrupt Processing......................................................................................................................5-40

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-3
5.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled)...........................................................5-41
5.3.5 Flow Charts When Interrupt Level Control Is Enabled ...............................................................................5-46
5.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled ..............................................5-48
5.3.7 Interrupt Disable State .................................................................................................................................5-51
Chapter 6
6. Clock Generation Circuit................................................................................................................................ 6-1
6.1 General Description.......................................................................................................................................6-1
6.1.1 Features.......................................................................................................................................................... 6-1
6.1.2 Configuration.................................................................................................................................................6-2
6.1.3 List of Pins..................................................................................................................................................... 6-3
6.2 Description of Registers................................................................................................................................. 6-4
6.2.1 List of Registers.............................................................................................................................................6-4
6.2.2 High-Speed Clock Mode Register (FHCKMOD)..........................................................................................6-5
6.2.3 Low-speed Clock Mode Register (FLMOD).................................................................................................6-7
6.2.4 Clock Control Register (FCON)....................................................................................................................6-8
6.2.5 High-Speed Clock Wake-up Time Setting Register (FHWUPT) .................................................................. 6-9
6.2.6 Backup Control Register (FBUCON).......................................................................................................... 6-10
6.2.7 Backup Clock Status Register (FBUSTAT) ................................................................................................ 6-11
6.2.8 Clock Backup Test Mode Acceptor (FBTACP) ..........................................................................................6-12
6.2.9 Clock Backup Test Mode (FBTCON)......................................................................................................... 6-13
6.2.10 Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ).................................................. 6-14
6.3 Description of Operation ............................................................................................................................. 6-15
6.3.1 Low-Speed Clock ........................................................................................................................................6-15
6.3.2 High-Speed Clock........................................................................................................................................6-21
6.3.3 WDT Clock.................................................................................................................................................. 6-22
6.3.4 Switching of System Clock..........................................................................................................................6-23
6.3.5 Switching Low-speed Clock........................................................................................................................6-25
Chapter 7
7. Low Speed Time Base Counter...................................................................................................................... 7-1
7.1 General Description.......................................................................................................................................7-1
7.1.1 Features.......................................................................................................................................................... 7-1
7.1.2 Configuration.................................................................................................................................................7-2
7.1.3 List of Pins.....................................................................................................................................................7-4
7.2 Description of Registers................................................................................................................................. 7-5
7.2.1 List of Registers............................................................................................................................................. 7-5
7.2.2 Low Speed Time Base Counter Register (LTBR) ......................................................................................... 7-6
7.2.3 Low Speed Time Base Register Control Register (LTBCCON) ...................................................................7-7
7.2.4 Simplified RTC Time Base Counter Register (LTBRR)...............................................................................7-8
7.2.5 Low Speed Time Base Counter frequency adjustment Register (LTBADJ) .............................................. 7-9
7.2.6 Low Speed Time Base Counter Interrupt Selection Register (LTBINT).....................................................7-10
7.3 Description of Operation ............................................................................................................................. 7-12
7.3.1 Low Speed Time Base Counter Operation ..................................................................................................7-12
7.3.2 Low Speed Time Base Counter Frequency Adjustment Function...............................................................7-14
7.3.3 The way of monitoring the frequency on LCD drive outputs......................................................................7-15
Chapter 8
8. 16-Bit Timer ...................................................................................................................................................8-1
8.1 General Description.......................................................................................................................................8-1
8.1.1 Features.......................................................................................................................................................... 8-1
8.1.2 Configuration................................................................................................................................................ 8-3
8.1.3 List of Pin ..................................................................................................................................................... 8-4
8.2 Description of Registers.................................................................................................................................8-5
8.2.1 List of Registers............................................................................................................................................8-5
8.2.2 16-Bit Timer n Data Register (TMHnD: n = 0 to 7)..................................................................................... 8-7
8.2.3 16-Bit Timer n Counter Register (TMHnC: n = 0 to 7)................................................................................8-8

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-4
8.2.4 16-Bit Timer n Mode Register (TMHnMOD: n = 0 to 7)............................................................................. 8-9
8.2.5 16-Bit Timer n Interrupt Status Register (TMHnIS: n = 0 to 7).................................................................8-11
8.2.6 16-Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7)..................................................................8-12
8.2.7 16-Bit Timer Start Register (TMHSTR)..................................................................................................... 8-13
8.2.8 16-Bit Timer Stop Register (TMHSTP) ..................................................................................................... 8-15
8.2.9 16-Bit Timer Status Register (TMHSTAT)................................................................................................8-17
8.3 Description of Operation ............................................................................................................................. 8-19
8.3.1 16-Bit Timer Mode......................................................................................................................................8-19
8.3.2 8-Bit Timer Mode.......................................................................................................................................8-22
8.3.3 Common Operation ....................................................................................................................................8-27
Chapter 9
9. Functional Timer.............................................................................................................................................9-1
9.1 General Description.......................................................................................................................................9-1
9.1.1 Features.........................................................................................................................................................9-3
9.1.2 Configuration................................................................................................................................................ 9-4
9.1.3 List of Pins....................................................................................................................................................9-5
9.2 Description of Registers.................................................................................................................................9-7
9.2.1 List of Registers............................................................................................................................................ 9-7
9.2.2 FTMn Cycle Register (FTnP: n = 0 to 7).................................................................................................... 9-12
9.2.3 FTMn Event Register A (FTnEA: n = 0 to 7).............................................................................................9-13
9.2.4 FTMn Event Register B (FTnEB: n = 0 to 7)............................................................................................. 9-14
9.2.5 FTMn Dead Time Register (FTnDT: n = 0 to 7)........................................................................................9-15
9.2.6 FTMn Counter Register (FTnC: n = 0 to 7)................................................................................................9-16
9.2.7 FTMn Status Register (FTnSTAT: n = 0 to 7) ...........................................................................................9-17
9.2.8 FTMn Mode Register (FTnMOD: n = 0 to 7).............................................................................................9-18
9.2.9 FTMn Clock Register (FTnCLK: n= 0 to 7)...............................................................................................9-20
9.2.10 FTMn Trigger Register 0 (FTnTRG0: n = 0 to 7) .....................................................................................9-22
9.2.11 FTMn Trigger Register 1 (FTnTRG1: n = 0 to 7) .....................................................................................9-25
9.2.12 FTMn Interrupt Enable Register (FTnINTE: n = 0 to 7) ...........................................................................9-27
9.2.13 FTMn Interrupt Status Register (FTnINTS: n = 0 to 7).............................................................................9-29
9.2.14 FTMn Interrupt Clear Register (FTnINTC: n = 0 to 7) ............................................................................. 9-31
9.2.15 FTM Common Update Register (FTCUD)................................................................................................9-32
9.2.16 FTM Common Control Register (FTCCON)............................................................................................. 9-33
9.2.17 FTM Common Start Register (FTCSTR) .................................................................................................. 9-34
9.2.18 FTM Common Stop Register (FTCSTP)...................................................................................................9-35
9.2.19 FTM Common Status Register (FTCSTAT) ............................................................................................. 9-36
9.3 Description of Operation ............................................................................................................................. 9-37
9.3.1 Common Sequence (Initial setting Common to All Modes)....................................................................... 9-37
9.3.2 Counter Operation (Common to All Modes)..............................................................................................9-39
9.3.3 TIMER Mode Operation............................................................................................................................. 9-40
9.3.4 CAPTURE Mode Operation.......................................................................................................................9-44
9.3.5 PWM1 Mode Operation .............................................................................................................................9-47
9.3.6 PWM2 Mode Operation ............................................................................................................................. 9-51
9.3.7 Event Trigger/Emergency Stop Trigger Control ........................................................................................ 9-56
9.3.8 Output at Counter Stop...............................................................................................................................9-59
9.3.9 Changing Cycle, Event A/B, and Dead Time during Operation.................................................................9-60
9.3.10 Interrupt Source.........................................................................................................................................9-62
Chapter 10
10. Watchdog Timer ...........................................................................................................................................10-1
10.1 General Description................................................................................................................................... 10-1
10.1.1 Features......................................................................................................................................................10-2
10.1.2 Configuration.............................................................................................................................................10-3
10.2 Description of Registers.............................................................................................................................10-4
10.2.1 List of Registers......................................................................................................................................... 10-4
10.2.2 Watchdog Timer Control Register (WDTCON)........................................................................................10-5

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-5
10.2.3 Watchdog Timer Mode Register (WDTMOD)..........................................................................................10-6
10.2.4 Watchdog Timer Counter Register (WDTMC).........................................................................................10-7
10.2.5 Watchdog Status Register (WDTSTA)......................................................................................................10-8
10.3 Description of Operation ........................................................................................................................... 10-9
10.3.1 How to Clear WDT Counter.................................................................................................................... 10-10
10.3.2 Window Function Disabled Mode........................................................................................................... 10-12
10.3.3 Window Function Enabled Mode............................................................................................................10-16
Chapter 11
11. Serial Communication Unit.......................................................................................................................... 11-1
11.1 General Description................................................................................................................................... 11-1
11.1.1 Features......................................................................................................................................................11-1
11.1.2 Configuration.............................................................................................................................................11-3
11.1.3 List of Pins.................................................................................................................................................11-4
11.1.4 Combination of SSIO port.........................................................................................................................11-8
11.1.5 Combination of UART port.......................................................................................................................11-8
11.2 Description of Registers.............................................................................................................................11-9
11.2.1 List of Registers......................................................................................................................................... 11-9
11.2.2 Serial Communication Unit n Transmit/Receive Buffer (SDnBUF) ....................................................... 11-16
11.2.3 Serial Communication Unit n Mode Register (SUnMOD)...................................................................... 11-18
11.2.4 Serial Communication Unit n Transmission Interval Setting Register (SUnDLY) ................................. 11-19
11.2.5 Serial Communication Unit n Control Register (SUnCON)....................................................................11-21
11.2.6 Synchronous Serial Port n Mode Register (SIOnMOD).......................................................................... 11-22
11.2.7 Synchronous Serial Port n Status Register (SIOnSTAT)......................................................................... 11-24
11.2.8 UARTn0 Mode Register (UAn0MOD) ................................................................................................... 11-26
11.2.9 UARTn1 Mode Register (UAn1MOD) ................................................................................................... 11-28
11.2.10 UARTn0 Baud Rate Register (UAn0BRT) ...........................................................................................11-30
11.2.11 UARTn1 Baud Rate Register (UAn1BRT) ...........................................................................................11-30
11.2.12 UARTn0 Baud Rate Adjustment Register (UAn0BRC)........................................................................ 11-31
11.2.13 UARTn1 Baud Rate Adjustment Register (UAn1BRC)........................................................................ 11-31
11.2.14 UARTn0 Status Register (UAn0STAT)................................................................................................11-32
11.2.15 UARTn1 Status Register (UAn1STAT)................................................................................................11-34
11.3 Description of Operation ......................................................................................................................... 11-36
11.3.1 Synchronous Serial Port (SSIO) .............................................................................................................. 11-36
11.3.2 Asynchronous Serial Interface (UART) .................................................................................................. 11-45
Chapter 12
12. I2C Bus Unit.................................................................................................................................................12-1
12.1 General Description................................................................................................................................... 12-1
12.1.1 Features......................................................................................................................................................12-1
12.1.2 Configuration.............................................................................................................................................12-2
12.1.3 List of Pins................................................................................................................................................. 12-3
12.1.4 Pin Setting.................................................................................................................................................. 12-3
12.2 Description of Registers.............................................................................................................................12-4
12.2.1 List of Registers.........................................................................................................................................12-4
12.2.2 I2C Bus Unit 0 Mode Register (I2U0MSS)...............................................................................................12-5
12.2.3 I2C Bus 0 Receive Register (Master) (I2UM0RD)....................................................................................12-6
12.2.4 I2C Bus 0 Slave Address Register (Master) (I2UM0SA)..........................................................................12-7
12.2.5 I2C Bus 0 Transmit Data Register (Master) (I2UM0TD).......................................................................... 12-8
12.2.6 I2C Bus 0 Control Register (Master) (I2UM0CON) .................................................................................12-9
12.2.7 I2C Bus 0 Mode Register (Master) (I2UM0MOD) ................................................................................. 12-10
12.2.8 I2C Bus 0 Status Register (Master) (I2UM0STR)................................................................................... 12-12
12.2.9 I2C Bus 0 Receive Register (Slave) (I2US0RD).....................................................................................12-14
12.2.10 I2C Bus 0 Slave Address Register (Slave) (I2US0SA)..........................................................................12-15
12.2.11 I2C Bus 0 Transmit Data Register (Slave) (I2US0TD).........................................................................12-16
12.2.12 I2C Bus 0 Control Register (Slave) (I2US0CON).................................................................................12-17
12.2.13 I2C Bus 0 Mode Register (Slave) (I2US0MD)...................................................................................... 12-18