LAPIS Semiconductor ML62Q1000 Series User manual

ML62Q1000 Series
ML62Q1300 Group
ML62Q1500 Group
ML62Q1700 Group
User's Manual
Issue Date: Dec 11, 2018
FEUL62Q1000-01

ML62Q1000 Series User's Manual
FEUL62Q1000 i
Notes
1) The information contained herein is subject to change without notice.
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3) Examples of application circuits, circuit constants and any other information contained herein are provided only to
illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account
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http://www.lapis-semi.com/en/

ML62Q1000 Series User's Manual
FEUL62Q1000 ii
Notes for product usage
Notes on this page are applicable to the all microcontroller devices.
For individual notes on each product, refer to [Note] in the chapters of each user's manual.
The description contents on this page take priority over those in the chapters if they are different.
1. HANDLING OF UNUSED INPUT PINS
Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong
operation or increasing the current consumption due to noise, etc. If the handlings for the unused pins are
described in the chapters, follow the instruction.
2. STATE AT POWER ON
At the power on, the data in the internal registers and output of the ports are undefined until the power supply
voltage reaches to the recommended operating condition and "L" level is input to the reset pin.
On the products that have the power on reset function, the data in the internal registers and output of the ports
are undefined until the power on reset is generated.
Be careful to design the application system does not work incorrectly due to the undefined data of internal
registers and output of the ports.
3. ACCESS TO UNUSED MEMORY
If reading from unused address area or writing to unused address area of the memory, the operations are not
guaranteed.

ML62Q1000 Series User's Manual
FEUL62Q1000 iii
Preface
This manual describes the operation of the hardware of the 16-bit microcontroller ML62Q1000 Series.
This manual is for ML62Q1300 group, ML62Q1500 group and ML62Q1700 group.
See other manuals for ML62Q1200 group, ML62Q1400 group and ML62Q1600 group.
The following manuals are also available. Read them as necessary.
nnX-U16/100 Core Instruction Manual
Description on the basic architecture and the each instruction of the nX-U16/100 Core.
nMACU8 Assembler Package User's Manual
Description on the method of operating the relocatable assembler, the linker, the librarian, and the
object converter and also on the specifications of the assembler language.
nCCU8 User's Manual
Description on the method of operating the compiler.
nCCU8 Programming Guide
Description on the method of programming.
nCCU8 Language Reference
Description on the language specifications.
nDTU8 Debugger User's Manual
Description on the method of operating the debugger DTU8.
nIDEU8 User's Manual
Description on the integrated development environment IDEU8.
nEASE1000 User's Manual
Description on the on-chip debug emulator EASE1000.
nHTU8 User's Manual
Description on the ROM code data generation tool HTU8.
nMULDIVU8LIB Multiplication and Division Library for U8/U16 Accelerator User's Manual
Description on the MULDIVU8LIB Multiplication and Division Library.
nMultiple Flash Writer MWU16 User's Manual
Description on the Multiple Flash Writer MWU16.

ML62Q1000 Series User's Manual
FEUL62Q1000 iv
Notation
Classification Notation Description
♦Numeric value XXh, XXH, 0xXX Indicates a hexadecimal number.
♦Unit word, W 1 word = 16 bits
byte, B 1 byte = 8 bits
nibble, N 1 nibble = 4 bits
mega-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
♦Terminology "H" level Indicates high level voltage VIH and VOH as specified by the electrical
characteristics.
"L" level Indicates low level voltage VIL and VOL as specified by the electrical
characteristics.
♦Register description
"R/W"indicates that Read/Write attribute. "R" indicates that data can be read and "W" indicates that data can be written.
"R/W"indicates that data can be read or written.
MSB: The highest bit of 16-bit register
LSB: The lowest bit of 16-bit register
Registers that have a word symbol allow the word-access. If writing or reading the registers not using the word symbol,
specify the even number addresses.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Word FHCKMOD
Byte FHCKMODH FHCKMODL
Bit - OUT
C2 OUT C1 OUT C0 - SYSC 2 SYSC 1 SYSC 0 - - - - - - - HOS CM0
R/W R R/W R/W R/W R R/W R/W R/W R R R R R R R R/W
Initial
value 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Initial value after the system reset
Invalid bit: This bit returns "0" for reading and writing to this bit is ignored,
Bit symbol name
Word symbol name
Byte symbol name

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-1
Table of Contents
Chapter 1
1. Overvier..........................................................................................................................................................1-1
1.1 Features........................................................................................................................................................... 1-1
1.2 BLOCK DIAGRAM..................................................................................................................................... 1-16
1.2.1 Block Diagram of ML62Q1300 Group.......................................................................................................1-16
1.2.2 Block Diagram of ML62Q1500 Group.......................................................................................................1-16
1.2.3 Block Diagram of ML62Q1700 Group.......................................................................................................1-16
1.3 PIN...............................................................................................................................................................1-19
1.3.1 Pin Layout....................................................................................................................................................1-19
1.3.2 PIN LIST .....................................................................................................................................................1-37
1.3.3 PIN DESCRIPTION.................................................................................................................................... 1-87
1.3.4 TERMINATION OF UNUSED PINS.........................................................................................................1-94
Chapter 2
2. CPU and Memory Space.................................................................................................................................2-1
2.1 General Description..........................................................................................................................................2-1
2.2 CPU nX-U16/100 .............................................................................................................................................2-3
2.2.1 Wait mode and No-wait mode....................................................................................................................... 2-4
2.3 Coprocessor ................................................................................................................................................... 2-5
2.3.1 Multiplier/ Divider........................................................................................................................................ 2-5
2.3.2 List of Coprocessor General-purpose Registers............................................................................................2-6
2.3.3 How to Use Multiplier/Divider................................................................................................................... 2-11
2.4 Memory Space............................................................................................................................................. 2-12
2.5 Program Memory Space ..............................................................................................................................2-13
2.6 Data Memory Space .................................................................................................................................... 2-16
2.7 Description of Registers............................................................................................................................... 2-36
2.7.1 List of Registers..........................................................................................................................................2-36
2.7.2 Data Segment Register (DSR)....................................................................................................................2-36
2.7.3 Flash Remap Address Register (REMAPADD) .........................................................................................2-37
2.8 Remapping Function.................................................................................................................................... 2-38
2.8.1 Description of Remapping Function........................................................................................................... 2-39
2.8.2 Software Remap..........................................................................................................................................2-39
2.8.3 Code Option Remap .................................................................................................................................... 2-40
Chapter 3
3. Reset Function ................................................................................................................................................3-1
3.1 General Description..........................................................................................................................................3-1
3.1.1 Features.......................................................................................................................................................... 3-1
3.1.2 Configuration.................................................................................................................................................3-2
3.1.3 List of Pins..................................................................................................................................................... 3-3
3.2 Description of Registers.................................................................................................................................... 3-3
3.2.1 List of Registers.............................................................................................................................................3-3
3.2.2 Reset Status Register (RSTAT)..................................................................................................................... 3-4
3.2.3 Safety Function Reset Status Register (SRSTAT).........................................................................................3-6
3.3 Description of Operation .................................................................................................................................. 3-7
3.3.1 Operation of Reset Function..........................................................................................................................3-7
3.3.2 System Reset Mode .......................................................................................................................................3-8
3.3.3 Reset Input Pin Reset.....................................................................................................................................3-8
3.3.4 Power-On Reset.............................................................................................................................................3-9

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-2
Chapter 4
4. Power Management ........................................................................................................................................ 4-1
4.1 General Description.......................................................................................................................................4-1
4.1.1 Features.......................................................................................................................................................... 4-2
4.1.2 Configuration.................................................................................................................................................4-3
4.2 Description of Registers................................................................................................................................. 4-4
4.2.1 List of Registers.............................................................................................................................................4-4
4.2.2 Stop Code Acceptor (STPACP).....................................................................................................................4-5
4.2.3 Standby Control Register (SBYCON)...........................................................................................................4-6
4.2.4 Software Reset Acceptor (SOFTRACP)........................................................................................................4-7
4.2.5 Software Reset Control Register (SOFTRCON) ...........................................................................................4-8
4.2.6 Block Clock Control Register 0 (BCKCON0)............................................................................................... 4-9
4.2.7 Block Clock Control Register 1 (BCKCON1)............................................................................................. 4-10
4.2.8 Block Clock Control Register 2 (BCKCON2)............................................................................................. 4-12
4.2.9 Block Clock Control Register 3 (BCKCON3)............................................................................................. 4-14
4.2.10 Block Reset Control Register 0 (BRECON0)............................................................................................4-15
4.2.11 Block Reset Control Register 1 (BRECON1)............................................................................................4-16
4.2.12 Block Reset Control Register 2 (BRECON2)............................................................................................4-18
4.2.13 Block Reset Control Register 3 (BRECON3)............................................................................................4-20
4.3 Description of Operation ............................................................................................................................. 4-21
4.3.1 Program Run Mode...................................................................................................................................... 4-21
4.3.2 HALT Mode................................................................................................................................................ 4-21
4.3.3 HALT-H mode.............................................................................................................................................4-22
4.3.4 STOP mode.................................................................................................................................................. 4-23
4.3.5 STOP-D Mode.............................................................................................................................................4-24
4.3.6 Note on Return Operation from the Standby Mode.....................................................................................4-25
4.3.7 Operation of Each Function in Standby Mode.............................................................................................4-26
4.3.8 Block Control Function ...............................................................................................................................4-28
Chapter 5
5. Interrupts.........................................................................................................................................................5-1
5.1 General Description.......................................................................................................................................5-1
5.1.1 Features.......................................................................................................................................................... 5-1
5.2 Description of Registers................................................................................................................................. 5-2
5.2.1 List of Registers.............................................................................................................................................5-2
5.2.2 Interrupt Enable Register 01 (IE01)...............................................................................................................5-5
5.2.3 Interrupt Enable Register 23 (IE23)...............................................................................................................5-6
5.2.4 Interrupt Enable Register 45 (IE45)...............................................................................................................5-8
5.2.5 Interrupt Enable Register 67 (IE67)............................................................................................................. 5-10
5.2.6 Interrupt Request Register 01 (IRQ01)........................................................................................................5-12
5.2.7 Interrupt Request Register 23 (IRQ23)........................................................................................................5-14
5.2.8 Interrupt Request Register 45 (IRQ45)........................................................................................................5-16
5.2.9 Interrupt Request Register 67 (IRQ67)........................................................................................................5-18
5.2.10 Interrupt Level Control Enable Register (ILEN).......................................................................................5-20
5.2.11 Current Interrupt Level Management Register (CIL) ................................................................................5-21
5.2.12 Interrupt Level Control Register 0 (ILC0).................................................................................................5-22
5.2.13 Interrupt Level Control Register 1 (ILC1).................................................................................................5-23
5.2.14 Interrupt Level Control Register 2 (ILC2).................................................................................................5-25
5.2.15 Interrupt Level Control Register 3 (ILC3).................................................................................................5-27
5.2.16 Interrupt Level Control Register 4 (ILC4).................................................................................................5-29
5.2.17 Interrupt Level Control Register 5 (ILC5).................................................................................................5-31
5.2.18 Interrupt Level Control Register 6 (ILC6)................................................................................................. 5-33
5.2.19 Interrupt Level Control Register 7 (ILC7)................................................................................................. 5-35
5.3 Description of Operation ............................................................................................................................. 5-37
5.3.1 Maskable Interrupt Processing.....................................................................................................................5-40
5.3.2 Non-Maskable Interrupt Processing ............................................................................................................5-40
5.3.3 Software Interrupt Processing......................................................................................................................5-40

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-3
5.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled)...........................................................5-41
5.3.5 Flow Charts When Interrupt Level Control Is Enabled ...............................................................................5-46
5.3.6 How To Write Interrupt Processing When Interrupt Level Control Enabled ..............................................5-48
5.3.7 Interrupt Disable State .................................................................................................................................5-51
Chapter 6
6. Clock Generation Circuit................................................................................................................................ 6-1
6.1 General Description.......................................................................................................................................6-1
6.1.1 Features.......................................................................................................................................................... 6-1
6.1.2 Configuration.................................................................................................................................................6-2
6.1.3 List of Pins..................................................................................................................................................... 6-3
6.2 Description of Registers................................................................................................................................. 6-4
6.2.1 List of Registers.............................................................................................................................................6-4
6.2.2 High-Speed Clock Mode Register (FHCKMOD)..........................................................................................6-5
6.2.3 Low-speed Clock Mode Register (FLMOD).................................................................................................6-7
6.2.4 Clock Control Register (FCON)....................................................................................................................6-8
6.2.5 High-Speed Clock Wake-up Time Setting Register (FHWUPT) .................................................................. 6-9
6.2.6 Backup Control Register (FBUCON).......................................................................................................... 6-10
6.2.7 Backup Clock Status Register (FBUSTAT) ................................................................................................ 6-11
6.2.8 Clock Backup Test Mode Acceptor (FBTACP) ..........................................................................................6-12
6.2.9 Clock Backup Test Mode (FBTCON)......................................................................................................... 6-13
6.2.10 Low-Speed RC Oscillation Frequency Adjustment Register (LRCADJ).................................................. 6-14
6.3 Description of Operation ............................................................................................................................. 6-15
6.3.1 Low-Speed Clock ........................................................................................................................................6-15
6.3.2 High-Speed Clock........................................................................................................................................6-21
6.3.3 WDT Clock.................................................................................................................................................. 6-22
6.3.4 Switching of System Clock..........................................................................................................................6-23
6.3.5 Switching Low-speed Clock........................................................................................................................6-25
Chapter 7
7. Low Speed Time Base Counter...................................................................................................................... 7-1
7.1 General Description.......................................................................................................................................7-1
7.1.1 Features.......................................................................................................................................................... 7-1
7.1.2 Configuration.................................................................................................................................................7-2
7.1.3 List of Pins.....................................................................................................................................................7-4
7.2 Description of Registers................................................................................................................................. 7-5
7.2.1 List of Registers............................................................................................................................................. 7-5
7.2.2 Low Speed Time Base Counter Register (LTBR) ......................................................................................... 7-6
7.2.3 Low Speed Time Base Register Control Register (LTBCCON) ...................................................................7-7
7.2.4 Simplified RTC Time Base Counter Register (LTBRR)...............................................................................7-8
7.2.5 Low Speed Time Base Counter frequency adjustment Register (LTBADJ) .............................................. 7-9
7.2.6 Low Speed Time Base Counter Interrupt Selection Register (LTBINT).....................................................7-10
7.3 Description of Operation ............................................................................................................................. 7-12
7.3.1 Low Speed Time Base Counter Operation ..................................................................................................7-12
7.3.2 Low Speed Time Base Counter Frequency Adjustment Function...............................................................7-14
7.3.3 The way of monitoring the frequency on LCD drive outputs......................................................................7-15
Chapter 8
8. 16-Bit Timer ...................................................................................................................................................8-1
8.1 General Description.......................................................................................................................................8-1
8.1.1 Features.......................................................................................................................................................... 8-1
8.1.2 Configuration................................................................................................................................................ 8-3
8.1.3 List of Pin ..................................................................................................................................................... 8-4
8.2 Description of Registers.................................................................................................................................8-5
8.2.1 List of Registers............................................................................................................................................8-5
8.2.2 16-Bit Timer n Data Register (TMHnD: n = 0 to 7)..................................................................................... 8-7
8.2.3 16-Bit Timer n Counter Register (TMHnC: n = 0 to 7)................................................................................8-8

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-4
8.2.4 16-Bit Timer n Mode Register (TMHnMOD: n = 0 to 7)............................................................................. 8-9
8.2.5 16-Bit Timer n Interrupt Status Register (TMHnIS: n = 0 to 7).................................................................8-11
8.2.6 16-Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7)..................................................................8-12
8.2.7 16-Bit Timer Start Register (TMHSTR)..................................................................................................... 8-13
8.2.8 16-Bit Timer Stop Register (TMHSTP) ..................................................................................................... 8-15
8.2.9 16-Bit Timer Status Register (TMHSTAT)................................................................................................8-17
8.3 Description of Operation ............................................................................................................................. 8-19
8.3.1 16-Bit Timer Mode......................................................................................................................................8-19
8.3.2 8-Bit Timer Mode.......................................................................................................................................8-22
8.3.3 Common Operation ....................................................................................................................................8-27
Chapter 9
9. Functional Timer.............................................................................................................................................9-1
9.1 General Description.......................................................................................................................................9-1
9.1.1 Features.........................................................................................................................................................9-3
9.1.2 Configuration................................................................................................................................................ 9-4
9.1.3 List of Pins....................................................................................................................................................9-5
9.2 Description of Registers.................................................................................................................................9-7
9.2.1 List of Registers............................................................................................................................................ 9-7
9.2.2 FTMn Cycle Register (FTnP: n = 0 to 7).................................................................................................... 9-12
9.2.3 FTMn Event Register A (FTnEA: n = 0 to 7).............................................................................................9-13
9.2.4 FTMn Event Register B (FTnEB: n = 0 to 7)............................................................................................. 9-14
9.2.5 FTMn Dead Time Register (FTnDT: n = 0 to 7)........................................................................................9-15
9.2.6 FTMn Counter Register (FTnC: n = 0 to 7)................................................................................................9-16
9.2.7 FTMn Status Register (FTnSTAT: n = 0 to 7) ...........................................................................................9-17
9.2.8 FTMn Mode Register (FTnMOD: n = 0 to 7).............................................................................................9-18
9.2.9 FTMn Clock Register (FTnCLK: n= 0 to 7)...............................................................................................9-20
9.2.10 FTMn Trigger Register 0 (FTnTRG0: n = 0 to 7) .....................................................................................9-22
9.2.11 FTMn Trigger Register 1 (FTnTRG1: n = 0 to 7) .....................................................................................9-25
9.2.12 FTMn Interrupt Enable Register (FTnINTE: n = 0 to 7) ...........................................................................9-27
9.2.13 FTMn Interrupt Status Register (FTnINTS: n = 0 to 7).............................................................................9-29
9.2.14 FTMn Interrupt Clear Register (FTnINTC: n = 0 to 7) ............................................................................. 9-31
9.2.15 FTM Common Update Register (FTCUD)................................................................................................9-32
9.2.16 FTM Common Control Register (FTCCON)............................................................................................. 9-33
9.2.17 FTM Common Start Register (FTCSTR) .................................................................................................. 9-34
9.2.18 FTM Common Stop Register (FTCSTP)...................................................................................................9-35
9.2.19 FTM Common Status Register (FTCSTAT) ............................................................................................. 9-36
9.3 Description of Operation ............................................................................................................................. 9-37
9.3.1 Common Sequence (Initial setting Common to All Modes)....................................................................... 9-37
9.3.2 Counter Operation (Common to All Modes)..............................................................................................9-39
9.3.3 TIMER Mode Operation............................................................................................................................. 9-40
9.3.4 CAPTURE Mode Operation.......................................................................................................................9-44
9.3.5 PWM1 Mode Operation .............................................................................................................................9-47
9.3.6 PWM2 Mode Operation ............................................................................................................................. 9-51
9.3.7 Event Trigger/Emergency Stop Trigger Control ........................................................................................ 9-56
9.3.8 Output at Counter Stop...............................................................................................................................9-59
9.3.9 Changing Cycle, Event A/B, and Dead Time during Operation.................................................................9-60
9.3.10 Interrupt Source.........................................................................................................................................9-62
Chapter 10
10. Watchdog Timer ...........................................................................................................................................10-1
10.1 General Description................................................................................................................................... 10-1
10.1.1 Features......................................................................................................................................................10-2
10.1.2 Configuration.............................................................................................................................................10-3
10.2 Description of Registers.............................................................................................................................10-4
10.2.1 List of Registers......................................................................................................................................... 10-4
10.2.2 Watchdog Timer Control Register (WDTCON)........................................................................................10-5

ML62Q1000 Series User's Manual
Contents
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10.2.3 Watchdog Timer Mode Register (WDTMOD)..........................................................................................10-6
10.2.4 Watchdog Timer Counter Register (WDTMC).........................................................................................10-7
10.2.5 Watchdog Status Register (WDTSTA)......................................................................................................10-8
10.3 Description of Operation ........................................................................................................................... 10-9
10.3.1 How to Clear WDT Counter.................................................................................................................... 10-10
10.3.2 Window Function Disabled Mode........................................................................................................... 10-12
10.3.3 Window Function Enabled Mode............................................................................................................10-16
Chapter 11
11. Serial Communication Unit.......................................................................................................................... 11-1
11.1 General Description................................................................................................................................... 11-1
11.1.1 Features......................................................................................................................................................11-1
11.1.2 Configuration.............................................................................................................................................11-3
11.1.3 List of Pins.................................................................................................................................................11-4
11.1.4 Combination of SSIO port.........................................................................................................................11-8
11.1.5 Combination of UART port.......................................................................................................................11-8
11.2 Description of Registers.............................................................................................................................11-9
11.2.1 List of Registers......................................................................................................................................... 11-9
11.2.2 Serial Communication Unit n Transmit/Receive Buffer (SDnBUF) ....................................................... 11-16
11.2.3 Serial Communication Unit n Mode Register (SUnMOD)...................................................................... 11-18
11.2.4 Serial Communication Unit n Transmission Interval Setting Register (SUnDLY) ................................. 11-19
11.2.5 Serial Communication Unit n Control Register (SUnCON)....................................................................11-21
11.2.6 Synchronous Serial Port n Mode Register (SIOnMOD).......................................................................... 11-22
11.2.7 Synchronous Serial Port n Status Register (SIOnSTAT)......................................................................... 11-24
11.2.8 UARTn0 Mode Register (UAn0MOD) ................................................................................................... 11-26
11.2.9 UARTn1 Mode Register (UAn1MOD) ................................................................................................... 11-28
11.2.10 UARTn0 Baud Rate Register (UAn0BRT) ...........................................................................................11-30
11.2.11 UARTn1 Baud Rate Register (UAn1BRT) ...........................................................................................11-30
11.2.12 UARTn0 Baud Rate Adjustment Register (UAn0BRC)........................................................................ 11-31
11.2.13 UARTn1 Baud Rate Adjustment Register (UAn1BRC)........................................................................ 11-31
11.2.14 UARTn0 Status Register (UAn0STAT)................................................................................................11-32
11.2.15 UARTn1 Status Register (UAn1STAT)................................................................................................11-34
11.3 Description of Operation ......................................................................................................................... 11-36
11.3.1 Synchronous Serial Port (SSIO) .............................................................................................................. 11-36
11.3.2 Asynchronous Serial Interface (UART) .................................................................................................. 11-45
Chapter 12
12. I2C Bus Unit.................................................................................................................................................12-1
12.1 General Description................................................................................................................................... 12-1
12.1.1 Features......................................................................................................................................................12-1
12.1.2 Configuration.............................................................................................................................................12-2
12.1.3 List of Pins................................................................................................................................................. 12-3
12.1.4 Pin Setting.................................................................................................................................................. 12-3
12.2 Description of Registers.............................................................................................................................12-4
12.2.1 List of Registers.........................................................................................................................................12-4
12.2.2 I2C Bus Unit 0 Mode Register (I2U0MSS)...............................................................................................12-5
12.2.3 I2C Bus 0 Receive Register (Master) (I2UM0RD)....................................................................................12-6
12.2.4 I2C Bus 0 Slave Address Register (Master) (I2UM0SA)..........................................................................12-7
12.2.5 I2C Bus 0 Transmit Data Register (Master) (I2UM0TD).......................................................................... 12-8
12.2.6 I2C Bus 0 Control Register (Master) (I2UM0CON) .................................................................................12-9
12.2.7 I2C Bus 0 Mode Register (Master) (I2UM0MOD) ................................................................................. 12-10
12.2.8 I2C Bus 0 Status Register (Master) (I2UM0STR)................................................................................... 12-12
12.2.9 I2C Bus 0 Receive Register (Slave) (I2US0RD).....................................................................................12-14
12.2.10 I2C Bus 0 Slave Address Register (Slave) (I2US0SA)..........................................................................12-15
12.2.11 I2C Bus 0 Transmit Data Register (Slave) (I2US0TD).........................................................................12-16
12.2.12 I2C Bus 0 Control Register (Slave) (I2US0CON).................................................................................12-17
12.2.13 I2C Bus 0 Mode Register (Slave) (I2US0MD)...................................................................................... 12-18

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12.2.14 I2C Bus 0 Status Register (Slave) (I2US0STA) ....................................................................................12-19
12.3 Description of Operation ......................................................................................................................... 12-21
12.3.1 Master Operation.....................................................................................................................................12-21
12.3.2 Master Mode Communication Operation Timing.................................................................................... 12-25
12.3.3 Slave Operation .......................................................................................................................................12-27
12.3.4 Slave Mode Communication Operation Timing...................................................................................... 12-31
12.3.5 Operation Waveforms..............................................................................................................................12-33
Chapter 13
13. I2C Master ....................................................................................................................................................13-1
13.1 General Description................................................................................................................................... 13-1
13.1.1 Features......................................................................................................................................................13-1
13.1.2 Configuration.............................................................................................................................................13-2
13.1.3 List of Pins................................................................................................................................................. 13-3
13.1.4 Pin Setting..................................................................................................................................................13-3
13.2 Description of Registers............................................................................................................................. 13-4
13.2.1 List of Registers......................................................................................................................................... 13-4
13.2.2 I2C Master n Receive Register (I2MnRD:n=0,1)...................................................................................... 13-5
13.2.3 I2C Master n Slave Address Register (I2MnSA:n=0,1) ............................................................................13-6
13.2.4 I2C Master n Transmit Data Register (I2MnTD:n=0,1)............................................................................13-7
13.2.5 I2C Master n Control Register (I2MnCON:n=0,1).................................................................................... 13-8
13.2.6 I2C Master n Mode Register (I2MnMOD:n=0,1)...................................................................................... 13-9
13.2.7 I2C Master n Status Register (I2MnSTAT: n=0,1)..................................................................................13-11
13.3 Description of Operation ......................................................................................................................... 13-13
13.3.1 Master Operation..................................................................................................................................... 13-13
13.3.2 Communication Operation Timing..........................................................................................................13-17
13.3.3 Operation Waveforms.............................................................................................................................. 13-19
Chapter 14
14. DMA Controller............................................................................................................................................14-1
14.1 General Description...................................................................................................................................14-1
14.1.1 Features......................................................................................................................................................14-1
14.1.2 Configuration.............................................................................................................................................14-3
14.2 Description of Registers.............................................................................................................................14-4
14.2.1 List of Registers.........................................................................................................................................14-4
14.2.2 DMA Channel n Transfer Mode Register (DCnMOD: n = 0, 1)...............................................................14-5
14.2.3 DMA Channel n Transfer Count Register (DCnTN: n = 0, 1)...................................................................14-7
14.2.4 DMA Channel n Transfer Source Address Register (DCnSA: n = 0, 1)....................................................14-8
14.2.5 DMA Channel n Transfer Destination Address Register (DCnDA: n = 0, 1)............................................14-9
14.2.6 DMA Transfer Enable Register (DCEN)................................................................................................. 14-10
14.2.7 DMA Status Register (DSTAT)............................................................................................................... 14-11
14.2.8 DMA Interrupt Status Clear Register (DICLR).......................................................................................14-12
14.3 Description of Operation ......................................................................................................................... 14-13
14.3.1 Procedure to Use DMA Controller .......................................................................................................... 14-13
14.3.2 DMA transfer Operation Timing Diagram ..............................................................................................14-15
14.3.3 UART Continuous Transmission Using DMA Transfer ......................................................................... 14-16
14.3.4 UART Continuous Reception Using DMA Transfer............................................................................... 14-17
14.3.5 DMA Transfer Target Block.................................................................................................................... 14-18
Chapter 15
15. Buzzer.............................................................................................................................................................15-1
15.1 General Description................................................................................................................................... 15-1
15.1.1 Features......................................................................................................................................................15-2
15.1.2 Configuration.............................................................................................................................................15-3
15.1.3 List of Pins................................................................................................................................................. 15-4
15.2 Description of Registers.............................................................................................................................15-5
15.2.1 List of Registers.........................................................................................................................................15-5

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-7
15.2.2 Buzzer 0 Control Register (BZ0CON).......................................................................................................15-6
15.2.3 Buzzer 0 Mode Register (BZ0MOD) ........................................................................................................15-7
15.3 Description of Operation ...........................................................................................................................15-9
15.3.1 Intermittent Sound 1 Mode........................................................................................................................ 15-9
15.3.2 Intermittent Sound 2 Mode...................................................................................................................... 15-11
15.3.3 Single Sound Mode.................................................................................................................................. 15-12
15.3.4 Continuous Sound Mode ......................................................................................................................... 15-13
15.3.5 Common Operation ................................................................................................................................. 15-14
Chapter 16
16. Simplified RTC....................................................................................................................................................
16.1 General Description................................................................................................................................... 16-1
16.1.1 Features...................................................................................................................................................... 16-1
16.1.2 Configuration.............................................................................................................................................16-1
16.2 Description of Registers............................................................................................................................. 16-2
16.2.1 List of Registers.........................................................................................................................................16-2
16.2.2 Simplified RTC Acceptor (SRTCACP).....................................................................................................16-3
16.2.3 Simplified RTC Minute/Second Counter (SRTCMAS) ............................................................................16-4
16.2.4 Simplified RTC Control Register (SRTCCON) ........................................................................................16-6
16.3 Description of Operation ........................................................................................................................... 16-7
16.3.1 Simplified RTC Time Data Writing Operation.......................................................................................... 16-7
16.3.2 Simplified RTC Setting Example for Writing Time Data..........................................................................16-8
Chapter 17
17. General Purpose Port.................................................................................................................................... 17-1
17.1 General Description................................................................................................................................... 17-1
17.1.1 Features......................................................................................................................................................17-2
17.1.2 Configuration.............................................................................................................................................17-3
17.1.3 List of Pins................................................................................................................................................. 17-5
17.2 Description of Registers.............................................................................................................................17-8
17.2.1 List of Registers......................................................................................................................................... 17-8
17.2.2 Port n Data Register (PnD:n=0 to 9, A, B) ..............................................................................................17-15
17.2.3 Port n Mode Register 01 (PnMOD01:n=0 to 9, A, B) .............................................................................17-16
17.2.4 Port n Mode Register 23 (PnMOD23:n=0 to 9, A, B) .............................................................................17-19
17.2.5 Port n Mode Register 45 (PnMOD45:n=0 to 2, 4 to 9, A, B) .................................................................. 17-22
17.2.6 Port n Mode Register 67 (PnMOD67:n=0 to 2, 4 to 9, A, B) .................................................................. 17-25
17.2.7 Port n Pulse Mode Register (PnPMD:n=0 to 3)....................................................................................... 17-28
17.2.8 Port n Pulse Selection Register (PnPSL:n=0 to 3)...................................................................................17-29
17.2.9 PORTXT data input register (PXTDI)..................................................................................................... 17-30
17.2.10 PORTXT mode register 01 (PXTMOD01)............................................................................................ 17-31
17.3 Description of Operation ......................................................................................................................... 17-32
17.3.1 Input......................................................................................................................................................... 17-32
17.3.2 Output...................................................................................................................................................... 17-32
17.3.3 Primary Function Other Than Input/Output Function ............................................................................. 17-32
17.3.4 Shared Function.......................................................................................................................................17-32
17.3.5 Carrier Frequency Output........................................................................................................................17-33
17.3.6 Port Output Level Test.............................................................................................................................17-34
17.3.7 Port Setting Example ............................................................................................................................... 17-34
17.3.8 Notes for using the P00/TEST0 pin......................................................................................................... 17-35
Chapter 18
18. External Interrupt Function........................................................................................................................... 18-1
18.1 General Description................................................................................................................................... 18-1
18.1.1 Features......................................................................................................................................................18-2
18.1.2 Configuration.............................................................................................................................................18-3
18.1.3 List of Pins................................................................................................................................................. 18-5
18.2 Description of Registers.............................................................................................................................18-6

ML62Q1000 Series User's Manual
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18.2.1 List of Registers.........................................................................................................................................18-6
18.2.2 External Interrupt Control Register 0 (EICON0)....................................................................................... 18-7
18.2.3 External Interrupt Mode Register 0 (EIMOD0)......................................................................................... 18-8
18.2.4 Expanded External Interrupt Control Register 0 (EEICON0) ................................................................. 18-10
18.2.5 Expanded External Interrupt Mode Register 0 (EEIMOD0) ...................................................................18-11
18.2.6 Expanded External Interrupt Mode Register 1(EEIMOD1) ....................................................................18-12
18.2.7 Expanded External Interrupt Status Register (EEISTAT)....................................................................... 18-13
18.2.8 Expanded External Interrupt Clear Register (EEINTC) .......................................................................... 18-14
18.3 Description of Operation ......................................................................................................................... 18-15
18.3.1 Interrupt Request Timing.........................................................................................................................18-15
18.3.2 External Trigger Signal............................................................................................................................ 18-16
18.3.3 External Interrupt Setting Flow ...............................................................................................................18-17
18.3.4 Expanded External Interrupt Setting Flow............................................................................................... 18-18
Chapter 19
19. CRC (Cycle Redundancy Check) Generator................................................................................................. 19-1
19.1 General Description................................................................................................................................... 19-1
19.1.1 Features......................................................................................................................................................19-1
19.1.2 Configuration.............................................................................................................................................19-2
19.2 Description of Registers.............................................................................................................................19-3
19.2.1 List of Registers......................................................................................................................................... 19-3
19.2.2 Automatic CRC Calculation Start Address Setting Register (CRCSAD).................................................. 19-4
19.2.3 Automatic CRC Calculation End Address Setting Register (CRCEAD)...................................................19-5
19.2.4 Automatic CRC Calculation Start Segment Setting Register (CRCSSEG)............................................... 19-6
19.2.5 Automatic CRC Calculation End Segment Setting Register (CRCESEG)................................................19-7
19.2.6 CRC Data Register (CRCDATA)..............................................................................................................19-8
19.2.7 CRC Calculation Result Register (CRCRES)............................................................................................19-9
19.2.8 Automatic CRC Mode Register (CRCMOD).......................................................................................... 19-10
19.3 Description of Operation .........................................................................................................................19-11
19.3.1 Manual CRC Calculation Mode............................................................................................................... 19-11
19.3.2 Automatic CRC Calculation Mode..........................................................................................................19-17
Chapter 20
20. Analog Comparator.......................................................................................................................................20-1
20.1 General Description................................................................................................................................... 20-1
20.1.1 Features......................................................................................................................................................20-2
20.1.2 Configuration.............................................................................................................................................20-3
20.1.3 List of Pins.................................................................................................................................................20-4
20.2 Description of Registers.............................................................................................................................20-4
20.2.1 List of Registers......................................................................................................................................... 20-5
20.2.2 Comparator n Control Register (CMPnCON: n=0,1) ................................................................................20-6
20.2.3 Comparator n Mode Register (CMPnMOD: n=0,1) ..................................................................................20-7
20.3 Description of Operation ........................................................................................................................... 20-9
20.3.1 Analog Comparator Operation...................................................................................................................20-9
20.3.2 Interrupt Request ..................................................................................................................................... 20-10
Chapter 21
21. D/A Converter .............................................................................................................................................. 21-1
21.1 General Description................................................................................................................................... 21-1
21.1.1 Features......................................................................................................................................................21-2
21.1.2 Configuration.............................................................................................................................................21-3
21.1.3 List of Pins................................................................................................................................................. 21-4
21.2 Description of Registers.............................................................................................................................21-5
21.2.1 List of Registers......................................................................................................................................... 21-5
21.2.2 D/A Converter 0 Control Register (DACCON).........................................................................................21-6
21.2.3 D/A Converter 0 Code Register (DACCODE)..........................................................................................21-7
21.2.4 D/A Converter 1 Control Register (DACCON1).......................................................................................21-8

ML62Q1000 Series User's Manual
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FEUL62Q1000 Contents-9
21.2.5 D/A Converter 1 Code Register (DACCODE1)........................................................................................21-9
21.3 Description of Operation ......................................................................................................................... 21-10
21.3.1 D/A Converter Operation......................................................................................................................... 21-10
Chapter 22
22. Voltage Level Supervisor .............................................................................................................................22-1
22.1 General Description................................................................................................................................... 22-1
22.1.1 Features......................................................................................................................................................22-2
22.1.2 Configuration.............................................................................................................................................22-3
22.2 Description of Registers.............................................................................................................................22-4
22.2.1 List of Registers.........................................................................................................................................22-4
22.2.2 Voltage Level Supervisor 0 Control Register (VLS0CON)....................................................................... 22-5
22.2.3 Voltage Level Supervisor 0 Mode Register (VLS0MOD).........................................................................22-6
22.2.4 Voltage Level Supervisor 0 Level Register (VLS0LV).............................................................................22-8
22.2.5 Voltage Level Supervisor 0 Sampling Register (VLS0SMP)....................................................................22-9
22.3 Description of Operation ......................................................................................................................... 22-10
22.3.1 Supervisor Mode...................................................................................................................................... 22-11
22.3.2 Single Mode............................................................................................................................................. 22-16
Chapter 23
23. Successive Approximation Type A/D Converter..........................................................................................23-1
23.1 General Description................................................................................................................................... 23-1
23.1.1 Features......................................................................................................................................................23-2
23.1.2 Configuration.............................................................................................................................................23-3
23.1.3 List of Pins.................................................................................................................................................23-4
23.2 Description of Registers.............................................................................................................................23-6
23.2.1 List of Registers......................................................................................................................................... 23-6
23.2.2 SA-ADC Result Register n (SADRn : n=0 to 15, 16)................................................................................23-8
23.2.3 SA-ADC Result Register (SADR).............................................................................................................23-9
23.2.4 SA-ADC Upper/Lower Limit Status Register 0 (SADULS0) ................................................................. 23-10
23.2.5 SA-ADC Upper/Lower Limit Status Register 1 (SADULS1) ................................................................. 23-11
23.2.6 SA-ADC Mode Register (SADMOD)..................................................................................................... 23-12
23.2.7 SA-ADC Control Register (SADCON)................................................................................................... 23-13
23.2.8 SA-ADC Enable Register 0 (SADEN0) ..................................................................................................23-14
23.2.9 SA-ADC Enable Register 1 (SADEN1) ..................................................................................................23-15
23.2.10 SA-ADC Conversion Interval Setting Register (SADSTM)..................................................................23-16
23.2.11 SA-ADC Upper/Lower Limit Mode Register (SADLMOD) ................................................................23-17
23.2.12 SA-ADC Upper Limit Setting Register (SADUPL).............................................................................. 23-18
23.2.13 SA-ADC Lower Limit Setting Register (SADLOL) ............................................................................. 23-18
23.2.14 SA-ADC Reference Voltage Control Register (VREFCON) ................................................................ 23-19
23.2.15 SA-ADC Interrupt Mode Register (SADIMOD)...................................................................................23-20
23.2.16 SA-ADC Trigger Register (SADTRG)..................................................................................................23-21
23.2.17 SA-ADC test mode register (SADTMOD)............................................................................................ 23-22
23.3 Description of Operation ......................................................................................................................... 23-23
23.3.1 Operation of Successive Approximation Type A/D Converter ...............................................................23-23
23.3.2 How to test the Successive Approximation Type A/D Converter............................................................23-27
23.3.3 A/D Conversion Time Setting ................................................................................................................. 23-28
23.4 Notes on SA-ADC...................................................................................................................................23-31
23.4.1 Sampling Time Setting ............................................................................................................................ 23-31
23.4.2 Noise Suppression ...................................................................................................................................23-32
Chapter 24
24. Regulator.......................................................................................................................................................24-1
24.1 General Description...............................................................................................................................24-1
24.1.1 Features............................................................................................................................................. 24-1
24.1.2 Configuration....................................................................................................................................24-1
24.1.3 List of Pins........................................................................................................................................24-2

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-10
24.2 Description of Operation.......................................................................................................................24-2
Chapter 25
25. Flash Memory..............................................................................................................................................25-1
25.1 General Description................................................................................................................................... 25-1
25.1.1 List of Pins.................................................................................................................................................25-4
25.2 Description of Registers.............................................................................................................................25-5
25.2.1 List of Registers......................................................................................................................................... 25-5
25.2.2 Flash Address Register (FLASHA) ...........................................................................................................25-6
25.2.3 Flash Segment Register (FLASHSEG)...................................................................................................... 25-7
25.2.4 Flash Data Register 0 (FLASHD0)............................................................................................................25-9
25.2.5 Flash Data Register 1 (FLASHD1).......................................................................................................... 25-10
25.2.6 Flash Control Register (FLASHCON)..................................................................................................... 25-11
25.2.7 Flash Acceptor (FLASHACP)................................................................................................................. 25-12
25.2.8 Flash Self Register (FLASHSLF)............................................................................................................ 25-13
25.2.9 Flash Status Register (FLASHSTA)........................................................................................................ 25-14
25.3 Self-programming.................................................................................................................................... 25-15
25.3.1 Notes on debugging self-programming codes .........................................................................................25-15
25.3.2 Programming program memory space.....................................................................................................25-16
25.3.3 Programming data flash area ................................................................................................................... 25-18
25.3.4 Notes on use of self-programming........................................................................................................... 25-20
25.4 In-System Programming Function........................................................................................................... 25-21
25.4.1 Programming procedure ..........................................................................................................................25-21
25.4.2 Communication method........................................................................................................................... 25-21
25.4.3 Communication command....................................................................................................................... 25-22
25.4.4 Transition Command to ISP Mode.......................................................................................................... 25-23
25.4.5 Flash Memory Handling.......................................................................................................................... 25-24
Chapter 26
26. Code Option................................................................................................................................................. 26-1
26.1 General Description................................................................................................................................... 26-1
26.1.1 Function List..............................................................................................................................................26-1
26.2 Description of Code Option.......................................................................................................................26-2
26.2.1 Code Options 0 (CODEOP0).....................................................................................................................26-2
26.2.2 Code Options 1 (CODEOP1).....................................................................................................................26-3
26.2.3 Code Options 2 (CODEOP2).....................................................................................................................26-4
26.3 Code Option Data Setting..........................................................................................................................26-5
Chapter 27
27. LCD Driver..................................................................................................................................................27-1
27.1 General Description................................................................................................................................... 27-1
27.1.1 Features......................................................................................................................................................27-1
27.1.2 Configuration of LCD Display Function ...................................................................................................27-2
27.1.3 Configuration of Bias Generation Circuit.................................................................................................. 27-3
27.1.4 List of Pins................................................................................................................................................. 27-5
27.2 Description of Registers.............................................................................................................................27-8
27.2.1 List of Registers.........................................................................................................................................27-8
27.2.2 Bias Control Register(BIASCON)............................................................................................................. 27-9
27.2.3 Display Mode Register(DSPMOD).........................................................................................................27-11
27.2.4 Display Control Register(DSPCON) .......................................................................................................27-12
27.2.5 Segment Mode Register0 (SEGMOD0) .................................................................................................. 27-13
27.2.6 Segment Mode Register1 (SEGMOD1) .................................................................................................. 27-15
27.2.7 Segment Mode Register2 (SEGMOD2) .................................................................................................. 27-17
27.2.8 Segment Mode Register3 (SEGMOD3) .................................................................................................. 27-19
27.2.9 Segment Mode Register4 (SEGMOD4) .................................................................................................. 27-21
27.2.10 Display Register(DSPR00 to DSPR64)................................................................................................. 27-22
27.3 Description of Operation ......................................................................................................................... 26-25

ML62Q1000 Series User's Manual
Contents
FEUL62Q1000 Contents-11
27.3.1 Operation of LCD Driver Circuit LCDs ..................................................................................................27-25
27.3.2 Display Register Segment Map ............................................................................................................... 27-25
27.3.3 Common Output Waveform .................................................................................................................... 27-26
27.3.4 Segment Output Waveform ..................................................................................................................... 27-28
27.3.5 Common Output Waveform for LED drive.............................................................................................27-32
27.3.6 Segment Output Waveform for LED drive.............................................................................................. 27-34
Chapter 28
28. On-Chip Debug Function.............................................................................................................................28-1
28.1 General Description................................................................................................................................... 28-1
28.1.1 Features......................................................................................................................................................28-2
28.1.2 Configuration.............................................................................................................................................28-3
28.1.3 List of Pins................................................................................................................................................. 28-4
28.2 How to Use On-chip Debug Function........................................................................................................28-5
28.3 Precautions.................................................................................................................................................28-5
28.4 Operation of Peripheral Circuits during breaks in the on-chip debug mode..............................................28-6
Chapter 29
29. Safety Function............................................................................................................................................29-1
29.1 General Description................................................................................................................................... 29-1
29.1.1 Features......................................................................................................................................................29-2
29.2 Description of Registers............................................................................................................................. 29-3
29.2.1 List of Registers.........................................................................................................................................29-3
29.2.2 RAM Guard Setting Register (RAMGD) ..................................................................................................29-4
29.2.3 SFR Guard Setting Register 0 (SFRGD0) ................................................................................................. 29-5
29.2.4 SFR Guard Setting Register 1 (SFRGD1) .................................................................................................29-6
29.2.5 RAM Parity Setting Register (RASFMOD) .............................................................................................. 29-8
29.2.6 Communication Test Setting Register (COMFT0).................................................................................... 29-9
29.2.7 MCU Status Interrupt Enable Register (MCINTEL)...............................................................................29-10
29.2.8 MCU Status Interrupt Register (MCISTATL).........................................................................................29-11
29.2.9 MCU Status Interrupt Clear Register (MCINTCL) .................................................................................29-12
29.3 Description of Operation .........................................................................................................................29-13
29.3.1 Communication Function Self-Test......................................................................................................... 29-13
29.3.2 Unused ROM Area Access Reset Function.............................................................................................29-14
29.3.3 Clock Mutual Monitoring Function.........................................................................................................29-15
29.3.4 CRC Calculation...................................................................................................................................... 29-17
29.3.5 WDT Counter Read................................................................................................................................. 29-17
29.3.6 Port Output Level Test.............................................................................................................................29-17
29.3.7 Successive Approximation Type A/D Converter Test............................................................................. 29-17
29.3.8 Clock Backup Function and Its Test........................................................................................................ 29-17
Appendixes
Appendix A Register List ................................................................................................................................... A-1
Appendix B Package Dimensions........................................................................................................................B-1
Appendix C Instruction Execution Cycle ............................................................................................................C-1
Appendix D Application Circuit Example.......................................................................................................... D-1
Appendix E List of Notes ....................................................................................................................................E-1
Revision History
Revision History.....................................................................................................................................................R-1

Chapter 1 Overview

ML62Q1000 Group User's Manual
Chapter 1 Overview
FEUL62Q1000 1-1
1. Overview
1.1 Features
ML62Q1000 Series is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory*1), data memory(RAM), data Flash and rich peripheral functions such as
the multiplier/divider, CRC operator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports,
UART, Synchronous serial port, I2C bus interface unit(Master, Slave), Buzzer, Voltage Level Supervisor(VSL), Successive
approximation type A/D converter, D/A converter , Analog comparator, LCD driver, Safety function and etc.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipeline architecture
parallel processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The product lists are shown below.
*1The products use SuperFlash® technology licensed from Silicon Storage Technology, Inc. SuperFlash® is a registered
trademark of Silicon Storage Technology, Inc.
Table 1-1 ML62Q1300 Group Product List
Program
memory Data memory Data
Flash
16pin
SSOP16
WQFN16
20pin
TSSOP20 24pin WQFN24 32pin TQFP32
64Kbyte
4Kbyte
2Kbyte
−
−
ML62Q1347
ML62Q1367
48Kbyte −−ML62Q1346 ML62Q1366
32Kbyte
−
−
ML62Q1345
ML62Q1365
32Kbyte 2Kbyte ML62Q1325 ML62Q1335 −−
24Kbyte
ML62Q1324
ML62Q1334
−
−
16Kbyte ML62Q1323 ML62Q1333 −−
Table 1-2 ML62Q1500 Group Product List
Program
memory Data memory Data
Flash 48pin TQFP48 52pin TQFP52
64pin
QFP64
TQFP64
80pin
QFP80
100pin
QFP100
TQFP100
256Kbyte
16Kbyte
4Kbyte
−
−
ML62Q1557
ML62Q1567
ML62Q1577
192Kbyte −−ML62Q1556 ML62Q1566 ML62Q1576
160Kbyte
−
−
ML62Q1555
ML62Q1565
ML62Q1575
128Kbyte 16Kbyte −−−ML62Q1564 ML62Q1574
8Kbyte
ML62Q1534
ML62Q1544
ML62Q1554
−
−
96Kbyte 16Kbyte −−−ML62Q1563 ML62Q1573
8Kbyte
ML62Q1533
ML62Q1543
ML62Q1553
−
−
64Kbyte 8Kbyte ML62Q1532 ML62Q1542 ML62Q1552 −−
48Kbyte
ML62Q1531
ML62Q1541
ML62Q1551
−
−
32Kbyte ML62Q1530 ML62Q1540 ML62Q1550 −−

ML62Q1000 Group User's Manual
Chapter 1 Overview
FEUL62Q1000 1-2
Table 1-3 ML62Q1700 Group Product List
Program
memory Data memory Data
Flash 48pin TQFP48 52pin TQFP52
64pin
QFP64
TQFP64
80pin
QFP80
100pin
QFP100
TQFP100
256Kbyte
16Kbyte
4Kbyte
-
-
ML62Q1727
ML62Q1737
ML62Q1747
192Kbyte - - ML62Q1726 ML62Q1736 ML62Q1746
160Kbyte
-
-
ML62Q1725
ML62Q1735
ML62Q1745
128Kbyte 16Kbyte - - - ML62Q1734 ML62Q1744
8Kbyte
ML62Q1704
ML62Q1714
ML62Q1724
-
-
96Kbyte 16Kbyte - - - ML62Q1733 ML62Q1743
8Kbyte
ML62Q1703
ML62Q1713
ML62Q1723
-
-
64Kbyte 8Kbyte ML62Q1702 ML62Q1712 ML62Q1722 - -
48Kbyte
ML62Q1701
ML62Q1711
ML62Q1721
-
-
32Kbyte ML62Q1700 ML62Q1710 ML62Q1720 - -

ML62Q1000 Group User's Manual
Chapter 1 Overview
FEUL62Q1000 1-3
lCPU
−16-bit RISC CPU (CPU name: nX-U16/100)
−Instruction system: 16-bit length instruction
−Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and
so on
−On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
−ISP (In-System Programming) function built-in
−Minimum instruction execution time
−30.5 μs (at 32.768 KHz system clock)
−62.5ns/41.6ns (at 16 MHz/24MHz system clock)
lCoprocessor for multiplication and division
−
−Multiplication: 16bit × 16bit (operation time 4 cycles)
−Division: 32bit / 16bit (operation time 8 cycles)
−Division: 32bit / 32bit (operation time 16 cycles)
−Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
−Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
−Signed or Unsigned is selectable
lOperating voltage and temperature
−Operating voltage: VDD = 1.6 to 5.5 V
−Operating temperature: -40 to +105 °C
lInternal memory
−Prrogram Flash memory area
Rewrite count: 100 cycles
Rewrite unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Rewrite temperature: 0°C to +40°C
−Data Flash memory area
Rewrite count 10,000 cycles
Rewrite unit: 8bit(1byte)
Erase unit: 2Kbyte/128byte (ML62Q1300 group)
4Kbyte/128byte (ML62Q1500 and ML62Q1700 group)
Erase/Rewrite temperature: -40°C to +85°C
Back Ground Operation(CPU can work while erasing and rewriting)
−Data RAM area
Rewrite unit: 8bit/16bit(1byte/2byte)
Parity check function (Parity error reset is generatable)
lClock Generation Circuit
−Low-speed clock
Internal low-speed RC oscillation: Approx.32.768 kHz
External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable (ML62Q1500 and
ML62Q1700 group)
3 modes are available for the crystal oscillatiion
⋅Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins
⋅Standard mode: Standard oscillation allowance and current consumption
⋅Low power current mode: Smaller oscillation allowance than standard mode to make lower current
consumption
−High-speed clock
PLL oscillation: 24MHz/16MHz is selectable by code option
−WDT(Watch Dog Timer) clock
Internal low-speed RC oscillation: Aprox. 1kHz
The WDT independent clock or the divided clock of internal low-speed 32.768kHz RC oscillation clock is
selectable by the code option.