LAPIS Semiconductor ML7345 Guide

Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020

ML7345 Family LSIs
Hardware Design Manual
Issue Date: Sep,5th, 2019
FEXL7345DG-02

ML7345 Family LSIs Hardware Design Manual
i
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from
failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to
illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when
designing circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this
document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such
rights owned by third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells,
and power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have
no responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS
Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor
shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2018 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/

ML7345 Family LSIs Hardware Design Manual
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Introduction
This hardware design manual contains hardware information that should be referenced when
designing ML7345 family devices (Hereafter ML7345). And also contains the measurement
conditions and example of measurement results of RF characteristics.
Target product：
ML7345
ML7345C
ML7345D
The following related manual is available and should be referenced as needed
ML7345 data sheet
All other company and products names are the trademarks or registered trademarks of the respective companies.

ML7345 Family LSIs Hardware Design Manual
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Notation
Classification Notation Description
Numeric value 0xnn Represents a hexadecimal number.
0bnnnn Represents a binary number.
Address 0xnnnn_nnnn Represents a hexadecimal number. (indicates 0xnnnnnnnn)
Unit word, W 1 word = 32 bits
byte, B 1 byte = 8 bits
Mega, M 106
Kilo, K (uppercase) 210=1024
Kilo, k (lowercase) 103=1000
Milli, m 10-3
Micro, 10-6
Nano, n 10-9
Second, s (lowercase) Second
Terminology "H" level Signal level on the high voltage side; indicates the voltage level of
VIH and VOH as defined in electrical characteristics.
"L" level Signal level on the low voltage side; indicates the voltage level of
VIL and VOL as defined in electrical characteristics.
Register description
Read/write attribute: R indicates read-enabled; W indicates write-enabled.
MSB: Most significant bit in an 8-bit register (memory)
LSB: Least significant bit in an 8-bit register (memory)

ML7345 Family LSIs Hardware Design Manual
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Table of Contents
INTRODUCTION.............................................................................................................................................II
NOTATION ..................................................................................................................................................... III
TABLE OF CONTENTS ................................................................................................................................ IV
1. PLACING DECOUPLING CAPACITORS .............................................................................................. 1
2. CLOCK INPUT......................................................................................................................................... 3
2.1. CRYSTAL OSCILLATOR CIRCUIT ........................................................................................................... 3
2.1.1. Circuit component values for crystal oscillator circuit ................................................................ 3
2.1.2. Notes on the crystal oscillator circuit configuration .................................................................... 4
2.2. TCXO CIRCUIT (ML7345/ML7345D)................................................................................................. 5
3. PLL LOOP FILTER .................................................................................................................................. 6
4. VCO ........................................................................................................................................................... 7
4.1. ADJUSTING COMPONENT VALUES FOR VCO TANK .............................................................................. 8
4.2. NOTE ON THE VCO TANK CIRCUIT ...................................................................................................... 9
5. RF MATCHING COMPONENT VALUES ............................................................................................ 10
5.1. ANTENNA TX AND RX DIRECT TIE MATCHING CIRCUIT................................................................... 10
6. NOTES ON SELECTING EXTERNAL PARTS (RECOMMENDATIONS).........................................11
6.1. ANNTENNA.........................................................................................................................................11
6.2. INDUCTORS ........................................................................................................................................11
6.3. CAPACITORS.......................................................................................................................................11
6.4. RESISTORS .........................................................................................................................................11
7. NOTES ON BOARD ARTWORKS (RECOMMENDATIONS)..............................................................11
7.1. GND ..................................................................................................................................................11
8. APPLICATION CIRCUIT(ML7345/ML7345C) .................................................................................... 12
8.1. 426～433MHZ(ML7345/ML7345C) .................................................................................................. 12
8.2. 868MHZ(ML7345/ML7345C).......................................................................................................... 13
8.3. 922MHZ(ML7345/ML7345C).......................................................................................................... 14
8.4. 470～510MHZ(ML7345C) ............................................................................................................... 15
9. BILL OF MATERIALS(ML7345/ML7345C) ......................................................................................... 16
9.1 426～433MHZ/868MHZ/922MHZ BAND (ML7345) 470MHZ～490MHZ BAND (ML7345C) ........ 16
10. APPLICATION CIRCUIT(ML7345D) ............................................................................................... 18
10.1. 426～433MHZ (ML7345D) .......................................................................................................... 18
10.2. 868MHZ(ML7345D)..................................................................................................................... 19
10.3. 922MHZ(ML7345D)..................................................................................................................... 20
11. BILL OF MATERIALS(ML7345D) .................................................................................................... 21
11.1 426～433MHZ/868MHZ/922MHZ BAND (ML7345D)...................................................................... 21
REVISION HISTORY .................................................................................................................................... 23

ML7345 Family LSIs Hardware Design Manual
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ML7345 Family LSIs Hardware Design Manual
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1. Placing decoupling capacitors
Place decoupling capacitors between each power pins and GND as shown in Figure 1.1.
Figure 1.1 Power Supply Block Diagram
*[1] The supply voltage for the PA_OUT pin (#20) should be provided the DC bias through the inductor (L3)
REG_PA(#21)
VDD_PA(#22)
VDD_REG(#1)
Including backside GND
GND
REG_OUT(#3)
PA_OUT(#20)
VBG(#2)
VDD
REG_CORE(#4)
VB_EXT(#31)
VDD_VCO(#32)
VDD_CP(#27)
VDD_RF(#25)
Each decoupling capacitors as close to an LSI pin as possible.
PA regulator
VDDIO(#9)
1.5V regulator
Logic circuit
0.1µF
0.1µF
0.1µF
1000pF
1000pF
1000pF
0.1µF
L3*[1]
1000pF
1μF
0.1µF
1μF
PA

ML7345 Family LSIs Hardware Design Manual
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Notes the following when placing decoupling capacitors:
1. The VDD and GND traces should be wider than other signal line traces to reduce the resister element.
2. Decoupling capacitor should be placed as close to an LSI pin as possible.
3. The smaller capacitor should be closer to an LSI pin than other capacitors.
4. VDDIO (#9), VDD_PA (#22), VDD_REG (#1) pins connected to the VDD share the trace.
5. A 1 µF decoupling capacitor should be placed to the REG_CORE (#4) pin to stabilize 1.5V regulator.
6. The VBG (#2) pin is a reference voltage output pin of band-gap reference circuit. Placing a 0.1μF
multilayer ceramic capacitor to the VBG (#2) pin to reduce the noise from the band-gap reference
circuit.

ML7345 Family LSIs Hardware Design Manual
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R11
2. Clock Input
2.1. Crystal Oscillator circuit
Figure 2.1 shows a configuration example of the crystal oscillator circuit.
Capacitors should be connected to XIN (#5) and XOUT (#6) pins to stabilize 24MHz crystal oscillator circuit. To
determine the component values, the oscillator circuit evaluation on your designing board is required, since the
stray capacitor of the board will be influenced.
Amplitude level, oscillation margin, frequency accuracy and oscillator circuit start-up time should be considered
and evaluated.
Figure 2.1 Crystal Oscillator circuit configurations
2.1.1. Circuit component values for crystal oscillator circuit
It is recommended to ask your oscillator manufacturer to evaluate the matching component values on the
assembled board. The following tables show the matching component values with LAPIS Semiconductor RF
board as reference.
Table 2.1.1 Representative matching component values
Manufacturer
Oscillator
Type
Frequency
(MHz)
Equivalent
series resister
Max(Ω)
Load
capacitor
(pF)
Component
Values
Operating Condition
(+/-10ppm)
C4
(pF)
C5
(pF)
R11
(Ω)
Power supply
voltage range
VDDIO(V)
Temperature range
( ℃)
NDK
NX2016SA
(CHP-CZS-6)
24
80Ω
8pF
1pF
1pF
0Ω
1.8 to 3.6
0～+70℃
EPSON
FA-128
24
80Ω
8pF
5pF
5pF
100Ω
1.8 to 3.6
-10～+70℃
YOKETAN
S2016A
24
110Ω
6pF
2.7pF
2.7pF
0Ω
1.8 to 3.6
-10～+70℃
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.
XIN(#5)
C4
X’tal
XOUT(#6)
C5

ML7345 Family LSIs Hardware Design Manual
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2.1.2. Notes on the crystal oscillator circuit configuration
Note the following when designing the crystal oscillator circuit.
1. The capacitors value of C4 and C5 depends on the crystal oscillator specification.
2. C1 and C2 should be placed as close as possible to the XIN (#5) and the XOUT (#6) pins to suppress
parasitic LCR and stabilize the oscillator.
3. Do not place the crystal oscillator circuit across other signal lines.
4. Do not trace signal lines where large current flow around the crystal oscillator circuit.
5. For the oscillator circuit capacitors, make sure the potential of the ground points is always equal to that
of the GND. Do not connect the capacitors to GNDs where large current flow.
6. X’tal must connect to ML7345/C/D only. Do not take oscillation signals from the oscillator circuit.

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2.2. TCXO circuit (ML7345/ML7345D)
Please use a TCXO that satisfy the following specification.
Output load: 10kΩ//10pF
Output level: 0.8Vpp to 1.5Vpp
Frequency accuracy: below ±10ppm
The ML7345 has integrated bias circuit and the DC bias is applied to the TCXO (#6) pin. A 0.1uF capacitor
should be placed on the TCXO line as following.
In ML7345, #5 pin is N.C. pin, then it should be open.
In order to low current, the TCXO should be disable when sleep mode.
Figure 2.2 External oscillator circuit (TCXO) configurations
TCXO
24MHz
0.1uF
TCXO(#6)
Bias
N.C.(#5)

ML7345 Family LSIs Hardware Design Manual
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3. PLL loop filter
Figure 3.1 shows a configuration example of the PLL loop filter circuit . C3 and R3 values depend on the data
rate to satisfy phase noise feature. The recommend values are listed in Table 3.1.
It is recommended to select the components with flat temperature characteristics and temperature coefficient is
managed. Capacitors, do not select high dielectric type and semiconductor type, so there is low accuracy and
non-linear temperature characteristics.
In order to prevent noise, the loop filter components (C3, R3 and C2) should be placed as close to the LP (#26)
pin as possible, recommends within 5 mm. Do not trace signal lines that become a noise source like a reference
clock line, around the loop filter.
Figure 3.1 PLL loop filter circuit configurations
Table 3.1 Representative component values for the loop filter
Data rate
Less
than100kbps
100kbps
C2
10pF
68pF
C3
1000pF
1000pF
R3
6.8kΩ
12kΩ
R4
N.M.
N.M.
LP(#26)
C2
R3
C3
R4

ML7345 Family LSIs Hardware Design Manual
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4. VCO
Figure 4.1 shows a configuration example of the VCO tank circuit. VCO oscillator frequency calculated as
follows:
LC
F
 2
1

The L in the above equation will be the sum of the inductor L1, the line inductance of the PCB and the internal
inductance of the ML7345. And the C will be the sum of the capacitor C1, the line capacitor of the PCB and the
internal capacitor (including calibration capacitor) of the ML7345. Table 4.1 shows the typical value of internal
capacitor.
Figure 4.1 VCO tank circuit configurations
Table 4.1: Internal capacitor value
VCO_CAL[6:0](B0, 0x6E)
Internal capacitor value[pF]
0x00
2.94pF
0x40
2.46pF
0x7F
1.97pF
conditions：LP(#26) pin voltage（VCO tuning voltage）=0.75V
IND1(#28)
Variable capacitor
Amplifier
C1
L1
IND2(#30)
Variable capacitor
for calibration

ML7345 Family LSIs Hardware Design Manual
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4.1. Adjusting component values for VCO tank
Adjustment procedure of the VCO tank componentｓis as below:
1. Execute the VCO calibration with the following condition.
Set the frequency to the center of usingfrequency range.
In the idle state with the room temperature.
2. Adjust the L1 and C1 values so that the calibration value obtained by [VCO_CAL] register (B0 0x6E)
becomes close to “64”(Decimal).
Reducing one or both L1 and C1 values if decreasing the VCO_CAL value.
Increasing one or both L1 and C1 values if increasing the VCO_CAL value.
[Note] In order to lock the PLL, the VCO_CAL value is required to be in the range from 1 to 126 (decimal) under
all conditions.
VCO calibration is required at customer manufactureing process (normal temperature contorol).In order
for the VCO_CAL value to be within the 64(dec)±20code by shipment test, use the deviation of L,C is
less than±2%
The frequency range that PLL can lock, VCO phase noise and the temperature feature depend on the L1, C1
values. It is recommended to evaluate these characteristics when L1 and C1 values is fixed.
Table 4.1.1 Representative component values for operating frequency
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not guaranteed
to obtain same result on your specific board.
VCO tank
RF frequency
PLL(VCO)
Divider
setting
VCO
Oscillation
frequency(F)
L1
C1
ML7345
169MHz
Divide by 6
1014MHz
4.3nH
2.0pF
426MHz
Divide by 2
852MHz
4.7nH
3.9pF
868MHz
no divide
868MHz
4.7nH
3.9pF
920MHz
no divide
920MHz
4.3nH
3.3pF
ML7345C
470~510MHz
no divide
470~510MHz
33nH
N.M.
ML7345D
868MHz
no divide
868MHz
4.7nH
3.9pF
920MHz
no divide
920MHz
4.3nH
3.3pF

ML7345 Family LSIs Hardware Design Manual
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4.2. Note on the VCO tank circuit
Note the following when designing the VCO tank cercuit.
1. In order to stable VCO oscillation, the VCO tank components (L1 and C1) should be placed as close to the
IND1 (#28) and IND2 (#30) pins as possible, recommends within 2 mm. Since the line inductance and
capacitance of PCB will effect to the oscillation frequency.
2. ML7345 maximum output power is more than 100mW. As shown in the Figure 4.2.1, high output will flow
on the transmission path from PA_OUT (#20) pin. If this output affects on VCO tank circuit, it may cause
the PLL unlock. So be careful the followings:
2.1. VCO tank inductor L1 and PA choke inductor L3 should be placed so that their positional relationship
becomes the 90 degrees to avoid their coupling.
2.2. L1 and L3 should be placed close to their connect pins of ML7345. They should not be placed close to
each other. recommends within 2 mm. Spacing between each inductors is recommended more than
8mm.
2.3. RF maching circuit should not be close to the L1.recommends more than 6mm.
2.4. PCB traces to the L1, C1 from VCO pins(IND1/IND2) should be symmetrical.
2.5. L1 should be placed nearer to the VCO pins(IND1/IND2) than C1.
2.6. Avoid signal line or Vdd line underneath layers of L1,C1.
Figure 4.2.1 Notes on the VCO tank circuit
Figure 4.2.2 Recommended placement of L1 and L3
L1 and L3 should be placed so that their
positional relationship with the 90 degrees
in order to avoid their coupling.
IND1(#28)
REG_PA (#21)
PA_OUT (#20)
PA
Regulator
VCO
Matching
Network
PA
L3
～100mW
Interference from Tx signal
IND2 (#30)
L1
C1
L3
L1

ML7345 Family LSIs Hardware Design Manual
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5. RF matching component values
Table 5.1 shows the measured impedance of the PA_OUT (#20) pin and the LNA_P (#24) pin at operationg
frequency.These impedances are presented as a reference.
Table 5.1 Measured RF impedance.
R + jX [Ω]
TX [PA_OUT(#20)]
RX [LNA_P(#24)]
RF frequency
20dBm
13dBm
10dBm
0dBm
-
ML7345
169MHz
-
3.6 + j16.4
3.6 + j16.4
1.4 + j16.8
627 - j344.7
426MHz
-
60.5 + j25.3
60.5 + j25.3
8.7 + j87.8
264.8 - j414
868MHz
-
22.0 - j69.0
22.0 - j69.0
4.9 - j104.7
92.3 - j190.2
920MHz
-
19.7 - j62.5
19.7 - j62.5
4.6 - j91.2
75.8 - j202
ML7345C
470～510MHz
16.9 + j16.7
-
-
-
2.2 - j90.5
ML7345D
868MHz
-
22.0 - j69.0
22.0 - j69.0
4.9 - j104.7
15.1 - j77
920MHz
-
19.7 - j62.5
19.7 - j62.5
4.6 - j91.2
13.7- j72.5
[Note] These component values appropriate for use on the LAPIS Semiconductor’s RF board. It is not
guaranteed to obtain same result on your specific board.
5.1. ANTENNATx and Rx direct tie matching circuit
Figure 5.1.1 shows the Antenna maching circuit configuraltions. RF Line layout from LNA_P(24) and PA_OUT(20) to
the Antenna should be the shortest and straight. The REG_PA (#21) pin provides the DC bias to the PA_OUT(#20) pin.
This DC bias should be provided through the inductor (L3). Chebyshev lowpass filter is consist of components L5~L8
and C47~C50,to suppress harmonics.
*Only ML7345D needs to short C41 by 0ohm.
Figure 5.1.1 Transmission matching circuit configurations
C37
C41
L2
L3
C45
C48
L5
C47
L7
C49
Thick line is Zo=50 ohm
C38
L9
ANTENNA
C51
C50
L4
L6
L8
PA_OUT(20)
LNA_P(24)
REG_PA(21)

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6. Notes on selecting external parts (recommendations)
6.1. Anntenna
It is recommended to use an antenna with the specifications shown in Table 6.1.
Select an antenna with the best directive characteristics for your specific operating, environmental and
installation condition. Since antennas are affected by installation conditions such as GND, external factors should
always be taken into account.
It is recommended to ask the manufacturer of the selected antenna for installation details in relation to various
factors, including the shape and stray capacitance of the board to be used.
Table 6.1 Antenna
Frequency band
160~180MHz / 315~450MHz / 470~510MHｚ/
868MHz / 920MHz band
VSWR
2.0MAX
Nominal Impedance
50Ω
6.2. Inductors
Use inductors with high Q. It is recommended to use LQW15AN series (manufactured by Murata Manufacturing
Co. Ltd) or equivalent.
6.3. Capacitors
Use capacitors with a CH (temperature compensating) or a B (high dielectric constant type) of temperature
characteristics. It is recommended to use capacitors of 0 ± 60 ppm/°C or less for areas that affect high frequency
characteristics. To realize lower power system it recommended to use low leak components because ML7345
has very low current consumption in sleep mode(0.4uA).
6.4. Resistors
Use resistors for which the resistance variation are small when the temperature changes.
7. Notes on board artworks (recommendations)
7.1. GND
About IC’s back side GND pad, the number of through-hole to board GND plane should be placed more than 12.
And drawing GND line width should be more wide as much as possible. Almost of L2 layer should be GND
plane for double-layered board.

ML7345 Family LSIs Hardware Deaign Manual
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8. Application circuit(ML7345)
8.1. 426～433MHz(ML7345/ML7345C)
[Note] · The XIN (#5) pin should be OPEN when using TCXO.
Thick line is Zo=50 ohm.
ANTENNA
Power Supply
3.3V
C6
Place LC tank on surface as close to LSI
pin as possible.
About the peripheral parts of pin#5 and pin#6 ,
please refer the section 2 and section 9.
VDD_RF VB_EXT VDD_VCO REG_OUT VDD_CP VBG REG_CORE VDD_REG
(25) (31) (32) (3) (27) (2) (4) (1)
R3
6.8kΩ
C3
1000pF
C37
1uF
X1
IC1
ML7345
LP
(26)
PA_OUT(20)
LNA_P(24)
IND2 GND_VCO IND1
(30) (29) (28)
Back side is GND PAD
VDDIO(9)
A_MON(23)
C33
1000pF
C27
1000pF
C41
100pF
L2
40nH
L3
18nH
C45
100pF
C48
2.4pF
L5
7.3nH
C47
4.7pF
L1
4.7nH
C5
C4
C17
0.1uF
C22
1000pF
C15
0.1uF
C2
10pF
C21
0.1uF
L7
20nH
C49
N.M.
VDD_PA(22)
REG_PA(21)
C1
3.9pF
C36
0.1uF
C38
1000pF
L9
20nH
N.C.
(7)
SDI(15)
SDO(12)
SCLK(13)
SCEN(14)
GPIO0(16)
EXT_CLK(10)
RESETN(8)
GPIO2(18)
GPIO1(17)
GPIO3(19)
REGPDIN(11)
C31
0.1uF
C19
1uF
C51
1.2pF
Digital
I/O
C50
5.6pF
L4
0Ω
L6
5.8nH
L8
0Ω
TCXO
IC2
R4
N.M.
R11
C13
10uF

ML7345 Family LSIs Hardware Deaign Manual
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8.2. 868MHz(ML7345)
[Note] · The XIN (#5) pin should be OPEN when using TCXO.
Thick line is Zo=50 ohm.
ANTENNA
Power Supply
3.3V
C6
Place LC tank on surface as close to LSI
pin as possible.
About the peripheral parts of pin#5 and pin#6 ,
please refer the section 2 and section 9.
VDD_RF VB_EXT VDD_VCO REG_OUT VDD_CP VBG REG_CORE VDD_REG
(25) (31) (32) (3) (27) (2) (4) (1)
R3
12kΩ
C3
1000pF
C37
1uF
X1
IC1
ML7345
LP
(26)
PA_OUT(20)
LNA_P(24)
IND2 GND_VCO IND1
(30) (29) (28)
Back side is GND PAD
VDDIO(9)
XIN XOUT
(5) (6)
A_MON(23)
C33
1000pF
C27
1000pF
C41
100pF
L2
11nH
L3
5.8nH
C45
100pF
C48
0Ω
L5
8.7nH
C47
N.M.
L1
4.7nH
C5
C4
C17
0.1uF
C22
1000pF
C15
0.1uF
C2
68pF
C21
0.1uF
L7
8.7nH
C49
0.9pF
VDD_PA(22)
REG_PA(21)
C1
3.9pF
C36
0.1uF
C38
1000pF
L9
0Ω
N.C.
(7)
SDI(15)
SDO(12)
SCLK(13)
SCEN(14)
GPIO0(16)
EXT_CLK(10)
RESETN(8)
GPIO2(18)
GPIO1(17)
GPIO3(19)
REGPDIN(11)
C31
0.1uF
C19
1uF
C51
0.9pF
Digital
I/O
C50
N.M.
L4
0Ω
L6
2.4pF
L8
N.M
.
TCXO
IC2
R4
N.M.
R11
C13
10uF