Lattice Semiconductor mVision AR0234 User manual

Lattice mVision AR0234 Sensor Board
User Guide
FPGA-UG-02124-1.1
February 2022

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-UG-02124-1.1
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 3
Contents
Acronyms in This Document.................................................................................................................................................5
1. Introduction..................................................................................................................................................................6
1.1. Features ..............................................................................................................................................................6
2. Required Components..................................................................................................................................................8
3. Headers and Jumpers .................................................................................................................................................10
4. Programming the Board .............................................................................................................................................11
4.1. Programming the Device...................................................................................................................................11
5. Interfaces....................................................................................................................................................................13
5.1. J1 Interface........................................................................................................................................................13
5.2. External Power Supply Connections .................................................................................................................13
5.3. Flash and Shutter Control Connections.............................................................................................................14
5.4. IR_CUT Driver Circuit.........................................................................................................................................14
6. Electrical Characteristics.............................................................................................................................................15
6.1. Absolute Maximum Ratings ..............................................................................................................................15
6.2. DC Electrical Characteristics..............................................................................................................................15
6.3. Operating Current Consumption for MIPI Output ............................................................................................16
6.4. Standby Current Consumption..........................................................................................................................16
6.5. Two-Wire Serial Bus Timing Parameters...........................................................................................................16
6.6. Two-Wire Serial Bus Characteristics..................................................................................................................17
7. Power-On Reset and Standby Timing .........................................................................................................................19
7.1. Power-Up Sequence..........................................................................................................................................19
7.2. Power-Down Sequence.....................................................................................................................................20
References..........................................................................................................................................................................22
Technical Support...............................................................................................................................................................23
Revision History..................................................................................................................................................................24

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-UG-02124-1.1
Figures
Figure 1.1. Top View of Lattice mVision AR0234CS Sensor Board........................................................................................7
Figure 1.2. Bottom View of Lattice mVision AR0234CS Sensor Board..................................................................................7
Figure 2.1. Embedded Vision Development Kit ....................................................................................................................8
Figure 2.2. Lattice mVision AR0234 Sensor Board................................................................................................................8
Figure 2.3. EVDK and AR0234 Sensor Boards Connected with Flex Cable............................................................................9
Figure 2.4. Flex Cable Connection Detail ..............................................................................................................................9
Figure 4.1. Programming Cable Setup ................................................................................................................................11
Figure 4.2. CrossLink Programming Setup..........................................................................................................................11
Figure 4.3. CrossLink Programming Status .........................................................................................................................12
Figure 4.4. ECP5 Programming Setup .................................................................................................................................12
Figure 4.5. ECP5 Programming Status ................................................................................................................................12
Figure 5.1. J1 Interface........................................................................................................................................................13
Figure 5.2. External Power Supply Connections .................................................................................................................13
Figure 5.3. Flash and Shutter Control Connections ............................................................................................................14
Figure 5.4. IR_CUT Driver Circuit ........................................................................................................................................14
Figure 6.1. Two-Wire Serial Bus Timing Parameters Diagram............................................................................................17
Figure 7.1. Power-up Sequence..........................................................................................................................................19
Figure 7.2. Power-down Sequence.....................................................................................................................................20
Tables
Table 3.1. AR0234 Sensor Board.........................................................................................................................................10
Table 3.2. CrossLink VIP Input Bridge Board.......................................................................................................................10
Table 3.3. ECP5 VIP Processor Board..................................................................................................................................10
Table 6.1. Absolute Maximum Ratings ...............................................................................................................................15
Table 6.2. DC Electrical Characteristics...............................................................................................................................15
Table 6.3. Operating Current Consumption for MIPI Output .............................................................................................16
Table 6.4. Standby Current Consumption...........................................................................................................................16
Table 6.5. Two-Wire Serial Bus Characteristics...................................................................................................................17
Table 7.1. Power-up Sequence ...........................................................................................................................................20
Table 7.2. Power-down Sequence ......................................................................................................................................21

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
EVDK
Embedded Vision Development Kit
FPGA
Field-Programmable Gate Array
ISP
Image Signal Processing
JTAG
Joint Test Action Group
MIPI
Mobile Industry Processor Interface
SCLK
Serial Clock Signal

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-UG-02124-1.1
1. Introduction
The Lattice mVision™AR0234CS sensor board uses a 1/2.6−inch 2.3 Mp Color 0deg Global Shutter CMOS digital image
sensor with an active−pixel array of 1920 (H) × 1200 (V) from On Semiconductor. The sensor board can be interfaced to
the EVDK (Embedded Vision Development Kit). The EVDK combines the bridging capability of our CrossLink™FPGA, the
low-power, small form factor ECP5™and the high-resolution benefits of our HDMI ASSP, onto this modular platform
enabling flexible connectivity and energy efficient image processing for robotics, drones, ADAS, smart surveillance and
AR/VR systems. The included software provides a comprehensive setup interface and flexibility to evaluate the Lattice
mVision ISP solution from Lattice and full sensor features and capabilities.
The sensor board comes with a lens suitable for evaluation with M12 lens holder to use standard M12 compatible
lenses. You can use your own lens as long as it is compatible with the mechanical and optical requirements.
An IR-CUT driver circuit using TI’s DRV8838 integrated motor driver solution for cameras allows the use of IR-CUT filter.
1.1. Features
The key features of the Lattice mVision AR0234CS sensor board are:
ON Semiconductor CMOS ½.6”, Color, 0deg, Image Sensor AR02345CS with following specifications:
Active pixels: 1920H × 1200V
Pixel size: 3.0 um × 3.0 um
Color sensor
Interface: MIPI output
Global Shutter
Part#: AR0234CS3C00SUKA0-CP-E
IR_CUR driver circuit for use of IR_CUT filters
Included PT-0620 lens with following specifications:
Focal Length: 6.0 mm
Iris: F2.0
Mount: M12x0.5
Image Sensor Size: 1/3"
Angle of View: 51°
Housing: Metal
Optics: Glass
M12 lens holder
External connection for Flash and Shutter control
External connection for all power supplies
External connection for EVDK kit (including power, data, and control signals)
Tripod Connection

Lattice mVision AR0234 Sensor Board
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© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 7
Camera, Lens, and Holder
Figure 1.1. Top View of Lattice mVision AR0234CS Sensor Board
Camera, Lens, and Holder
Flash and Shutter Control
Power (2.8 V)
Control, Power, and MIPI
(from EVDK)
Power (1.8 V)
Power (3.3 V)
IR_CUT Motor Control
IR_CUT Motor
Figure 1.2. Bottom View of Lattice mVision AR0234CS Sensor Board

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-UG-02124-1.1
2. Required Components
Before starting the evaluation, the following items must be available and ready to use on the test bench.
Embedded Vision Development Kit (EVDK) with camera modules removed
Figure 2.1. Embedded Vision Development Kit
mVision AR0234 Sensor Board with lens holder and lens assembled
Figure 2.2. Lattice mVision AR0234 Sensor Board
HDMI Monitor
HDMI Cable
Flexible Cable
Two jumpers placed on J7 and J8 headers of AR0234 Sensor Board

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 9
Once all required items are available, connect the EVDK and AR0234 sensor board together using the Flex cable as
shown in Figure 2.3.
Figure 2.3. EVDK and AR0234 Sensor Boards Connected with Flex Cable
Figure 2.4. Flex Cable Connection Detail

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-UG-02124-1.1
3. Headers and Jumpers
Table 3.1 lists the headers and jumpers as shown in Figure 1.2.
Table 3.1. AR0234 Sensor Board
S. No.
Jumper Name
Description
1
J7
Short
2
J8
Short
Table 3.2. CrossLink VIP Input Bridge Board
S. No.
Jumper Name
Description
1
J4
Short
2
J30
Open
3
J2
Short
4
—
All other headers should be kept open
Table 3.3. ECP5 VIP Processor Board
S. No.
Jumper Name
Description
1
J55
Connect 2 and 3
2
J51
Connect 1 and 2
3
J5
Connect 1 and 2
4
J9
Connect 1 and 2
6
J6
Connect 1 and 2
7
J3
Connect 1 and 2, also 5 and 6
8
J50
Connect 1 and 2, also 3 and 5
9
J7
Connect 2 and 3
10
J52
Connect 1 and 2 for SPI, 2 and 3 for JTAG
11
J53
Connect 1 and 2
12
—
All other headers should be kept open

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User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 11
4. Programming the Board
4.1. Programming the Device
The board is programmed through the Lattice Radiant™programmer software, which can be started as a standalone
tool or from a Lattice Radiant Project.
To program the Lattice mVision AR0234 Sensor Board using the Lattice EVDK:
1. Connect the LF-EVDK1-EVN board to the DC power adapter (12 V).
2. Connect the board to PC through the USB mini port.
3. Start the Lattice Diamond® Programmer version 3.10 or higher.
4. In the Getting Started dialog box, select the configurations shown in Figure 4.1. Click OK.
Figure 4.1. Programming Cable Setup
5. Select LIFMD for Device Family, LIF-MD6000 for Device, Fast Program for Operation, and
mVision_CSI2_2_parallel_impl1.bit for File Name as shown in Figure 4.5.
Figure 4.2. CrossLink Programming Setup
6. Click the Program button to program and check the status.

Lattice mVision AR0234 Sensor Board
User Guide
© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-UG-02124-1.1
Figure 4.3. CrossLink Programming Status
7. Select ECP5UM for Device Family, LFE5UM-85F for Device, Fast Program for Operation, and
mVision_ISP_1080p_impl1.bit for File Name as shown in Figure 4.4.
Figure 4.4. ECP5 Programming Setup
8. Click the Program button to program and check the status.
Figure 4.5. ECP5 Programming Status
9. Connect the HDMI monitor to the board using the HDMI cable.
10. Toggle the SW3 (SYS_RST) button on the Crosslink VIP Bridge Board. The sensor-captured video is displayed on the
HDMI monitor.

Lattice mVision AR0234 Sensor Board
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© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 13
5. Interfaces
5.1. J1 Interface
The J1 interface includes power, control, and MIPI signals connection to EVDK.
DVDD1V8
R3
4K7
R4
4K7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
J1
CLK_N
CLK_P
GND1
DATA3_N
DATA3_P
GND2
DATA1_N
DATA1_P
GND3
DATA0_N
DATA0_P
GND4
DATA2_N
DATA2_P
GND5
EXTCLK
SDATA
SCLK
RESET_BAR
DVDD1V8E
GND6
GND7
AVDD2V8E
GND8
Kyocera 24-5804-030-000-829+
Figure 5.1. J1 Interface
5.2. External Power Supply Connections
The J5, J7, and J8 headers allow external power supply connection to the sensor board. Using a jumper to short pin 1
and 2 of the J7 header supplies 1.8 V from J1 connector. Using a jumper to short pin 1 and 2 of the J8 header supplies
2.8 V from J1 connector.
To use external supplies, use pin 1 of these headers. Note that 3.3 V supply for IR_CUT circuit is not provided through
J1.
3v3
3.3 v
1
2
DVDD1V8
AVDD2V8
DVDD1V8E
AVDD2V8E
1
2
1
2
C44
100nF C45 10uF
J5
HEADER 2
J7
J8
HEADER 7
HEADER 8
1.8 v
2.8 v
Figure 5.2. External Power Supply Connections

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14 FPGA-UG-02124-1.1
5.3. Flash and Shutter Control Connections
J2 and J3 allow external control for Shutter and Flash.
DVDD1V8
1
2
3
1
2
3
SHUTTER
FLASH
J3
J2
C1
100nF
HEADER 3
HEADER 3
SHUTTER
FLASH
Figure 5.3. Flash and Shutter Control Connections
5.4. IR_CUT Driver Circuit
Figure 5.4 shows the IR_CUT driver circuit. A 3.3 V supply power must be applied using the J5 header. J6 allows external
control of the driver. J4 must be connected to appropriate IR_CUT motor.
3V3
C43
10uF
C42
100nF
J4
HEADER 2
MOTOR
1
2
C46
100nF
U4
1
2
3
4
9
IR_CUT Driver
VM
OUT1
OUT2
GND
EPAD
VCC
nSLEEP
PH
EN
8
7
6
5
R14 10K
1
2
DRV8838DSGT
HEADER 2
CONTROL
J6 C44
100nF C45
10uF
1
2
J5
3.3 V
HEADER 2
3V3
Figure 5.4. IR_CUT Driver Circuit

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© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 15
6. Electrical Characteristics
6.1. Absolute Maximum Ratings
Table 6.1. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VSUPPLY
Power Supply Voltage
–0.3
4.5
V
ISUPPLY
Total Power Supply Current
—
200
mA
IGND
Total Ground Current
—
200
mA
VIN
DC Input Voltage
–0.3
VDD_IO + 0.3
V
VOUT
DC Output Voltage
–0.3
VDD_IO + 0.3
V
TSTG
Storage Temperature2
–40
+125
°C
Notes:
1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded,
device functionality should not be assumed, damage may occur, and reliability may be affected.
2. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
6.2. DC Electrical Characteristics
Table 6.2. DC Electrical Characteristics
Symbol
Definition
Condition
Min
Typ
Max
Unit
VDO
Core Digital Voltage
1.14
1.2
1.26
V
VDD_IO
I/O Digital Voltage
1.7/2.5
1.8/2.8
1.9/3.1
V
VDD_IO_PHY
I/O Power Supply
1.7/2.5
1.8/2.8
1.9/3.1
V
VAA
Analog Voltage
2.5
2.8
3.1
V
VAA_PIX
Pixel Supply Voltage
2.5
2.8
3.1
V
VDD_PHY
MIPI Supply Voltage
1.14
1.2
1.26
V
VDD_DATA
MIPI Supply Voltage
1.14
1.2
1.26
V
VAA_PHY
MIPI Supply Voltage
2.5
2.8
3.1
V
VIH
Input HIGH Voltage
VDD_IO × 0.7
—
—
V
VIL
Input LOW Voltage
—
—
VDD_IO × 0.3
V
IIN
Input Leakage Current
No pull-up resistor;
VIN = VDD_IO or DGND
20
—
—
µA
VOH
Output HIGH Voltage
VDD_IO - 0.3
—
—
V
VOL
Output LOW Voltage
VDD_IO = 2.8 V
—
—
0.4
V
IOH
Output HIGH Current
At specified VOH
–22
—
—
mA
IOL
Output LOW Current
At specified VOL
—
—
22
mA
Note: Stresses greater than those listed in Table 6.2 may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied.

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16 FPGA-UG-02124-1.1
6.3. Operating Current Consumption for MIPI Output
Table 6.3. Operating Current Consumption for MIPI Output
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IDD_PHY +
IDD_DATA +
IDD
Digital Operating Current
MIPI, Streaming, Full Resolution 120 fps
TBD
147
TBD
mA
IDDIO_PHY +
IDD_IO
I/O Digital Operating
Current
MIPI, Streaming, Full Resolution 120 fps
TBD
8
—
mA
IAA_PHY + TAA
Analog Operating Current
MIPI, Streaming, Full Resolution 120 fps
TBD
55
TBD
mA
IAA_PIX
Pixel Supply Current
MIPI, Streaming, Full Resolution 120 fps
TBD
6
TBD
mA
Notes:
1. (VAA = VAA_PIX = VDD_IO = 2.8 V; VDD = VDD_PHY = 1.2 V; VDDIO_PHY = 1.8 V; PLL Enabled and PIXCLK = 90 MHz; TA= 25 °C;
CLOAD = 10 pF)
2. Values in Table 6.3 are subject to change.
3. The following supply rails can be connected together:
a. VDD, VDD_PHY, and VDD_DATA
b. VDD_IO and VDDIO_PHY
c. VAA, VAA_PHY, and VAA_PIX
6.4. Standby Current Consumption
Table 6.4. Standby Current Consumption
Definition
Condition
Min
Typ
Max
Unit
Apply XSHUTDOWN (Clock Off)
Analog, 2.8 V
TBD
10
TBD
µA
Digital, 1.8 V
TBD
40
TBD
µA
Apply XSHUTDOWN (Clock On)
Analog, 2.8 V
TBD
25
TBD
µA
Digital, 1.8 V
TBD
55
TBD
µA
Soft Standby (Clock Off, Driven Low)
Analog, 2.8 V
TBD
15
TBD
µA
Digital, 1.8 V
TBD
270
TBD
µA
Soft Standby (Clock On, EXTCLK = 27 MHz)
Analog, 2.8 V
TBD
70
TBD
µA
Digital, 1.8 V
TBD
2600
TBD
µA
Notes:
1. (Analog = VAA + VAA_PIX + VAA_PHY; Digital = VDD + VDD_IO + VDD_PHY + VDDIO_PHY + VDD_DATA; TA= 25 °C)
2. Values in Table 6.4 are subject to change.
6.5. Two-Wire Serial Bus Timing Parameters
Unless otherwise stated, the following specifications apply to the following conditions:
VDD = VDD_PHY = VDD_DATA = 1.2 V +/-0.06;
VDD_IO = VAA = VAA_PIX = 2.8 V +/-0.3 V; VDDIO_PHY = 1.8 V +/-0.1 V
TA= −40 °C to + 105 °C;
Output Load = 10 pF;
PIXCLK Frequency = 90 MHz;
MIPI off
The electrical characteristics of the two−wire serial register interface (SCLK, SDATA) are shown in Figure 6.1 and Table 6.5.

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FPGA-UG-02124-1.1 17
SData
tf
SCLK
S
tLOW
tHD;STA
trtSU;DAT
tHD;DAT tHIGH
tf
tSU;STA
tHD;STA
Sr
tSU;STO
trtBUF
P S
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are
issued.
Figure 6.1. Two-Wire Serial Bus Timing Parameters Diagram
6.6. Two-Wire Serial Bus Characteristics
Table 6.5. Two-Wire Serial Bus Characteristics
Parameter
Symbol
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
SCLK Clock Frequency
fSCL
0
100
0
400
kHz
Hold Time (Repeated) START
Condition (after this period, the First
Clock Pulse is generated)
tHD;STA
4.0
—
0.6
—
µs
LOW Period of the SCLK Clock
tLOW
4.7
—
1.3
—
µs
HIGH Period of the SCLK Clock
tHIGH
4.0
—
0.6
—
µs
Set-Up Time for a Repeated START
Condition
tSU;STA
4.7
—
0.6
—
µs
Data Hold Time
tHD;DAT
05
3.456
07
0.96
µs
Data Set-Up Time
tSU;DAT
250
—
1007
µs
Rise Time of both SDATA and SCLK Signals
tr
—
1000
20 + 0.1 Cb8
µs
Fall Time of both SDATA and SCLK Signals
tf
—
300
20 + 0.1 Cb8
µs
Set-Up Time for STOP Condition
tSU;STO
4.0
—
0.6
—
µs
Bus Free Time between a STOP and
START Condition
tBUF
4.7
—
1.3
—
µs
Capacitive Load for each Bus Line
Cb
—
400
—
400
pF
Serial Interface Input Pin Capacitance
CIN_SI
—
3.3
—
3.3
pF
SDATA Max Load Capacitance
CLOAD_SD
—
30
—
30
pF
SDATA Pull-Up Resistor
RSD
1.5
4.7
1.5
4.7
kΩ
Notes:
1. (fEXTCLK = 27 MHz; VDD = 1.2 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PHY = 1.2 V; VDDIO_PHY = 1.8 V; TA= 25 °C)
2. This table is based on I2C standard (v2.1 January 2000) Philips Semiconductor.
3. Two-wire control is I2C-compatible.
4. All values referred to VIHmin = 0.9 V VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXCLK = 27 MHz.
5. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling
edge of SCLK. The two-wire standard specifies a minimum rise and fall time for Fast Mode operation. This specification is not a
timing requirement that is enforced on ON Semiconductor sensor’s as a receiver, because our receivers are designed to work in
mixed systems with std-mode where no such minimum rise and fall times are required/specified. However, it is the host’s
responsibility when using fast edge rates, especially when two-wire slew-rate driver control is not available, to manage the
generated EMI, and the potential voltage undershoot on the sensor receiver circuitry, to avoid activating sensor ESD diodes and
current-clamping circuits. This is typically not an issue in most applications., but should be checked if below minimum fall times
and rise times are required. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.

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18 FPGA-UG-02124-1.1
6. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
7. A Fast mode I2C bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be
met. This is automatically the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch
the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tfmax + tSU;DAT = 1000 + 250 = 1250 ns
(according to the Standard-mode I2C bus specification) before the SCLK line is released.
8. Cb = total capacitance of one bus line in pF.

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© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02124-1.1 19
7. Power-On Reset and Standby Timing
7.1. Power-Up Sequence
The recommended power-up sequence for the AR0234 is shown in Figure 7.1. The available power supplies
(VAA/VAA_PIX/VAA_PHY, VDDIO, VDDIO_PHY, VDD/VDD_PHY, and VDD_DATA) must have the separation specified
below.
Turn on VAA/VAA_PIX/VAA_PHY power supply.
After 100 µs, turn on VDDIO power supply.
After 100 µs, turn on VDDIO_PHY (1.8 V) power supply.
After 100 µs, turn on VDD/VDD_PHY power supply.
After 100 µs, turn on VDD_DATA power supply.
After the last power supply is stable, enable EXTCLK.
Assert RESET_N for at least 1 ms. The parallel interface is tristated during this time.
Wait for ~150000 EXTCLKs for internal initialization into soft standby where M3ROM and full OTPM upload is
complete.
Set streaming mode (mode_select/stream (R0x301A[2]) = 1) and the internal PLL is enabled (not locked yet).
Wait for 1 ms for PLL lock to complete, and then part goes into streaming mode.
VAA
VAA_PIX
VAA_PHY
(2.8)
VDD (1.8/2.8)
IO
VDD_PHY (1.8)
IO
VDD
VDD_PHY
(1.2)
VDD_DATA (1.2)
EXTCLK
RESET_BAR
t1
t2
t3
t4
tx
t5
t6t7
Hard
Reset
Internal
Initialization
Software
Standby PLL Lock Streaming
Figure 7.1. Power-up Sequence

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© 2021-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-UG-02124-1.1
Table 7.1. Power-up Sequence
SN
Definition
Symbol
Min
Typ
Max
Unit
1
VAA/VAA_PIX/VAA_PHY to VDDIO
t1
0
100
—
µs
2
VDDIO to VDDIO_PHY
t2
0
100
—
µs
3
VDDIO_PHY to VDD/VDD_PHY
t3
0
100
—
µs
4
VDD/VDD_PHY to VDD_DATA
t4
0
100
—
µs
5
Xtal Settle Time (Component Dependent)
tx
—
30 ms
—
ms
6
Hard Reset
t5
1
—
—
ms
7
Internal Initialization
t6
16000
—
—
EXTCLK
8
PLL Lock Time
t7
1
—
—
ms
Notes:
1. VDD and VDD_DATA can be tied together (t4becomes 0in this case).
2. VAA/VAAPIX/VAA_PHY can be tied together.
7.2. Power-Down Sequence
The recommended power-down sequence for the AR0234 is shown in Figure 9. The available power supplies
(VAA/VAA_PIX/VAA_PHY, VDDIO, VDDIO_PHY, VDD/VDD_PHY, and VDD_DATA) must have the separation specified
below.
Disable streaming if output is active by setting standby R0x301a[2] = 0.
The soft standby state is reached after the current row or frame, depending on configuration, has ended.
Turn off VDD_DATA.
Turn off VDD/VDD_PHY.
Turn off VDDIO_PHY.
Turn off VDDIO.
Turn off VAA/VAA_PIX/VAA_PHY
VDD_DATA (1.2)
VDD
VDD_PHY
(1.2)
VDDIO_PHY (1.8)
VDDIO (1.8/2.8)
VAA
VAA_PIX
VAA_PHY
(2.8)
EXTCLK
t1
t2
t3
t4
t5
Power Down until Next Power Up
Figure 7.2. Power-down Sequence