Lattice Semiconductor sysCLOCK ECP5 Parts list manual

www.latticesemi.com 1TN1263_1.1
November 2015 Technical Note TN1263
© 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
This usage guide describes the clock resources available in the ECP5TM and ECP5-5GTM device architecture.
Details are provided for primary clocks, edge clocks, PLLs, the internal oscillator, and clocking elements such as
clock dividers, clock multiplexers, and clock stop blocks available in the ECP5 and ECP5-5G device.
The number of PLLs, Edge clocks, and Clock dividers for each device is listed in Table 1.
Table 1. Number of PLLs, Edge Clocks, and Clock Dividers1
It is very important to note that the user needs to validate their pinout so that correct pin placement is used. The
Lattice Diamond®tools should be used to validate the pinout while designing the printed circuit board.
Clock/Control Distribution Network
ECP5 and ECP5-5G devices provide global clock distribution in the form of 16 global primary clocks. These Pri-
mary clocks can be divided into 16 clocks per each of the four quadrants; however there is a maximum of 60 unique
clock input sources. The ECP5 and ECP5-5G primary clocking structure is enhanced as it features more Edge
clock resources, more low-skew Primary clock resources and removes the Secondary clock resources.
Parameter Description LFE5-85 LFE5-45 LFE5-25
Number of PLLs General purpose PLLs. 4 4 2
Number of Edge Clocks Edge Clocks for high speed applica-
tions. 888
Number of Clock Dividers Edge Clock Dividers for DDR applica-
tions. 444
Number of PCS Clock Dividers1Clock dividers for domain crossing appli-
cations. 221
Number of DDRDLLs DDRDLL used to DDR memory and
High Speed IO interfaces 442
1. LFE5U devices do not have PCS Clock Dividers.
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
ECP5 and ECP5-5G Top-Level View
A top level view of the major clocking resources for the ECP5 and ECP5-5G devices is shown in Figure 1.
Figure 1. ECP5 and ECP5-5G Clocking Structure (LFE5-85)
Clocking Architecture Overview
Below is a brief overview of the clocking structure, elements, and PLL. Greater detail is provided starting with the
Appendix A. Primary Clock Sources and Distribution section.
Primary Clock Network
Up to 60 Primary Clock Sources (PLLs, External Inputs, SERDES, etc.) can be selected and routed to the Primary
Clock Network. This gives the user an available 60 unique clock domains in the ECP5 and ECP5-5G.
The Primary Clock Network provides low-skew, high fanout clock distribution to all synchronous elements in the
FPGA fabric. The Primary Clock Network is divided into four clocking quadrants: Top Left (TL), Bottom Left (BL),
Top Right (TR), and Bottom Right (BR). Each of these quadrants has 16 clocks that can be distributed to the fabric
in the quadrant. Initially, the Lattice Diamond software automatically routes each clock to all four quadrants; up to a
maximum of 16 clocks since each clock is routed to all four quadrants. The user can change how the clocks are
routed by specifying a preference in the Lattice Diamond software to locate the clock to specific quadrants.
Edge Clock Network
Edge clocks are low skew, high speed clock resources used to clock data into/out of the I/O logic of the ECP5 and
ECP5-5G. There are two edge clocks per bank located on the left and right sides.
Center MUX
Mid
MUX
Mid
MUX
Quadrant TL
Quadrant BL
Quadrant TR
Quadrant BR
GPLL
CLK
DIV
PIOPIOPIOPIO
CLK
DIV
PIO PIO PIO PIO
Edge Clocks
Mid
MUX
Edge Clocks
GPLL
CLK
DIV
PIO PIO PIO PIO
CLK
DIV
Edge Clocks
Mid
MUX
Edge Clocks
SERDES DCU1
Bank 0 Bank 1
Bank 2 Bank 3
Bank 6 Bank 7
PCSCLKDIVPCSCLKDIV
SERDES DCU0
Fabric
Entry
Fabric
Entry
Fabric
Entry
Fabric
Entry
14
12
16
Primary Sources Primary Sources
Primary Sources
Primary Sources
Primary
Clocks
Primary
Clocks
Primary
Clocks
Primary
Clocks
16
16
16
16
Bank 8
14 DCC
14
14
14 DCC
14
12 DCC
16 DCC
Bank 4
GPLL GPLL
Note: LFE4U devices do not have PCS Clock Dividers

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Overview of Other Clocking Elements
Edge Clock Dividers (CLKDIVF)
Clock dividers are provided to create the divided down clocks used with the I/O Mux/DeMux gearing logic (SCLK
inputs to the DDR) and drives to the Primary Clock routing to the fabric. There are four clock dividers on the ECP5
and ECP5-5G device.
PCS Clock Dividers (PCSCLKDIV)
A new clock divider is provided to create phase-matched divided-down clocks for bus-widening/narrowing circuits.
A port is provided to dynamically change the divide value of the input clock. The PCSCLKDIVwill mainly be used to
slow the clock rate from high speed SERDES applications by providing the clocks for domain crossing circuits.
There is one PCSCLKDIVper SERDES on an LFE5UM device.
Dynamic Clock Select (DCSC)
The ECP5 and ECP5-5G dynamic clock select provides run-time selectable glitchless or non-glitchless operation
between two independent clock sources to the primary clock network. This clock select allows the selection of clock
sources without leaving the dedicated clock resources in the device. There are two dynamic clock select blocks on
the ECP5 and ECP5-5G device.
Edge Clock Bridge with Clock Select (ECLKBRIDGECS)
The ECLKBRIDGECS allows non-glitchless ECLK selection between two ECLKs. The ECLKBRIDGECS will allow
user bridge ECLK from one side to the other. There are two of these elements and they are used for ECLK clock
bridging and ECLK selection.
Edge Clock Stop (ECLKSYNCB)
Each ECLK has a block to allow dynamic stopping of the edge clock. This allows the user to start and stop the
clock synchronous to an event or external signal. These are important for applications requiring exact clock timing
relationships on the inputs, such as DDR memories and video applications.
Oscillator (OSCG)
An internal programmable rate oscillator is provided. The oscillator can be used for master configuration modes
when the FPGA sources the configuration clock, Soft Error Detect (SED), and as a user logic clock source that is
available after FPGA configuration. There is one OSCG on the ECP5 and ECP5-5G device. The oscillator clock
output is routed directly to primary clocking.
The oscillator output is not a high-accuracy clock, having a +/- 15% variation in its output frequency. It is mainly
used for circuits that do not require a high degree of clock accuracy. Examples of usage would be asynchronous
logic blocks such as a timer or reset generator, or other logic that require a constantly running clock.

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
sysCLOCK PLL Overview
The sysCLOCK PLLs can be used in a variety of clock management applications such as clock injection removal,
clock phase adjustment, clock timing adjustment, and frequency synthesis (multiplication and division of a clock).
The ECP5 and ECP5-5G Clarity Designer PLL GUI shows important timing parameters such as the VCO rate and
the PLL loop bandwidth.
PLL Input sources are:
• Dedicated PLL Input Pins
• Primary Clock Routing
• Edge Clock Routing
• FPGA Fabric
Figure 2. ECP5 and ECP5-5G PLL Block Diagram
There are four PLLs on the bigger density devices LFE5-85 and LFE5-45 and two PLLs on the smaller density
LFE5-25 device. There is one PLL on each corner of the device on the bigger density devices and the smaller den-
sity devices have one PLL only on the Lower Left and Lower Right corner. Each PLL has four outputs. All four PLL
outputs can go to the Primary Clock network. Only the CLKOP and CLKOS outputs can go to the ECLK network.
Refclk Divider M Phase
Detector,
VCO, and
Loop Filter
CLKOP
Divider
(1-128)
Lock
Detect
Feedback
Clock Divider
CLK0
CLK1
SEL Refclk
ENCLKOP
CLKOP
CLKOS
CLKOS2
CLKOS3
CLKI
PLLCSOUT
PLLREFCS
VCO
CLKFB
FBKSEL
CLKOS
Divider
(1-128)
CLKOS2
Divider
(1-128)
CLKOS3
Divider
(1-128)
VCO
VCO
VCO
Internal Feedback
CLKOP, CLKOS, CLKOS2, CLKOS3
RST
STDBY
PHASESTEP
PHASEDIR
PHASESEL[1: 0] Dynamic
Phase
Adjust
PHASELOADREG
LOCK
ENCLKOS
ENCLKOS2
ENCLKOS3
CLKI
CLKI2

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
PLL Features
Dedicated PLL Inputs
The PLLs have dedicated PLL input pins that are not Primary Clock input pins. Each of the Top Left and Right cor-
ner PLLs have two pairs of dedicated PLL input pins, one from the Left/Right side bank and the other from the Top
bank. Either one of these can be used as input to the PLL.
The bottom two PLLs have one pair of dedicated input pin on the Left/Right side banks.
Figure 3. PLL Input Pins for LFE5UM/LFE5UM5G-85 and LFE5UM/LFE5UM5G-45
Figure 4. PLL Input Structure for LFE5-25
Input PLL Clock Selection (PLLREFCS)
The PLLREFCS component is a non-glitchless multiplexor that allows the user to dynamically select between two
PLL input reference clocks. The PLLREFCS has the same input clock sources as the PLL. Since the dedicated
PLL inputs are routed to the input of the PLLREFCS components a user can dynamically select between two exter-
nal reference clock inputs for the top corners of the FPGA. This mux can also be used stand-alone with the PLL in
bypass mode for more clock muxing capabilities.
Clock Injection Delay Removal
The clock injection delay removal feature of the PLL removes the delay associated with the PLL and clock tree.
This feature is typically used to reduce clock to out timing and remove the delay differences between the PLL out-
put clock and the data input. This feature is performed by aligning the input clock with a feedback clock from the
clock tree. Optional delay may also be added to the feedback path to further reduce the clock injection time.
Clock Phase Adjustment
The clock phase adjustment feature of the PLL provides the ability to set a specific phase offset between the out-
puts of the PLL. New to the ECP5 and ECP5-5G device, phase adjustments can be calculated in much finer incre-
ments since the frequency is used to calculate the available phase increments. This feature is detailed further in
the Dynamic Phase Adjustment section.
Quadrant TL
Quadrant BL
Quadrant TR
Quadrant BR
CLKI
PLL0
0
CLKI
Dedicated External PLL Input 0
PLL0
CLKI
PLL0
CLKI
P
0
P
P
C
LK
I
Dedicated External PLL Input 1
Primary Clock/Edge Clock/Fabric Inputs
Dedicated External PLL Input 0
Primary Clock/Edge Clock/Fabric Inputs
Dedicated External PLL Input 0
Dedicated External PLL Input 1
Primary Clock/Edge Clock/Fabric Inputs
Dedicated External PLL Input 0
Primary Clock/Edge Clock/Fabric Inputs
PLL_BRPLL_BL
PLL_TL PLL_TR
PLL0
Quadrant TL
Quadrant BL
Quadrant TR
Quadrant BR
PLL0
0
CLKI
PLL0
CLKI
Dedicated External PLL Input 0
Primary Clock/Edge Clock/Fabric Inputs
Dedicated External PLL Input 0
Primary Clock/Edge Clock/Fabric Inputs
PLL_BRPLL_BL

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Frequency Synthesis
The PLL can be used to multiply up or divide down an input clock.
Additional Features
In addition to the major features, the PLL has several other options that can be used in conjunction with the major
modes.
• A Standby mode to reduce power.
• Smaller phase shift increments are supported, based upon frequency.
Primary Clocks
Primary Clock Sources
The primary clock network has multiple inputs, called primary clock sources, which can be routed directly to the pri-
mary clock routing to clock the FPGA fabric.
The primary clock sources that can get to the primary clock routing are:
• Dedicated Clock Input Pins
• PLL Outputs
•CLKDIVOutputs
• Internal FPGA Fabric Entries (with minimum general routing)
• SERDES/PCS/PCSDIVclocks
• OSC Clock
All potential primary clock sources are multiplexed prior to going to the primary clock routing by a mid-mux. There
are 56 mid-mux connections and four FPGA fabric connections, 60 total, routed to a multiplexor in the center of the
chip called the centermux. From the centermux primary clocks are selected and distributed to the FPGA fabric. The
maximum number of unique clock sources is 16 bottom mid-mux sources + 12 top mid-mux sources + 14 left mid-
mux sources + 14 right mid-mux sources + 4 direct FPGA fabric entry points (from general routing) = 60. The basic
clocking structure is shown in Figure 1 and elaborated in Appendix A. Primary Clock Sources and Distribution.
Primary Clock Routing
The primary clock routing network is made up of low skew clock routing resources with connectivity to every syn-
chronous element of the device. Primary clock sources are selected at the mid-mux, then selected in the center-
mux and distributed on the primary clock routing to clock the synchronous elements in the FPGA fabric.
The primary clock routing network is divided into four sections, called quadrants. Figure 5 is a simplified view of
Figure 1.

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Figure 5. Primary Clock Routing Architecture
The centermux can source up to 16 independent primary clocks per quadrant which can clock the logic located in
that quadrant. The centermux can also route each clock source to all quadrants. The Diamond software will auto-
matically route a primary clock to all four quadrants in the FPGA.
Dedicated Clock Inputs
The ECP5 and ECP5-5G device has dedicated pins, called PCLK pins, to bring an external clock source into the
FPGA and allow them to be used as FPGA primary clocks. These inputs route directly to the Primary clock net-
work, or to Edge clock routing resources. A dedicated PCLK clock pin must always be used to route an external
clock source to FPGA logic and I/O.
If an external input clock is being sourced to a PLL, then in most cases the input clock should use a dedicated PLL
input pin. SERDES reference clocks also have dedicated SERDES reference clock pins. The ECP5 and ECP5-5G
device allows a PLL reference clock or a SERDES reference clock to come from an external Primary Clock (PCLK)
pin and route through the Primary clock network to drive the reference clock to the SERDES or the input of a PLL.
PCS Clock Dividers (PCSCLKDIV)
The ECP5 and ECP5-5G device has a new clock divider called the PCSCLKDIV. The PCSCLKDIVis built with our
PCS / IP Core interaction in mind. Its main purpose is to allow our IP cores to do multi-rate clocking for cores that
can change data rates. The specific features are:
• Capability to generate different divider clocks
• Input mux to change the divider value on-the-fly.
• Non-glitchless when the divider’s select mux input is changed.
• Data width changes in the fabric for widening / narrowing circuits. This element must allow clock domain crossing
in the fabric registers.
Center MUX
Quadrant TL
Quadrant BL
Quadrant TR
Quadrant BR
Mid
MUX
Fabric
Entry
Fabric
Entry
Fabric
Entry
Fabric
Entry
14
12
16
16
16
16
14
Primary Clock Routing to Fabric Resources in
TR Quadrant of the FPGA
Primary Clock Routing to Fabric Resources in
TL Quadrant of the FPGA
Primary Clock Routing to Fabric Resources in
TL Quadrant of the FPGA
Primary Clock Routing to Fabric Resources in
TL Quadrant of the FPGA
Mid
MUX
Mid
MUX
Mid
MUX
Primary Clock Sources Into the Mid-Mux
Primary Clock Sources Into the Mid-Mux
Primary Clock
Sources
Into the Mid-Mux
Primary Clock
Sources
Into the Mid-Mux

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
There is one PCSCLKDIVper SERDES Channel on the bottom of the device where the SERDES blocks are
located. The clock outputs of the PCSCLKDIV(CDIV1, CDIVX) are delay and phase matched to each other and
has a run-time selectable divider value. The PCSCLKDIVclock input sources are:
• Up to four TX Channel Clocks
• Up to four RX Channel Clocks
• Clock from Routing
Figure 6. PCSCLKDIV Connection Diagram
The output PCS channel clocks route directly to the input of the PCSCLKDIVwithout requiring the use of a primary
clock. The CDIV1 and CDIVX outputs route directly to the primary clock routing. Its function is to do bus widening /
narrowing circuits in the FPGA fabric to reduce the fabric frequency. The PCSCLKDIVis not suitable for DDR I/O
interfaces (ECLK to SCLK domain crossing).
Figure 7. Logical Functional Timing of PCSCLKDIV Block
Clock from routing
4 TX Channel Clocks
4 RX Channel Clocks
RST
SEL[2:0]
PCSCLKDIV
/1,/2,/4,/5,/8or /10
/1
Primary Clocks
Mid MUX
CLKI
RST
CDIV_1
CDIV_2
CDIV_4
CDIV_5
CDIV_8
CDIV_10
De-asserted RST
is registered
Asserted RST
is asynchronized
Delayed output
clocks start
toggling

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
An example design is shown in Figure 8. It is a flip-flop based clock domain crossing circuit between the CDIV1 and
the CDIVX = 2 clock outputs of the PCSCLKDIV. In this example an IP core is using the PCSCLKDIVto change the
operating frequency and bus width for a PCS (SERDES) application.
Figure 8. PCSCLKDIV Example Usage
PCSCLKDIV Component Definition
The PCSCLKDIVcomponent can be instantiated in the source code of a design as defined in this section. Figure 9,
Table 2 and Table 3 define the PCSCLKDIVcomponent. Verilog and VHDL instantiations are included.
Figure 9. PCSCLKDIV Component Symbol
Table 2. PCSCLKDIV Component Port Definition
Table 3. PCSCLKDIV Component Attribute Definition
Port Name I/O Description
CLKI I Clock Input.
RST I Reset input – Active High, Asynchronously forces all outputs low.
—RST = 0 Clock output outputs are active
—RST = 1 Clock output outputs are OFF
SEL(2:0) I Signals are used for dynamically changing divide value.
—SEL = 000, Output = ‘0’
—SEL = 001, ÷1
—SEL = 010, ÷2
—SEL = 011, ÷4
—SEL = 100, ÷5
—SEL = 101, ÷8
—SEL = 110, ÷10
—SEL = 111, Output = ‘0’
CDIV1 O Output is the same frequency as the input clock. Delay matched to CDIVX.
CDIVX O Divide by 1, 2, 4, 5, 8, 10 Output Port
Name Description Value Default
GSR Enable or Disable Global Reset Signal to Component ENABLED, DISABLED DISABLED
PCS
rxdata_0
TX_Full_Clk
rxiclk
FF FF
PCSCLK
DIV
8-bit
Data
8-bit
Data
16-bit
Data
CLKI
CLKDIVX = ‘2’
CDIV1
FF FF
8-bit
Data
8-bit
Data
16-bit
Data
SEL
txiclk
txdata_0
IP
Core
PCSCLKDIV
CLKI
RST CDIV 1
CDIVX
SEL (2 :0 )

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
PCSCLKDIV Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
component PCSCLKDIV
Generic (GSR : string);
Port (RST : in STD_LOGIC;
CLKI : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR(2 downto 0);
CDIV1 : in STD_LOGIC;
CDIVX : out STD_LOGIC);
end component;
PCSCLKDIV Instantiation
attribute GSR : string;
attribute GSR of I1 : label is “DISABLED”;
I1: PCSCLKDIV
generic map (
GSR => “DISABLED”)
port map (
RST => RST
,CLKI => CLKI
,SEL => SEL
,CDIV1 => CDIV1
,CDIVX => CDIVX);
PCSCLKDIV Usage in Verilog
Component and Attribute Declaration
module PCSCLKDIV (RST, CLKI, SEL, CDIV1, CDIVX);
parameter GSR = “DISABLED”;// “ENABLED”, “DISABLED”
input RST, CLKI;
input [2:0] SEL;
output CDIVX;
endmodule
PCSCLKDIV Instantiation
defparam I1.GSR = “DISABLED”;
PCSCLKDIV I1 (
.RST (RST)
,.CLKI (CLKI)
,.SEL (SEL)
,.CDIV1 (CDIV1)
,.CDIVX (CDIVX));

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Dynamic Clock Select (DCSC)
The ECP5 and ECP5-5G device has two dynamic clock select (DCS) blocks that can drive to any or all the quad-
rants. The inputs to the DCS block come from all the output of MIDMUXs and local routing that is located at the
center of the PLC array core. The output of the DCS is connected to one of the inputs of Primary Clock Center
MUX.
Each DCS can select between two independent input clock sources. There are two modes of clock switching, a
glitchless mode of operation, or a non glitchless mode where the DCS operates as a regular mux. Figure 10 and
Figure 11 show the glitchless / non-glitchless modes of operation. It should be noted that the clock source used as
feedback into the GPLL should not be switched when using the DCS as it will lead to loss of lock for the GPLL.
As indicated there are two modes of clock switching. In non-glitchless mode (input MODESEL=’1’) the DCS acts
like a regular mux, allowing glitches and runt pulses on the output, depending on when the clock is switched. The
SEL and MODESEL inputs are driven by signals from the general routing fabric and are used to support the clock
switching feature in the DCS.
In glitchless mode (input MODESEL=’0’) the DCS avoids glitches or runt pulses on the output clock, regardless of
when the enable signal is toggled. In order to switch between clocks glitchlessly, both input clocks must be oscillat-
ing; otherwise the output clock will be ‘0’.
For glitchless operation, the “DCSMODE” attribute sets the behavior of the DCS output. The additional attribute val-
ues and their functions are shown in Table 5.

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
DCS Timing Diagrams
Figure 10 shows timing diagrams to show the operation of the DCS in Glitchless mode in conjunction with the DCS-
MODE attribute.
Figure 10. Timing Diagrams by “DCSMODE” Attribute Setting, Glitchless Operation (MODESEL=’0’)
CLK0
CLK1
SEL[3:0] “0001” “0010”
DCSOUT
“0001”
SEL[3:0] Changes to “0010”:
- Wait for CLK0 rising edge.
- Switch output at CLK1 rising edge.
SEL[3:0] Changes to “0001”:
- Wait for CLK1 rising edge.
- Switch output at CLK0 rising edge.
DCSMODE = “POS”
CLK0
CLK1
SEL[3:0] “0001” “0010”
DCSOUT
“0001”
SEL[3:0] Changes to “0010”:
- Wait for CLK0 falling edge.
- Switch output at CLK1 falling edge.
SEL[3:0] Changes to “0001”:
- Wait for CLK1 falling edge.
- Switch output at CLK0 falling edge.
DCSMODE = “NEG”
CLK0
SEL[3:0] “0001” “0010”
- Switch low @CLK0 falling edge.
- The attribute name indicates which clock will toggle. Other
values of SEL will cause the output to remain low.
- SEL must not change during setup prior to rising clock.
DCSMODE = “CLK<0-3>_LOW”
DCSOUT
CLK0
SEL[3:0] “0001” “0010”
- Switch low @CLK0 rising edge.
- The attribute name indicates which clock will toggle. Other
values of SEL will cause the output to remain high.
- SEL must not change during setup prior to rising clock.
DCSMODE = “CLK<0-3>_HIGH”
DCSOUT

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Figure 11. DCS Operation, Non-Glitchless Operation (MODESEL=’1’)
DCSC Component Definition
The DCSC component can be instantiated in the source code of a design as defined in this section.
Figure 12. DCSC Component Symbol
Table 4. DCSC Component Port Definition
Port Name I/O Description
CLK0 I Clock Input port 0 – Default.
CLK1 I Clock Input port 1
SEL[1:0] I Input Clock Select bit (See Table 6 below)
MODESEL I Selects Glitchless (‘0’) or Non-Glitchless
(‘1’) behavior.
DCSOUT O Clock Output Port
CLK0
CLK1
SEL[3:0] “0001” “0010”
DCSOUT
“0001”
DCSC
CLK 0
CLK 1
SEL [1 :0 ]
DCSOUT
MODESEL

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
DCSMODE Attribute
Table 5 provides the behavior of the DCS output based on the setting of the DCSMODE attribute when the pin
MODESEL =’0’. The MODESEL pin is dynamic and can toggle during operation. Table 5 is only valid when MODE-
SEL =’0’.
Table 5. DCSC – DCSMODE Attribute Table when MODESEL=’0’
DCSC Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
COMPONENT DCSC
GENERIC(DCSMODE : string := “POS”);
PORT (CLK0 :IN STD_LOGIC;
CLK1 :IN STD_LOGIC;
SEL :IN STD_LOGIC_VECTOR(1 downto 0);
MODESEL :IN STD_LOGIC;
DCSOUT :OUT STD_LOGIC);
END COMPONENT;
DCSC Instantiation
attribute DCSMODE : string;
attribute DCSMODE of DCSinst0 : label is "POS";
I1: DCSC
generic map(
DCSMODE => “POS”)
port map (
CLK0 => CLK0
,CLK1 => CLK1
,SEL => SEL
,MODESEL => MODESEL
,DCSOUT => DCSOUT);
Attribute Name Description
SEL[1:0] Attribute
Value2’b01 2’b10 2’b00/2’b11
DCSMODE Attributes Falling Edge Triggered Clk0 Clk1 0 NEG
Rising Edge Triggered Clk0 Clk1 1 POS
Disabled Output is Low, Clk0 Clk0 0 0 CLK0_LOW
Disabled Output is High, Clk0 Clk0 1 1 CLK0_HIGH
Disabled Output is Low, Clk0 0 Clk1 0 CLK1_LOW
Disabled Output is High, Clk0 1 Clk1 1 CLK1_HIGH
Clk0 Buffered Clk0 Clk0 Clk0 CLK0
Clk1 Buffered Clk1 Clk1 Clk1 CLK1
Tie Low 0 0 0 LOW
Tie High 1 1 1 HIGH
MODESEL= “1” Non-Glitchless Clk0 Clk1 0 -

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
DCSC Usage in Verilog
Component and Attribute Declaration
module DCSC(CLK0,CLK1,CLK2,CLK3,SEL,MODESEL,DCSOUT);
input CLK0;
input CLK1;
input [1:0] SEL;
input MODESEL;
output DCSOUT;
endmodule
DCSC Instantiation
defparam DCSInst0.DCSMODE = “POS”;
DCSC DCSInst0 (
.CLK0 (CLK0)
,.CLK1 (CLK1)
,.SEL (SEL)
,.MODESEL (MODESEL)
,.DCSOUT (DCSOUT));
Dynamic Clock Control (DCCA)
The ECP5 and ECP5-5G device has a Dynamic Clock Control feature which allows internal logic dynamically to
enable or disable quadrant primary clock network. The disable function will not create glitch and increase the clock
latency to the primary clock network. Also, this dynamic clock control function can be disabled by a configuration
memory fuse to always enable the primary clock network.
This DCC controls the clock sources from the Primary CLOCK MIDMUX before they are fed to the Primary Center
MUXs that drive the quadrant clock network. When a clock network is disabled, all the logic fed by that clock does
not toggle, hence reducing the overall power consumption of the device.
The ECP5 and ECP5-5G device clock architecture allows both DCC and DCS to function at the same. It should be
noted that the clock source used as feedback into the GPLL should always keep enable signal “high” in the DCC,
otherwise it will lead to loss of lock for the GPLL when toggling the enable signal.
Figure 13. Glitchless DCC Functional Waveform
tsutsu
CLK (input)
CE
CLK (output)

16
ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
DCCA Component Definition
The DCCA component can be instantiated in the source code of a design as defined in this section. Figure 14 and
Table 6 show the DCCA definitions.
Figure 14. DCCA Component Symbol
Table 6. DCCA Component Port Definition
DCCA Usage in VHDL
Component Instantiation
library lattice;
use lattice.components.all;
Component and Attribute Declaration
COMPONENT DCCA
PORT (CLKI :IN STD_LOGIC;
CE :IN STD_LOGIC;
CLKO :OUT STD_LOGIC);
END COMPONENT;
DCCA Instantiation
I1: DCCA
port map (
CLKI => CLKI
,CE => CE
,CLKO => CLKO);
DCCA Usage in Verilog
Component and Attribute Declaration
module DCCA(CLKI,CE,CLKO);
input CLKI;
input CE;
output CLKO;
endmodule
DCCA Instantiation
DCCA DCSInst0 (
.CLKI (CLKI)
,.CE (CE)
,.CLKO (CLKO));
Port Name I/O Description
CLKI I Clock Input port.
CE I Clock Enable port
—CE = 0 CLKO is disabled (CLKO = ’0’)
—CE = 1 CLKO is enabled (CLKO = CLKI)
CLKO O Clock Output Port
DCCA
CLKI
CE
CLKO

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Internal Oscillator (OSCG)
The OSCG element performs multiple functions on the ECP5 and ECP5-5G device. It is used for configuration,
SED, as well as optionally in user mode. In user mode, the OSCG element has the following features:
• It permits a design to be fully self-clocked, as long as the quality of the OSCG element’s silicon-based oscillator
is adequate.
• If it’s unused it can be turned off for power savings.
• It has an input to dynamically control standby/normal operation.
• It has a direct connection to primary clock routing through the left mid-mux.
• It can be configured for operation at a wide range of frequencies via configuration bits.
OSCG Component Definition
The OSCG component can be instantiated in the source code of a design as defined in this section. Figure 15 and
Table 7 below show the OSCG definitions.
Figure 15. OSCG Component Symbol
Table 7. OSCG Component Port Definition
Table 8. OSCG Component Attribute Definition
OSCG Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
component OSCG
Port (OSC : out STD_LOGIC);
end component;
OSCG Instantiation
I1: OSCG
port map (
OSC => OSC);
Port Name I/O Description
OSC O Clock Output Port
Name Description Value Default
DIVSelects Divider
Value
2 (~155.0 MHz) – 128 (~2.4 MHz) 2.4 MHz
OSC
OSCG

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
OSCG Usage in Verilog
Component and Attribute Declaration
module OSCG (OSC);
output OSC;
endmodule
OSCG Instantiation
OSCG I1 (.OSC(OSC))
Edge Clocks
Each ECP5 and ECP5-5G device I/O bank has four ECLK resources. These clocks, which have low injection time
and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with
high fan-out capability. Refer to Appendix B. EDGE CLOCK Sources and Connectivity for detailed information on
the ECLK locations and connectivity.
The sources of edge clocks are:
• Dedicated Clock (PCLK) pins
• DLLDEL output
• PLL outputs (CLKOP & CLKOS)
• ECLK Bridge
• Internal nodes
The ECP5 and ECP5-5G device has Edge Clock (ECLK) at the Left side and right side of the device. There are two
ECLK network per bank IO. ECLK Input MUX collects all clock sources available shown in figure below. There are
two ECLK Input MUXs, one on the left side and one on the right side. Each of these MUX will generate total of four
ECLK Clock sources. Two of them drive the upper IO bank and two of them drive the lower IO bank. Two out of four
also drive the ECLK Bridge Switch Block to form an ECLK Bridge high speed clock before drive the ECLK Tree Net-
work.
Figure 16. Edge Clock Sources Per Bank
Top Left/ Right PCLK Pin
Top Right/Left PLL CLKOP
Top Left/ Right DLLDEL Output
Top Right/Left PLL CLKOS
Bottom Right/Left PLL CLKOP
Bottom Right/Left PLL CLKOS
Bottom Left/ Right PCLK Pin
Bottom Left/ Right DLLDEL Output
From Routing
ECLKSYNC
To ECLK of other
bank on same side
To ECLKBRIDGE to go
to other side
From
ECLKBRIDGE
From ECLK of
other bank on
same side
ECLK Tree

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
Edge Clock Dividers (CLKDIVF)
There are four edge clock dividers available in the ECP5 and ECP5-5G device, two per side of the device. The
clock divider provides a single divided output with available divide values of 2 or 3.5. The inputs to the clock divid-
ers are the edge clocks, PLL outputs and Primary Clock Input pins. The outputs of the clock divider drive the pri-
mary clock network and are mainly used for DDR I/O domain crossing.
CLKDIVF Component Definition
The CLKDIVF component can be instantiated in the source code of a design as defined in this section. Figure 17,
Table 9, and Table 10 define the CLKDIVF component. Verilog and VHDL instantiations are included.
Figure 17. CLKDIVF Component Symbol
Table 9. CLKDIVF Component Port Definition
Table 10. CLKDIVF Component Attribute Definition
The ALIGNWD input is intended for use with high-speed data interfaces such as DDR or 7:1 LVDS Video.
CLKDIVF Usage in VHDL
Component Instantiation
Library lattice;
use lattice.components.all;
Component and Attribute Declaration
component CLKDIVF
Generic (DIV : string;
GSR : string);
Port (RST : in STD_LOGIC;
CLKI : in STD_LOGIC;
ALIGNWD : in STD_LOGIC;
CDIVX : out STD_LOGIC);
end component;
Port Name I/O Description
CLKI I Clock Input.
RST I Reset input – Active High, Asynchronously forces all
outputs low.
—RST = 0 Clock outputs are active
— RST = 1 Clock outputs are OFF
ALIGNWD I Signal is used for word alignment.
When enabled it slips the output one
cycle relative to the input clock.
CDIVX O Divide by 2 or 3.5 Output Port
Name Description Value Default
GSR Enable or Disable Global Reset
Signal to Component
ENABLED, DISABLED DISABLED
DIVCLK Divider Value 2.0 or 3.5 2.0
CLKDIVF
CLKI
RST
ALIGNWD
CDIVX

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ECP5 and ECP5-5G sysCLOCK
PLL/DLL Design and Usage Guide
CLKDIVF Instantiation
attribute DIV : string;
attribute DIV of I1 : label is “2.0”;
attribute GSR : string;
attribute GSR of I1 : label is “DISABLED”;
I1: CLKDIVF
generic map (DIV => “2.0”
,GSR => “DISABLED”)
port map (RST => RST
,CLKI => CLKI
,ALIGNWD => ALIGNWD
,CDIVX => CDIVX);
CLKDIVF Usage in Verilog
Component and Attribute Declaration
module CLKDIVF (RST, CLKI, ALIGNWD, CDIVX);
parameter DIV = “2.0”; // “2.0”, “3.5”
parameter GSR = “DISABLED”; // “ENABLED”, “DISABLED
input RST, CLKI, ALIGNWD;
output CDIVX;
endmodule
CLKDIVF Instantiation
defparam I1.DIV = “2.0”;
defparam I1.GSR = “DISABLED”;
CLKDIVF I1 (
.RST (RST)
,.CLKI (CLKI)
,.ALIGNWD (ALIGNWD)
,.CDIVX (CDIVX));
Edge Clock Bridge (ECLKBRIDGECS)
ECLK Clock Bridge provides to bridge the ECLK for banks on the same side or the ECLK of the left side and the
right side. The ECLK Bridge enhances the communication of high speed clocks of the two edges with minimum
skew to ECLK tree.
There are two ECLK bridge components in the ECP5 and ECP5-5G device. There are two ECLK muxes on the left
and two ECLK muxes on the right and they allow a user to bridge edge clocks to the left and right sides of the chip
with minimal skew.
In the edge clock bridge there is a non-glitchless clock select mux that allows a design to switch between two differ-
ent clock sources for each edge clock. This clock select mux is instantiated using the ECLKBRIDGECS primitive.
Not all edge clocks can drive the ECLKBRIDGECS, one of the two ECLKs on the left and right side can be bridged.
When connected to the ECLKBRIDGECS it would use up the ECLK1 of both banks on the left side and ECLK0 of
both banks on the right side of the device.