Lattice Semiconductor CertusPro-NX Parts list manual

CertusPro-NX SerDes/PCS Usage Guide
Preliminary
Technical Note
FPGA-TN-02245-0.81
May 2021

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
2 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
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CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 3
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Contents
Glossary ..............................................................................................................................................................................11
Introduction................................................................................................................................................................14
Features......................................................................................................................................................................15
Using This Technical Note...........................................................................................................................................16
Standards Supported..................................................................................................................................................17
Architecture Overview................................................................................................................................................18
Device Architecture...........................................................................................................................................18
SerDes/PCS Architecture...................................................................................................................................19
PCI Express Architecture ...................................................................................................................................20
MPCS Architecture ............................................................................................................................................22
Reference Clock Architecture............................................................................................................................24
Multi-Protocol Design Consideration................................................................................................................25
SerDes/PCS Block Signal Interface ....................................................................................................................25
Detailed Interface Descriptions.........................................................................................................................27
Control and Status Signals.................................................................................................................................43
Detailed Channel Block Diagram.......................................................................................................................44
SerDes/PCS Function Description ...............................................................................................................................47
SerDes (PMA) ....................................................................................................................................................47
PMA Controller..................................................................................................................................................49
PCI Express PCS .................................................................................................................................................49
MPCS .................................................................................................................................................................50
Quad Common ..................................................................................................................................................70
Reference Clock.................................................................................................................................................70
Clocks and Reset.........................................................................................................................................................72
MPCS Channel Clock Detail ...............................................................................................................................72
MPCS Quad Clock Detail....................................................................................................................................76
MPCS Quad-to-Quad Clock Connection............................................................................................................77
Clock Frequency ................................................................................................................................................78
Application Case................................................................................................................................................79
PMA Clock Divider.............................................................................................................................................85
SerDes/PCS Reset..............................................................................................................................................85
SerDes Equalization ....................................................................................................................................................89
Tx Equalization ..................................................................................................................................................90
Rx Equalization..................................................................................................................................................92
SerDes/PCS Debug Capabilities ..................................................................................................................................93
Loopback Mode.................................................................................................................................................93
Signal Detector..................................................................................................................................................95
Loss of Lock .......................................................................................................................................................96
ECO Editor .........................................................................................................................................................97
Eye Monitor.......................................................................................................................................................97
SerDes/PCS Register Access....................................................................................................................................98
Register Access Bus...........................................................................................................................................98
Register Space...................................................................................................................................................99
Protocol Mode......................................................................................................................................................100
PCI Express Mode............................................................................................................................................100
Generic 8B/10B Mode.....................................................................................................................................100
PMA Only Mode..............................................................................................................................................101
Ethernet Mode................................................................................................................................................101
SLVS-EC Mode .................................................................................................................................................103
DisplayPort Mode............................................................................................................................................104
CoaXPress Mode .............................................................................................................................................104
SerDes/PCS Block Latency.....................................................................................................................................105

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Other Design Considerations ................................................................................................................................106
Simulation of the SerDes/PCS .........................................................................................................................106
PMA PLL Filter .................................................................................................................................................106
Reference Clock Source Selection ...................................................................................................................107
Spread Spectrum Clocking Support.................................................................................................................108
Unused Quad/Channel and Power Supply ......................................................................................................108
Electrical Idle ...................................................................................................................................................109
Multiple Data Rate Support.............................................................................................................................109
SerDes/PCS Generation in Radiant Software........................................................................................................110
Configuration GUI............................................................................................................................................110
Attribute Summary..........................................................................................................................................111
Primitive ..........................................................................................................................................................117
Appendix A. Configuration Registers ................................................................................................................................122
A.1. PMA Registers........................................................................................................................................................122
A.1.1. Register Address .................................................................................................................................................122
A.1.2. Register Description ...........................................................................................................................................122
A.2. MPCS Registers ......................................................................................................................................................132
A.2.1. Register Address .................................................................................................................................................132
A.2.2. Register Description ...........................................................................................................................................134
Appendix B. 8B/10B Symbol Coding .................................................................................................................................155
Appendix C. Calculating Parameters for SerDes PLL.........................................................................................................161
Appendix D. Using Reveal SerDes Debug Tool..................................................................................................................167
References ........................................................................................................................................................................168
Technical Support Assistance ...........................................................................................................................................169
Revision History ................................................................................................................................................................170

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Figures
Figure 5.1. CertusPro-NX 100k Device Block Diagram........................................................................................................18
Figure 5.2. CertusPro-NX SerDes/PCS Quad Architecture ..................................................................................................20
Figure 5.3. PCI Express Hard IP Architecture ......................................................................................................................21
Figure 5.4. PCI Express Link Layer Functional Diagram.......................................................................................................22
Figure 5.5. MPCS Quad Block Diagram ...............................................................................................................................22
Figure 5.6. MPCS Channel Functional Block Diagram.........................................................................................................23
Figure 5.7. CertusPro-NX 100k Device SerDes Reference Clock Architecture ....................................................................24
Figure 5.8. PCI Express Hard IP Mode.................................................................................................................................25
Figure 5.9. PIPE Mode.........................................................................................................................................................26
Figure 5.10. MPCS Mode ....................................................................................................................................................26
Figure 5.11. PMA Only Mode..............................................................................................................................................27
Figure 5.12. Detailed Channel Block Diagram of MPCS-8B/10B Mode ..............................................................................45
Figure 5.13. Detailed Channel Block Diagram of MPCS-64B/66B Mode ............................................................................45
Figure 5.14. Detailed Channel Block Diagram of MPCS-PMA Only Mode ..........................................................................46
Figure 6.1. Simplified Block Diagram of the SerDes (PMA) ................................................................................................47
Figure 6.2. PCI Express AC Coupling Capacitors Location ...................................................................................................48
Figure 6.3. PMA Controller Block Diagram .........................................................................................................................49
Figure 6.4. PCI Express PCS & PMA Controller Block Diagram ...........................................................................................50
Figure 6.5. MPCS 8B/10B PCS Block Diagram .....................................................................................................................50
Figure 6.6. Tx Gearing Case I...............................................................................................................................................53
Figure 6.7. Tx Gearing Case II..............................................................................................................................................54
Figure 6.8. Rx Gearing Case I ..............................................................................................................................................54
Figure 6.9. Rx Gearing Case II .............................................................................................................................................55
Figure 6.10. Byte Shifting for Word Alignment Pattern......................................................................................................55
Figure 6.11. Word Aligner Block Diagram...........................................................................................................................57
Figure 6.12. Link Synchronization FSM...............................................................................................................................58
Figure 6.13. Before 2-byte Boundary Alignment................................................................................................................59
Figure 6.14. After 2-byte Boundary Alignment...................................................................................................................59
Figure 6.15. Data Stream before Word Alignment.............................................................................................................60
Figure 6.16. Data Stream after Word Alignment................................................................................................................60
Figure 6.17. Bit Mapping of Input Data ..............................................................................................................................60
Figure 6.18. The Expected Location of Synchronization Code............................................................................................61
Figure 6.19. SKIP Pattern Format........................................................................................................................................61
Figure 6.20. SKIP Pattern Mask Code .................................................................................................................................62
Figure 6.21. FIFO High/Low Water Line..............................................................................................................................62
Figure 6.22. Lane Alignment Pattern Mask Code ...............................................................................................................63
Figure 6.23. Data Shifting for Alignment ............................................................................................................................63
Figure 6.24. 64B/66B PCS Channel Block Diagram .............................................................................................................64
Figure 6.25. XGMII vs. MPCS-Fabric Interface ....................................................................................................................65
Figure 6.26. 64B/66B PCS Tx FIFO Write Operation Case I.................................................................................................66
Figure 6.27. 64B/66B PCS Tx FIFO Write Operation Case II................................................................................................67
Figure 6.28. 64B/66B PCS Rx FIFO Read Operation Case I..................................................................................................67
Figure 6.29. 64B/66B PCS Rx FIFO Read Operation Case II.................................................................................................67
Figure 6.30. PMA Only Mode Block Diagram......................................................................................................................69
Figure 6.31. Quad Reference Clock Source.........................................................................................................................71
Figure 7.1. 8B/10B PCS Channel Clock Diagram .................................................................................................................72
Figure 7.2. 64B/66B PCS Channel Clock Diagram ...............................................................................................................73
Figure 7.3. PMA Only Mode Clock Diagram........................................................................................................................75
Figure 7.4. Quad Clock Distribution Diagram .....................................................................................................................76
Figure 7.5. Two Quads Clock Connection ...........................................................................................................................77
Figure 7.6. Single Quad Clock Connection ..........................................................................................................................78
Figure 7.7. Case I-a Clock Structure ....................................................................................................................................79

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Figure 7.8. Case I-b Clock Structure ....................................................................................................................................79
Figure 7.9. Case II-a Clock Structure ...................................................................................................................................80
Figure 7.10. Case II-b Clock Structure.................................................................................................................................80
Figure 7.11. Case II-c Clock Structure .................................................................................................................................80
Figure 7.12. Case III-a Clock Structure ................................................................................................................................81
Figure 7.13. Case IV-a Clock Structure................................................................................................................................82
Figure 7.14. Case IV-b Clock Structure................................................................................................................................83
Figure 7.15. 64B/66B PCS with Using GPLL.........................................................................................................................84
Figure 7.16. 64B/66B PCS without using GPLL (Case I) .......................................................................................................84
Figure 7.17. 64B/66B PCS without Using GPLL (Case II) .....................................................................................................85
Figure 7.18. MPCS Mode Reset Sequence (Tx Path)...........................................................................................................87
Figure 7.19. MPCS Mode Reset Sequence (Rx Path)...........................................................................................................87
Figure 7.20. EPCS Mode Reset Sequence (Tx Path) ............................................................................................................88
Figure 7.21. EPCS Mode Reset Sequence (Rx Path)............................................................................................................88
Figure 8.1. Signal Distortion for Typical Backplane Application .........................................................................................89
Figure 8.2. Typical Backplane Application with Tx Equalizer ..............................................................................................89
Figure 8.3. Typical Backplane Application with Rx Equalizer ..............................................................................................90
Figure 8.4. Transmit Equalizer Block Diagram ....................................................................................................................90
Figure 8.5. Definition of Tx Voltage Levels..........................................................................................................................91
Figure 8.6. Receive Equalizer Block Diagram ......................................................................................................................92
Figure 9.1. PMA Loopback Mode........................................................................................................................................93
Figure 9.2. 8B/10B PCS Near-End Parallel Loopback Mode................................................................................................94
Figure 9.3. 8B/10B PCS Far-End Parallel Loopback Mode...................................................................................................94
Figure 9.4. 64B/66B PCS Loopback Mode...........................................................................................................................95
Figure 9.5. Signal Detector..................................................................................................................................................95
Figure 9.6. CDR PLL Locking Flow........................................................................................................................................96
Figure 10.1. Burst Read Transaction...................................................................................................................................98
Figure 10.2. Back-to-Back Read and Write Transaction......................................................................................................98
Figure 10.3. Back-to-Back Write and Read Transaction......................................................................................................99
Figure 13.1. Example Connection to Analog Power and Reference Pins..........................................................................107
Figure 14.1. MPCS Configuration GUI...............................................................................................................................110
Tables
Table 4.1. Standards Supported by the SerDes/PCS...........................................................................................................17
Table 5.1. Maximum Number of SerDes/PCS Channels per CertusPro-NX Device.............................................................19
Table 5.2. Maximum Number of PCI Express Blocks per CertusPro-NX Device..................................................................19
Table 5.3. Block Usage for the Corresponding SerDes/PCS Mode......................................................................................20
Table 5.4. PCI Express Link Layer Quad Lane Mapping.......................................................................................................21
Table 5.5. 10GBASE-R Lane Mapping..................................................................................................................................24
Table 5.6. CertusPro-NX Mixed Protocols within a Quad ...................................................................................................25
Table 5.7. MPCS Interface...................................................................................................................................................27
Table 5.8. EPCS Interface ....................................................................................................................................................30
Table 5.9. PIPE Interface.....................................................................................................................................................31
Table 5.10. LMMI Interface.................................................................................................................................................37
Table 5.11. Other Signals ....................................................................................................................................................38
Table 5.12. Data Bus Sharing and Mapping ........................................................................................................................39
Table 5.13. Control and Status Signals Functions (8B/10B PCS) .........................................................................................43
Table 5.14. Control and Status Signals Functions (64B/66B PCS).......................................................................................43
Table 6.1. Operation Range for FRef, FVCO, Fbit, and FPMA ......................................................................................................48
Table 6.2. Bit Mapping of Tx Data Bus................................................................................................................................51
Table 6.3. Bit Mapping of Rx Data Bus................................................................................................................................52

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Preliminary Technical Note
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Table 6.4. Tx FIFO Usage.....................................................................................................................................................54
Table 6.5. Disparity Combinations......................................................................................................................................55
Table 6.6. Example Settings for XAUI and GigE ..................................................................................................................58
Table 6.7. PMA Only Mode Data Bus..................................................................................................................................69
Table 6.8. Channel Alignment within One Quad ................................................................................................................70
Table 6.9. Channel Alignment between Two Quads...........................................................................................................70
Table 7.1. 8B/10B PCS Channel Clock .................................................................................................................................72
Table 7.2. 64B/66B PCS Channel Clock ...............................................................................................................................74
Table 7.3. PMA Only Mode Channel Clock .........................................................................................................................75
Table 7.4. Quad Clock .........................................................................................................................................................77
Table 7.5. Recommend Settings for Some Protocols..........................................................................................................78
Table 7.6. Reset and Power Control Signals .......................................................................................................................85
Table 8.1. Description of Tx Voltage Levels ........................................................................................................................90
Table 8.2. PCIe Tx Preset Ratios and Corresponding Coefficient Values ............................................................................91
Table 9.1. Loss of Signal Conditions....................................................................................................................................96
Table 9.2. Typical Duration Time for Each Lock Step..........................................................................................................96
Table 10.1. Access Type Definition .....................................................................................................................................99
Table 11.1. PCI Express Recommend AC Capacitance ......................................................................................................100
Table 11.2. GigE Configuration and IDLE Ordered Sets Definition ...................................................................................102
Table 11.3. XAUI IDLE Ordered Sets Definition.................................................................................................................102
Table 11.4. 64B/66B Blocks Formats ................................................................................................................................103
Table 11.5. SLVS-EC Baud Rate .........................................................................................................................................103
Table 11.6. General Parameters of Receiver Characteristics for SLVS-EC ........................................................................104
Table 11.7. DisplayPort Recommend AC Capacitance......................................................................................................104
Table 12.1. Transmit/Receive SerDes/PCS Latency ..........................................................................................................105
Table 13.1. Recommended External Reference Resistor for Serval Differential Impedance Applications.......................107
Table 13.2. PCSREFMUX Usage.........................................................................................................................................107
Table 13.3. SerDes Power Pins Numbering ......................................................................................................................109
Table 13.4. Electrical Idle Related Signals.........................................................................................................................109
Table 14.1. Protocol Descriptions.....................................................................................................................................110
Table 14.2. Attributes Summary.......................................................................................................................................111
Table 14.3. Attributes Descriptions ..................................................................................................................................115
Table 14.4. Pin-to-Pin Connection ....................................................................................................................................117
Table A. 1. Register Address .............................................................................................................................................122
Table A. 2. Control Register 0 [reg00]...............................................................................................................................122
Table A. 3. Clock Count for Error Counter Decrement [reg01].........................................................................................123
Table A. 4. Error Counter Threshold –Rx Idle Detect Max Latency [reg02] .....................................................................123
Table A. 5. Rx Impedance Ratio [reg03]............................................................................................................................123
Table A. 6. Tx PLL F Settings and PCLK Ratio [reg04] ........................................................................................................123
Table A. 7. Tx PLL M & N Settings [reg05] ........................................................................................................................124
Table A. 8. Rx PLL F Settings and PCLK Ratio [reg06]........................................................................................................124
Table A. 9. Rx PLL M & N Settings [reg07] ........................................................................................................................125
Table A. 10. 250ns Timer Base Count [reg08]...................................................................................................................125
Table A. 11. Tx Impedance Ratio [reg09]..........................................................................................................................125
Table A. 12. Tx Post-Cursor Ratio [reg0a].........................................................................................................................125
Table A. 13. Tx Pre-Cursor Ratio [reg0b] ..........................................................................................................................126
Table A. 14. Power down Feature [reg0e]........................................................................................................................126
Table A. 15. Tx Amplitude Ratio [reg18]...........................................................................................................................127
Table A. 16. CDR PLL Frequency Comparator Maximum Difference [reg21] ...................................................................127
Table A. 17. CDR PLL Frequency Comparator Counter [reg22] ........................................................................................127
Table A. 18. EI4 Mode Register [reg23] ............................................................................................................................127
Table A. 19. PMA Controller Status [reg30]......................................................................................................................127
Table A. 20. PRBS Control Register [reg64] ......................................................................................................................128

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Table A. 21. PRBS Error Counter Register [reg65] ............................................................................................................129
Table A. 22. PHY Reset Override Register [reg66] ............................................................................................................129
Table A. 23. PHY Power Override Register [reg67]...........................................................................................................129
Table A. 24. Transmit PLL Current Charge Pump [reg69] .................................................................................................129
Table A. 25. Receive PLL Current Charge Pump [reg6a] ...................................................................................................130
Table A. 26. PCS Loopback Control [reg74] ......................................................................................................................130
Table A. 27. CDR PLL Manual Control [reg79]...................................................................................................................131
Table A. 28. PMA Status [reg7f]........................................................................................................................................131
Table A. 29. Update Settings Command Register [reg80] ................................................................................................132
Table A. 30. Register Address ...........................................................................................................................................132
Table A. 31. MPCS Data Path Selection [reg00]................................................................................................................134
Table A. 32. Tx Path Control [reg10].................................................................................................................................135
Table A. 33. 8B/10B Encoder Control [reg11]...................................................................................................................135
Table A. 34. Rx Path Control [reg20].................................................................................................................................136
Table A. 35. MPCS Rx Path Status [reg21] ........................................................................................................................136
Table A. 36. 8B/10B Decoder Control [reg22] ..................................................................................................................137
Table A. 37. Word Alignment Control [reg30] ..................................................................................................................137
Table A. 38. Primary Word Alignment Pattern Byte 0 [reg31]..........................................................................................137
Table A. 39. Primary Word Alignment Pattern Byte 1 [reg32]..........................................................................................138
Table A. 40. Primary Word Alignment Pattern MSB [reg33] ............................................................................................138
Table A. 41. Secondary Word Alignment Pattern Byte 0 [reg34] .....................................................................................138
Table A. 42. Secondary Word Alignment Pattern Byte 1 [reg35] .....................................................................................138
Table A. 43. Secondary Word Alignment Pattern MSB [reg36] ........................................................................................138
Table A. 44. Word Alignment Pattern Mask Code Byte 0 [reg37] ....................................................................................138
Table A. 45. Word Alignment Pattern Mask Code Byte 1 [reg38] ....................................................................................138
Table A. 46. Word Alignment Pattern Mask Code MSB [reg39] .......................................................................................139
Table A. 47. Sync_Det FSM Configuration 0 [reg3a].........................................................................................................139
Table A. 48. Sync_Det FSM Configuration 1 [reg3b].........................................................................................................139
Table A. 49. Sync_Det FSM Configuration 2 [reg3c] .........................................................................................................139
Table A. 50. Sync_Det FSM Configuration 3 [reg3d].........................................................................................................139
Table A. 51. Number of Bit Slipped during Word Alignment [reg3e] ...............................................................................140
Table A. 52. Primary Sync_Det Pattern Byte 0 [reg3f]......................................................................................................140
Table A. 53. Primary Sync_Det Pattern Byte 1 [reg40] .....................................................................................................140
Table A. 54. Primary Sync_Det Pattern Byte 2 [reg41] .....................................................................................................140
Table A. 55. Primary Sync_Det Pattern Byte 3 [reg42] .....................................................................................................140
Table A. 56. Primary Sync_Det Pattern Byte MSB [reg43]................................................................................................140
Table A. 57. Secondary Sync_Det Pattern Byte 0 [reg44].................................................................................................141
Table A. 58. Secondary Sync_Det Pattern Byte 1 [reg45].................................................................................................141
Table A. 59. Secondary Sync_Det Pattern Byte 2 [reg46].................................................................................................141
Table A. 60. Secondary Sync_Det Pattern Byte 3 [reg47].................................................................................................141
Table A. 61. Secondary Sync_Det Pattern Byte MSB [reg48] ...........................................................................................141
Table A. 62. Sync_Det Pattern Mask Code Byte 0 [reg49]................................................................................................141
Table A. 63. Sync_Det Pattern Mask Code Byte 1 [reg4a] ................................................................................................141
Table A. 64. Sync_Det Pattern Mask Code Byte 2 [reg4b]................................................................................................141
Table A. 65. Sync_Det Pattern Mask Code Byte 3 [reg4c] ................................................................................................141
Table A. 66. Sync_Det Pattern Mask Code MSB [reg4d]...................................................................................................141
Table A. 67. Lane Alignment Control [reg50]....................................................................................................................142
Table A. 68. Maximum Lane-to-lane Skew [reg51]...........................................................................................................142
Table A. 69. Primary Lane Alignment Pattern Byte 0 [reg52] ...........................................................................................142
Table A. 70. Primary Lane Alignment Pattern Byte 1 [reg53] ...........................................................................................142
Table A. 71. Primary Lane Alignment Pattern Byte 2 [reg54] ...........................................................................................142
Table A. 72. Primary Lane Alignment Pattern Byte 3 [reg55] ...........................................................................................143
Table A. 73. Primary Lane Alignment Pattern Byte MSB [reg56]......................................................................................143
Table A. 74. Secondary Lane Alignment Pattern Byte 0 [reg57].......................................................................................143

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Table A. 75. Secondary Lane Alignment Pattern Byte 1 [reg58].......................................................................................143
Table A. 76. Secondary Lane Alignment Pattern Byte 2 [reg59].......................................................................................143
Table A. 77. Secondary Lane Alignment Pattern Byte 3 [reg5a].......................................................................................143
Table A. 78. Secondary Lane Alignment Pattern Byte MSB [reg5b] .................................................................................143
Table A. 79. Lane Alignment Pattern Mask Code [reg5c] .................................................................................................143
Table A. 80. Clock Frequency Compensation Control [reg60]..........................................................................................144
Table A. 81. SKIP Pattern Insertion/Deletion Control [reg61] ..........................................................................................144
Table A. 82. Elastic FIFO High Water Line [reg62] ............................................................................................................144
Table A. 83. Elastic FIFO Low Water Line [reg63] .............................................................................................................145
Table A. 84. Primary SKIP Pattern Byte 0 [reg64] .............................................................................................................145
Table A. 85. Primary SKIP Pattern Byte 1 [reg65] .............................................................................................................145
Table A. 86. Primary SKIP Pattern Byte 2 [reg66] .............................................................................................................145
Table A. 87. Primary SKIP Pattern Byte 3 [reg67] .............................................................................................................145
Table A. 88. Primary SKIP Pattern MSB [reg68]................................................................................................................145
Table A. 89. Secondary SKIP Pattern Byte 0 [reg69].........................................................................................................145
Table A. 90. Secondary SKIP Pattern Byte 1 [reg6a] .........................................................................................................145
Table A. 91. Secondary SKIP Pattern Byte 2 [reg6b].........................................................................................................145
Table A. 92. Secondary SKIP Pattern Byte 3 [reg6c] .........................................................................................................145
Table A. 93. Secondary SKIP Pattern MSB [reg6d]............................................................................................................146
Table A. 94. SKIP Pattern Mask Code [reg6e] ...................................................................................................................146
Table A. 95. 64B/66B PCS Tx Path Control [reg80] ...........................................................................................................146
Table A. 96. 64B/66B PCS Tx FIFO Almost Full Setting Control [reg81] ............................................................................146
Table A. 97. 64B/66B PCS Tx FIFO Almost Empty Setting Control [reg82] .......................................................................146
Table A. 98. 64B/66B PCS Rx Path Control [reg83]...........................................................................................................146
Table A. 99. 64B/66B PCS CTC High Water Line Control [reg84] ......................................................................................147
Table A. 100. 64B/66B PCS CTC Low Water Line Control [reg85].....................................................................................147
Table A. 101. 64B/66B PCS Block Align Shift [reg86] ........................................................................................................147
Table A. 102. 10GBASE-R BER Counter [reg90] ................................................................................................................147
Table A. 103. 10GBASE-R Block Error Counter [reg91].....................................................................................................148
Table A. 104. 10GBASE-R Test Pattern Seed A Byte 0 [reg92]..........................................................................................148
Table A. 105. 10GBASE-R Test Pattern Seed A Byte 1 [reg93]..........................................................................................148
Table A. 106. 10GBASE-R Test Pattern Seed A Byte 2 [reg94]..........................................................................................148
Table A. 107. 10GBASE-R Test Pattern Seed A Byte 3 [reg95]..........................................................................................148
Table A. 108. 10GBASE-R Test Pattern Seed A Byte 4 [reg96]..........................................................................................148
Table A. 109. 10GBASE-R Test Pattern Seed A Byte 5 [reg97]..........................................................................................148
Table A. 110. 10GBASE-R Test Pattern Seed A Byte 6 [reg98]..........................................................................................148
Table A. 111. 10GBASE-R Test Pattern Seed A Byte 7 [reg99]..........................................................................................149
Table A. 112. 10GBASE-R Test Pattern Seed B Byte 0 [reg9a] ..........................................................................................149
Table A. 113. 10GBASE-R Test Pattern Seed B Byte 1 [reg9b]..........................................................................................149
Table A. 114. 10GBASE-R Test Pattern Seed B Byte 2 [reg9c] ..........................................................................................149
Table A. 115. 10GBASE-R Test Pattern Seed B Byte 3 [reg9d]..........................................................................................149
Table A. 116. 10GBASE-R Test Pattern Seed B Byte 4 [reg9e] ..........................................................................................149
Table A. 117. 10GBASE-R Test Pattern Seed B Byte 5 [reg9f]...........................................................................................149
Table A. 118. 10GBASE-R Test Pattern Seed B Byte 6 [rega0]..........................................................................................149
Table A. 119. 10GBASE-R Test Pattern Seed B Byte 7 [rega1] ..........................................................................................149
Table A. 120. 10GBASE-R Test Pattern Control 0 [rega2] .................................................................................................150
Table A. 121. 10GBASE-R Test Pattern Control 1 [rega3] .................................................................................................150
Table A. 122. 10GBASE-R Test Pattern Error Counter Byte 0 [rega4]...............................................................................151
Table A. 123. 10GBASE-R Test Pattern Error Counter Byte 1 [rega5]...............................................................................151
Table A. 124. PMA Control [regc6] ...................................................................................................................................151
Table A. 125. PMA Control [regc7] ...................................................................................................................................151
Table A. 126. Loopback Mode Control [rege0].................................................................................................................152
Table A. 127. MPCS BIST Control 0 [rege1].......................................................................................................................152
Table A. 128. MPCS BIST Control 1 [rege2].......................................................................................................................153

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Table A. 129. User Defined BIST Constant 1 Byte_0 [rege3] ............................................................................................153
Table A. 130. User Defined BIST Constant 1 Byte_1 [rege4] ............................................................................................153
Table A. 131. User Defined BIST Constant 1 MSByte [rege5] ...........................................................................................153
Table A. 132. User Defined BIST Constant 2 Byte_0 [rege6] ............................................................................................154
Table A. 133. User Defined BIST Constant 2 Byte_1 [rege7] ............................................................................................154
Table A. 134. User Defined BIST Constant 2 MSB [rege8] ................................................................................................154
Table A. 135. BIST Status 0 [rege9]...................................................................................................................................154
Table A. 136. BIST Status 1 [regea] ...................................................................................................................................154
Table B. 1. 8B/10B Data Symbol Codes.............................................................................................................................155
Table B. 2. 8B/10B Control Symbol Codes ........................................................................................................................160
Table C. 1. Recommended Parameters for SerDes PLL.....................................................................................................161
Table C. 2. Serial Protocol Applications ............................................................................................................................166

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Glossary
A list of vocabulary used in this document.
Vocabulary
Definition
AC
Alternating Current
AN
Auto Negotiation
ASIC
Application Specific Integrated Circuit
BER
Bit Error Ratio
BIST
Built In Self-Test
CDR
Clock and Data Recovery
CE
Consumer Electronic
CIS
CMOS Image Sensor
CoaXPress
An interface to connect devices (typical cameras) to host (typical frame grabbers)
COMMA
The seven bit comma string is defined as either 7’b0011111 (comma+) or 7’b1100000 (comma-)
CTC
Clock Tolerance Compensation
CTLE
Continuous Time Linear Equalizer
DC
Direct Current
DDR
Double Data Rate
DFE
Decision Feedback Equalization
DFF
D-Flip Flop
DP
DisplayPort
DSP
Digital Signal Processor
eDP
Embedded DisplayPort
EI1
Electrical Idle 1
EI2
Electrical Idle 2
EI4
Electrical Idle 4
EIEOS
Electrical Idle Exit Ordered Set
EMI
Electro-Magnetic Interference
EPCS
External PCS
ESR
Equivalent Series Resistance
FEC
Forward Error Correction
FFE
Feed Forward Equalizer
FIFO
First Input First Output
FIR
Finite Impulse Response
FOM
Figure of Merit
FPGA
Field-Programmable Gate Array
FS
Full Swing
FSM
Finite State Machine
HBR
High Bit Rate
HBR2
High Bit Rate 2
HBR3
High Bit Rate 3
Gen1/Gen2/Gen3
Generation 1/Generation 2/Generation 3
GMII
Gigabit Media Independent Interface
GPLL
General Purpose PLL
GUI
Graphic User Interface
HCSL
High Speed Current Steering Logic, or Host Controller Signal Level
IP
Intellectual Property
IPG
Inter-Packet Gap
ISI
Inter-Symbol Interference

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Vocabulary
Definition
I/F
Interface
JIIA
Japan Industrial Imaging Association
JTAG
Joint Test Action Group
L2
A low power state inside PCIe LTSSM
LF
Low Frequency
LMMI
Lattice Memory Mapped Interface
LOS
Loss of Signal
LSByte/LSB
Last Significant Byte
LTSSM
Link Training and Status State Machine
LVDS
Low-Voltage Differential Signaling
MAC
Media Access Control
MPCS
Multi-protocol Physical Coding Sublayer
MSByte/MSB
Most Significant Byte
NL
Number of Lane
OOB
Out Of Band
PC
Personal Computer
PCI
Peripheral Component Interconnect
PCIe / PCI-E
PCI Express
PCS
Physical Coding Sublayer
PFD
Phase Frequency Detector
PMD
Physical Medium Dependent
PIPE
PHY Interface for PCI Express
PISO
Parallel In Serial Out
PLL
Phase Locked Loop
PMA
Physical Media Attachment
PPM
Parts Per Million
PRBS
Pseudo Random Bit Sequence
PRD
Pseudo Random Data
QSGMII
Quad Serial Gigabit Media Independent Interface
RBR
Reduced Bit Rate
RC
Root Complex
RS
Reconciliation Sublayer
Rx
Receiver
RxDP
Receiver Data Positive pin
RxDN
Receiver Data Negative pin
RXAUI
Reduced 10 Gigabit Attachment Unit Interface
SATA
Serial Advanced Technology Attachment
SDR
Single Data Rate
SerDes
Serializer/Deserializer
SIPO
Serial In Parallel Out
SGMII
Serial Gigabit Media Independent Interface
SKP
SKIP order sets defined by PCI Express
SLVS-EC
Scalable Low Voltage Signaling with Embedded Clock
SRIO
Serial Rapid IO
SSC
Spread Spectrum Clocking
SATA
Serial ATA
Sync
Synchronous
Tx
Transmitter

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
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Vocabulary
Definition
TxDP
Transmitter Data Positive pin
TxDN
Transmitter Data Negative pin
UI
Unit Interval
USB
Universal Serial Bus
USB3
USB SuperSpeed
VC0_RX
Virtual Channel 0 Receiver
VC0_TX
Virtual Channel 0 Transmitter
VESA
Video Electronics Standards Association
WAKE#
A wake up signal defined by PCIe
WIS
WAN Interface Sublayer
XAUI
10 Gigabit Ethernet Attachment Unit Interface
XGMII
10 Gigabit Media Independent Interface

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
14 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
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Introduction
The Lattice Semiconductor CertusPro-NX device family has up to 8 channels embedded SerDes with associated Physical
Coding Sublayer (PCS) logic, which supports PCI Express Gen1/2/3 hard IP Core, DisplayPort, 10GBASE-R, 1000BASE-X,
SGMII, QSGMII, XAUI, SLVS-EC, and CoaXPress protocols. There are two kinds of Physical Coding Sublayer logic inside
the CertusPro-NX device: one is for PCI Express only, the other is Multi-Protocol Physical Coding Sublayer (MPCS) for
protocols other than PCI Express.
Each channel of MPCS contains dedicated transmit and receive logic for high-speed, full-duplex serial data transfer at
data rates up to 10.3125 Gb/s. The MPCS logic in each channel can be configured to support corresponding protocols.
In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to provide you the
flexibility of designing your own high-speed data interface. SerDes channel input can be independently AC-coupled or
DC-coupled to meet the requirements from different protocols.

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 15
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Features
Single Channel MPCS Functionalities
From 625 Mb/s up to 10.3125 Gb/s per channel
Word alignment and link synchronization FSM
Supports DisplayPort, SLVS-EC, CoaXPress, and Ethernet 1000BASE-X/SGMII/XAUI/QSGMII protocols
Supports popular 8B/10B PCS-based protocols
Supports user-specified generic 8B/10B mode
Supports Ethernet 64B/66B coding and decoding
Supports per channel configuration
PMA-only mode allows direct 8-bit or 10-bit interface to FPGA logic
Multiple Channel Alignment
Up to eight channels of the same protocol
Minimized Transmitter (Tx) lane-to-lane skew
Receiver (Rx) multiple lane de-skew (up to 100UI)
Multiple Protocol Clock Tolerance Compensation (CTC) logic
Compensates for frequency difference between reference clock and received data rate
Allows user-defined SKIP pattern of 1, 2, or 4 bytes in length
Integrated Loopback Modes for System Debugging
Two loopback modes are provided by SerDes (PMA)
Two loopback modes are provided by MPCS 8B/10B mode
Three loopback modes are provided by MPCS 64B/66B mode
Rx Eye Monitor
Integrated 2D eye-scan for each Rx channel
First on-chip SerDes debug tool in Lattice general purpose FPGAs
SerDes Power Supply Monitor
Integrated real-time monitor for SerDes power supply
Easy-to-Use Design Interface in Lattice RadiantTM Design Tool
Easy-to-use Graphic User Interface (GUI)
Some easy-to-use soft IP cores and example projects available

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
16 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
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Using This Technical Note
This technical note provides a thorough description of the complete functionality of the embedded SerDes and
associated PCS logic, including the description of:
Architecture of the CertusPro-NX SerDes/PCS module and interface
SerDes/PCS function
Clock and reset
SerDes/PCS debug capabilities
SerDes/PCS register access
SerDes/PCS usage for different protocols
SerDes/PCS block latency
SerDes/PCS generation in Lattice Radiant software
The status and control registers associated with the SerDes and PCS logic, which can be accessed via the Lattice
Memory Mapped Interface (LMMI)
The electrical and timing characteristics of the embedded SerDes and the package pinout information are provided in
CertusPro-NX Family Data Sheet (FPGA-DS-02086).
The Lattice Radiant design tools support all modes of PCS. Most modes are dedicated to applications for specific
industry standard data protocols listed in the Features section. Other modes are more general purpose in nature in
order to let you customize your own application settings. Radiant design tools allow you to define the mode for each
quad in your design. This technical note describes operation of the SerDes and PCS for all modes supported by Lattice
Radiant software.

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 17
All rights reserved. CONFIDENTIAL
Standards Supported
The supported standards are listed in Table 4.1.
Table 4.1. Standards Supported by the SerDes/PCS
Standard
Data Rate (Mb/s)
System Reference
Clock (MHz)
FPGA Clock (MHz)
Number of Link
Width
Encoding Style
PCI Express Gen1
2500
100
125
×1, ×2, ×4
8b10b
PCI Express Gen2
5000
100
125
×1, ×2, ×4
8b10b
PCI Express Gen3
8000
100
250
×1, ×2, ×4
128b130b
Ethernet 1000BASE-X
1250
125
125
x1
8b10b
Ethernet SGMII
1250
125
125
×1
8b10b
Ethernet XAUI
3125
156.25
156.25
×4
8b10b
Ethernet QSGMII
5000
125
125
×1
8b10b
Ethernet 10GBASE-R
10312.5
161.1328125
161.1328125
×1
64b66b
SLVS-EC Grade1
~1250
—
~125
×1, ×2, ×4, ×6, ×8
8b10b
SLVS-EC Grade2
~2500
—
~125
×1, ×2, ×4, ×6, ×8
8b10b
SLVS-EC Grade3
~5000
—
~125
×1, ×2, ×4, ×6, ×8
8b10b
CoaXPress CXP-1
1250
125
125
×1~×8
8b10b
CoaXPress CXP-2
2500
125
125
×1~×8
8b10b
CoaXPress CXP-3
3125
156.25
156.25
×1~×8
8b10b
CoaXPress CXP-5
5000
125
125
×1~×8
8b10b
CoaXPress CXP-6
6250
156.25
156.25
×1~×8
8b10b
DP/eDP RBR
1620
108
162
×1, ×2, ×4
8b10b
DP/eDP HBR
2700
135
135
×1, ×2, ×4
8b10b
DP/eDP HBR2
5400
135
135
×1, ×2, ×4
8b10b
DP/eDP HBR3
8100
135
202.5
×1, ×2, ×4
8b10b
10-bit SerDes
625 –8100
—
—
×1~×8
N/A
8-bit SerDes
625 –8100
—
—
×1~×8
N/A
Generic 8b10b
625 –8100
—
—
×1~×8
8b10b

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
18 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
Architecture Overview
Device Architecture
The SerDes/PCS block is arranged in quads containing logic for four full-duplex data channels. Figure 5.1 shows the
arrangement of SerDes/PCS Quads on the CertusPro-NX 100k device.
PLL SERDES/PCS X4 OSC Configuration
& Security
I/O Bank (Bank 0)
Large
RAM
ALU
ADC
(2Ch)
Large
RAM
I/O Bank
(Bank 1)
I/O Bank
(Bank 2)
I/O Bank (Bank 5) I/O Bank (Bank 4) I/O Bank (Bank 3) PLL
I/O Bank
(Bank 7)
I/O Bank
(Bank 6)
PLL
CDR
(2Ch)
PLL
Large
RAM
Large
RAM
SERDES/PCS X4 Large
RAM
Large
RAM
Large
RAM
PCIe LL(X4+X1)
Figure 5.1. CertusPro-NX 100k Device Block Diagram

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
FPGA-TN-02245-0.81 © 2020-2021 Lattice Semiconductor 19
All rights reserved. CONFIDENTIAL
Table 5.1 shows the maximum number of available SerDes/PCS channels for each CertusPro-NX device. Refer to
CertusPro-NX Family Data Sheet (FPGA-DS-02086) for more details on the actual number of channels varying from
package to package.
Table 5.1. Maximum Number of SerDes/PCS Channels per CertusPro-NX Device
Package
CertusPro-NX 50k
CertusPro-NX 100k
SerDes/PCS Quads
1
2
SerDes/PCS Channels
4
8
SerDes/PCS Architecture
Each CertusPro-NX SerDes/PCS quad includes four PMA channels, one PCI Express PCS Quad, one MPCS Quad, and
related glue logic. Each PMA channel integrates CDR for Receiver and PLL for Transmitter. The PCI Express PCS is
designed only for PCI Express, while the Multi-Protocol PCS (MPCS) is designed for other protocols.
CertusPro-NX device also integrates one PCI Express Link Layer Quad, which contains one PCIe ×1 block and one PCIe
×4 block. The PCIe ×4 PCI Express Link Layer block can be configured as ×1, ×2 or ×4 mode. The PCI Express Link Layer
block, PCI Express PCS channels, and PMA channels constitute the complete PCI Express Hard IP block. Table 5.2 shows
the maximum number of available PCI Express blocks information for the CertusPro-NX device. Refer to CertusPro-NX
Family Data Sheet (FPGA-DS-02086) for more details on the actual number of channels varying from package to
package.
Table 5.2. Maximum Number of PCI Express Blocks per CertusPro-NX Device
Package
CertusPro-NX 50k
CertusPro-NX 100k
PCI Express Hard IP
1
1
PCI Express PCS Quad
1
2
PCI Express Link Layer ×1 Block
1
1
PCI Express Link Layer ×4 Block
1
1
Figure 5.2 shows CertusPro-NX device SerDes/PCS quad architecture. For protocols other than PCI Express, the PCI
Express PCS can be bypassed. You can implement MPCS and PMA for Ethernet SGMII, XAUI, QSGMII, XGMII, SLVS-EC,
CoaXpress, DP/eDP or Generic 8B/10B applications. The MPCS can also be bypassed so that the SerDes/PCS module
works in PMA-only mode.

CertusPro-NX SerDes/PCS Usage Guide
Preliminary Technical Note
20 © 2020-2021 Lattice Semiconductor FPGA-TN-02245-0.81
All rights reserved. CONFIDENTIAL
PCI Express Link Layer (x1 + x4)
MPCS x4
PCI Express PCS
PMA (SERDES)
Channel 0
Rx CDR
Tx PLL
PMA (SERDES)
Channel 1
Rx CDR
Tx PLL
PMA (SERDES)
Channel 2
Rx CDR
Tx PLL
PMA (SERDES)
Channel 3
Rx CDR
Tx PLL
LMMI TLP UCFG LMMI MPCS EPCS
FPGA Core
PMA Controller
Figure 5.2. CertusPro-NX SerDes/PCS Quad Architecture
Table 5.3 shows the specific block usage for the corresponding SerDes/PCS mode.
Table 5.3. Block Usage for the Corresponding SerDes/PCS Mode
SerDes/PCS Mode
PCI Express
MPCS
PMA Only
PIPE
PMA
√
√
√
√
PMA Controller
√
√
√
√
PCI Express PCS
√
—
—
√
PCI Express Link Layer Quad
√
—
—
—
MPCS
—
√
—
—
PCI Express Architecture
The CertusPro-NX PCI Express Link Layer block is a hard IP, which supports PCI Express Gen1, Gen2, and Gen3, and is
compatible with PCI-SIG PCI Express Base Spec version 3.1a. The PCI Express Link Layer Block implements PHY Layer
adaption, Data Link Layer, and Transaction Layer. The PCI Express Link Layer block together with PCI Express PCS, PMA
Controller and PMA, constitute the complete PCI Express Hard IP block.
The PCI Express Hard IP supports both Endpoint and Root Complex modes. It supports up to four physical functions.
Each of the four functions has independent PCI Express configurations space. It also supports ECC and parity data path
protection. You can configure this IP as PIPE mode, which is compliant to industry PIPE standard version 4.4, by
bypassing Link Layer block. The LMMI interface is provided in the top wrapper that is to be used in user-controlled IP
core configuration.
The PCI Express Link Layer Quad for all CertusPro-NX devices has four PIPE interfaces that can be used in different
number of links. This can provide the maximum flexibility, depending on the bandwidth of the application
requirements.
Figure 5.3 shows the architecture of the CertusPro-NX PCI Express Hard IP. There are four physical functions in the Link
Layer ×4 block. There are four physical functions in the Link Layer ×1 block. Total there are eight physical functions in
one Link Layer Quad. PCI Express Configuration Space access and Error Reporting are done through the dedicated
interface (PCI Express Configuration Register Interface, UCFG). The core Configuration and Status Registers can be
accessed using the corresponding LMMI interface per Link Layer block. PCI Express Link Layer block interface to PCI