Lattice Semiconductor iCE40 UltraLite Parts list manual

iCE40 Oscillator Usage Guide
Technical Note
FPGA-TN-02008-1.7
December 2020

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-TN-02008-1.7
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is entirely
with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been
subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02008-1.7 3
Contents
Acronyms in This Document.................................................................................................................................................4
1. Introduction..................................................................................................................................................................5
1.1. Key Features........................................................................................................................................................5
2. On-Chip Oscillator Overview ........................................................................................................................................5
3. I/O Port Description......................................................................................................................................................6
4. Connectivity Guideline..................................................................................................................................................6
5. Power Management Options .......................................................................................................................................8
Appendix A: Design Entry .....................................................................................................................................................9
A.1. SB_LFOSC Usage in iCEcube2 Software.....................................................................................................................9
A.2. SB_HFOSC Usage in iCEcube2 Software ....................................................................................................................9
A.3. LSOSC Usage in Lattice Radiant Software..................................................................................................................9
A.4. HSOSC Usage in Lattice Radiant Software...............................................................................................................10
TechnicalSupport Assistance ..............................................................................................................................................11
Revision History..................................................................................................................................................................12
Figures
Figure 2.1. On-Chip Oscillator...............................................................................................................................................5
Figure 4.1. Oscillator Calibration Example............................................................................................................................6
Figure 4.2. Oscillator Used for Dynamic Clock Calibration that Can Be Used On Service LED..............................................7
Tables
Table 3.1. SB_HFOSC/HSOSC I/O ..........................................................................................................................................6
Table 3.2. SB_LFOSC/LSOSC I/O............................................................................................................................................6

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-TN-02008-1.7
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
FPGA
Field Programmable Gate Array
LED
Light Emitting Diode
FSM
Finite State Machine
PWM
Pulse-Width Modulation

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02008-1.7 5
1. Introduction
The iCE40™ family, specifically iCE40 Ultra™, iCE40 UltraLite™ and iCE40 UltraPlus™, features two on-chip oscillators.
An ultra-low power 10 kHz oscillator is provided for Always-On applications and background polling that allow higher
power processors to remain in power-down or sleep mode, conserving overall power consumption. A low power 48
MHz oscillator with output divider is provided for sensor management and pre-processing functions. These oscillators
are intended for general clocking of internal logic and state machines.
This document provides guidance to software engineers on integrating these two oscillator types using iCEcube2™or
Lattice Radiant™Software.
1.1. Key Features
The following oscillators are available to iCEcube2 users:
SB_LFOSC –Low Frequency Oscillator
SB_HFOSC –High Frequency Oscillator with output divider
The following oscillators are available to Lattice Radiant Software users:
LSOSC –Low Frequency Oscillator
HSOSC –High Frequency Oscillator with output divider
2. On-Chip Oscillator Overview
You can access the two modules: SB_LFOSC and SB_HSOSC with enabled inputs and which you can dynamically control
as shown in Figure 2.1.
SB_LFOSC runs at 10 kHz and SB_HFOSC runs at maximum 48 MHz with output divider by 1, 2, 4 or 8. SB_LFOSC and
SB_HFOSC provide internal clock sources to user designs. These clocks can directly route to the global clock network or
to local fabric.
SB_HFOSC/HSOSC CLKHF
CLKHFEN
CLKHFPU
SB_LFOSC/LSOSC CLKLF
CLKLFEN
CLKLFPU
Figure 2.1. On-Chip Oscillator

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-TN-02008-1.7
3. I/O Port Description
Table 3.1. SB_HFOSC/HSOSC I/O
Pin Name
Pin Direction
Description
CLKHFEN
I
Enable the clock output. Enable should be low for the 100 us power up period. This does
not stop the oscillator, but only disables the output. Active High.
CLKHF
O
Oscillator Clock Output.
CLKHFPU
I
Power up the oscillator. After power up, output will be stable after 100 us. Active High.
Table 3.2. SB_LFOSC/LSOSC I/O
Pin Name
Pin Direction
Description
CLKLFEN
I
Enable the clock output. Enable should be low for the 100 us power up period. This does
not stop the oscillator, but only disables the output. Active High.
CLKLF
O
Oscillator Clock Output.
CLKLFPU
I
Power up the oscillator. After power up, output is stable after 100 us. Active High.
4. Connectivity Guideline
Both the low and high frequency oscillators can be used as a clock source and their outputs are available for the user.
They should be connected to the global clock network or local fabric. By default, the outputs are routed to global clock
network. To route to local fabric, see the examples in the Appendix: Design Entry section.
Note that Oscillator cannot provide accurate frequency. For applications that require more accuracy, it is
recommended to use calibration circuit to support the oscillator used as clock source. Figure 4.1 shows an example of
the use of a reference clock that is only temporarily available for calibration.
AP
iCE40
Reference Clock
Internal 48 MHz
SB_HFOSC/SOSC Counter
FSM
Figure 4.1. Oscillator Calibration Example
The calibration circuit for Oscillator can be improved for the purpose of power saving as shown in Figure 4.2.
In this example, 10 kHz oscillator is always on. Calibrated divider provides timing for LED on-off. When LED is on,
SB_LFOSC/LSOSC Enable turns on 48 MHz oscillator (SB_HFOSC/HSOSC turns on in two cycles). PWM FSM provides
accurate PWM for LED. Power benefit is 48 MHz only when LED is on and minimum power when LED is off.

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02008-1.7 7
AP
iCE40
24 MHz
Reference
Internal 10 kHz
SB_LFOSC/LSOSC
FSM
Divider LED Control
Counter
Preload
10 Hz SB_HFOSC/HSOSC
Enable Internal
SB_HFOSC/HSOSC PWM
FSM
LED
PWM
OUT
16
SB_HFOSC Enable
LED PWM OUT
Figure 4.2. Oscillator Used for Dynamic Clock Calibration that Can Be Used On Service LED

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-TN-02008-1.7
5. Power Management Options
When disabled, both the low and high frequency oscillators are in standby mode by default and consume only DC
leakage. Always enable them after there is an activity detected and the products return to full power mode for data
analysis/processing.

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02008-1.7 9
Appendix A: Design Entry
The following examples illustrate oscillator primitive usage in Verilog.
A.1. SB_LFOSC Usage in iCEcube2 Software
Synthesis Attributes
/* synthesis ROUTE_THROUGH_FABRIC = <value> */
Value:
0: Use dedicated clock network. Default option.
1: Use fabric routes.
Verilog Instantiation
SB_LFOSC OSCInst1 (
.CLKLFEN(ENCLKLF),
.CLKLFPU(CLKLF_POWERUP),
.CLKLF(CLKLF)
) /* synthesis ROUTE_THROUGH_FABRIC= 1 */; //the value can be either 0 or 1
A.2. SB_HFOSC Usage in iCEcube2 Software
Synthesis Attributes
/* synthesis ROUTE_THROUGH_FABRIC = <value> */
Value:
0: Use dedicated clock network. Default option.
1: Use fabric routes.
Parameter Values
The SB_HFOSC primitive has the following parameter options:
Parameter CLKHF_DIV = "0b00" (default), "0b01", "0b10", "0b11" (Clock divider selection. 0b00 = 48 MHz, 0b01 = 24 MHz,
0b10 = 12 MHz, 0b11 = 6 MHz)
Verilog Instantiation
SB_HFOSC OSCInst0 (
.CLKHFEN(ENCLKHF),
.CLKHFPU(CLKHF_POWERUP),
.CLKHF(CLKHF)
) /* synthesis ROUTE_THROUGH_FABRIC= 1 */; //the value can be either 0 or 1
defparam OSCInst0.CLKHF_DIV = "0b00";
A.3. LSOSC Usage in Lattice Radiant Software
Verilog Instantiation
LSOSC OSCInst1 (
.CLKLFEN(ENCLKLF),
.CLKLFPU(CLKLF_POWERUP),
.CLKLF(CLKLF)
);

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-TN-02008-1.7
A.4. HSOSC Usage in Lattice Radiant Software
Parameter Values
The HSOSC primitive has the following parameter options:
Parameter CLKHF_DIV = "0b00" (default), "0b01", "0b10", "0b11" (Clock divider selection. 0b00 = 48 MHz, 0b01 = 24 MHz, 0b10 = 12
MHz, 0b11 = 6 MHz)
Verilog Instantiation
HSOSC
#(
.CLKHF_DIV ("0b00")
) OSCInst0 (
.CLKHFEN (ENCLKHF),
.CLKHFPU (CLKHF_POWERUP),
.CLKHF (CLKHF)
);

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02008-1.7 11
Technical Support Assistance
Submit a technical support case via www.latticesemi.com/techsupport.

iCE40 Oscillator Usage Guide
Technical Note
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-TN-02008-1.7
Revision History
Revision 1.7, December 2020
Section
Change Summary
Appendix A. Design Entry
Updated code in the A.1. SB_LFOSC Usage in iCEcube2 Software and the A.2. SB_HFOSC
Usage in iCEcube2 Software sections.
Revision 1.6, July 2020
Section
Change Summary
Acronyms in This Document
Added this section.
Appendix A. Design Entry
Updated Parameter Values and Verilog Instantiation in the SB_HFOSC Usage in iCEcube2
Software section.
Revision 1.5, March 2020
Section
Change Summary
All
Added primitives for Lattice Radiant Software.
Disclaimers
Added this section.
Revision 1.4, September 2017
Section
Change Summary
All
Changed document number from TN1296 to FPGA-TN-02008.
Updated document template.
Multiple
Fixed the port name of SB_LFOSC and SB_HFOSC modules.
Changed Oscillator input pin names:
CLKHF_EN => CLKHFEN
CLKHF_PU => CLKHFPU
CLKLF_EN => CLKLFEN
CLKLF_PU => CLKLFPU
Connectivity Guideline
Removed clock generation logic information from the Connectivity Guideline section.
Disclaimers
Added this section.
Revision 1.3, June 2016
Section
Change Summary
Introduction
Updated Introduction section. Added iCE40 UltraPlus.
Revision 1.2, April 2015
Section
Change Summary
Connectivity Guideline
Updated Connectivity Guideline section. Added example of clock generation logic.
Technical Support Assistance
Updated Technical Support Assistance section.
Revision 1.1, January 2015
Section
Change Summary
All
Added support for iCE40 UltraLite.
Revision 1.0, June 2014
Section
Change Summary
All
Initial release.

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