Lattice Semiconductor CrossLink-NX User manual

PCIe Colorbar Demo for Lattice Nexus-based
FPGAs
User Guide
FPGA-UG-02149-1.1
March 2022

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-UG-02149-1.1
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02149-1.1 3
Contents
Acronyms in This Document.................................................................................................................................................6
1. Introduction..................................................................................................................................................................7
1.1. Learning Objectives.............................................................................................................................................7
2. Hardware and Software Requirements........................................................................................................................8
2.1. Hardware Requirements.....................................................................................................................................8
2.2. Software Requirements ......................................................................................................................................8
3. Setting Up the Demo ....................................................................................................................................................9
3.1. Hardware Setup ..................................................................................................................................................9
3.1.1. Programming the FPGA................................................................................................................................10
3.1.2. Status LED.....................................................................................................................................................14
3.2. Software Setup..................................................................................................................................................16
3.2.1. Software Setup and Installation for Windows .............................................................................................16
3.2.2. Software Setup for Linux..............................................................................................................................30
4. Demo Design Overview ..............................................................................................................................................33
4.1. Theory of Operation..........................................................................................................................................33
4.2. Design Overview ...............................................................................................................................................34
4.2.1. User Interface Application............................................................................................................................34
4.2.2. Driver API......................................................................................................................................................34
4.2.3. Device Drivers...............................................................................................................................................34
4.2.4. Device Hardware (FPGA Design) ..................................................................................................................34
5. Application Overview .................................................................................................................................................36
5.1. Running the PCIe Colorbar Demo Application ..................................................................................................36
1.1 Option ...............................................................................................................................................................37
5.1.1. PCIe Info .......................................................................................................................................................37
5.1.2. Play...............................................................................................................................................................38
5.1.3. Stop ..............................................................................................................................................................38
5.1.4. Set Video Param...........................................................................................................................................38
5.1.5. Exit................................................................................................................................................................38
5.1.6. About............................................................................................................................................................38
6. Importing and Building the FPGA Demonstration......................................................................................................39
6.1. Hardware Directory Structure...........................................................................................................................39
6.2. Building Lattice Radiant Project ........................................................................................................................39
7. Troubleshooting .........................................................................................................................................................40
7.1. SPI Flash Update................................................................................................................................................40
7.2. Driver Installation and User Interface Launch for Windows.............................................................................41
7.2.1. Problem in Driver Installation ......................................................................................................................41
7.2.2. Problem with Launching User Interface.......................................................................................................41
7.3. Driver Installation User Interface Launch for Linux...........................................................................................42
7.3.1. Problem in Driver Loading............................................................................................................................42
7.3.2. Problem with User Interface Launching.......................................................................................................43
Technical Support Assistance .............................................................................................................................................44
Revision History..................................................................................................................................................................45

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-UG-02149-1.1
Figures
Figure 3.1. CrossLink-NX PCIe Bridge Board Connection......................................................................................................9
Figure 3.2. Certus-NX PCIe Versa Evaluation Board Connection ........................................................................................10
Figure 3.3. Creating a New Project from a Scan .................................................................................................................10
Figure 3.4. Lattice Radiant Programmer Window ..............................................................................................................11
Figure 3.5. CrossLink-NX FPGA Device Settings ..................................................................................................................11
Figure 3.6. Certus-NX FPGA Device Settings.......................................................................................................................11
Figure 3.7. Device Properties Window for CrossLink-NX SPI Flash Programming ..............................................................12
Figure 3.8. Device Properties Window for Certus-NX SPI Flash Programming...................................................................13
Figure 3.9. Programmer Menu Bar.....................................................................................................................................13
Figure 3.10. Programmer Output Window.........................................................................................................................13
Figure 3.11. Status LED .......................................................................................................................................................14
Figure 3.12. Certus-NX Programming Done LED.................................................................................................................15
Figure 3.13. Running Disable Integrity Checks Command..................................................................................................16
Figure 3.14. Running Test Sign On Command.....................................................................................................................16
Figure 3.15. Troubleshoot Option.......................................................................................................................................17
Figure 3.16. Advanced Options...........................................................................................................................................17
Figure 3.17. Select Startup Settings....................................................................................................................................18
Figure 3.18. Restarting Windows........................................................................................................................................18
Figure 3.19. Welcome Page ................................................................................................................................................19
Figure 3.20. Destination Folder Page..................................................................................................................................20
Figure 3.21. Summary Page ................................................................................................................................................20
Figure 3.22. Application Installed .......................................................................................................................................21
Figure 3.23. Device Configuration Prompt .........................................................................................................................21
Figure 3.24. Device Driver Installation Wizard ...................................................................................................................22
Figure 3.25. Windows Security in Driver Installation..........................................................................................................22
Figure 3.26. Device Driver Installation Completed .............................................................................................................23
Figure 3.27. Device Manager..............................................................................................................................................23
Figure 3.28. Showing Device Properties .............................................................................................................................24
Figure 3.29. Hardware IDs of CrossLink-NX Colorbar Demo Device ...................................................................................24
Figure 3.30. Hardware IDs of Certus-NX Colorbar Demo Device........................................................................................25
Figure 3.31. Update Driver Menu in Device Manager........................................................................................................26
Figure 3.32. Update Driver Options....................................................................................................................................26
Figure 3.33. Browse the Driver for Device..........................................................................................................................27
Figure 3.34. Windows Security in Device Manager ............................................................................................................27
Figure 3.35. CrossLink-NX Driver Installation Status Message ...........................................................................................28
Figure 3.36. Certus-NX Driver Installation Status Message ................................................................................................28
Figure 3.37. CrossLink-NX Colorbar Demo Device Name Displayed in Device Manager....................................................29
Figure 3.38. Certus-NX Colorbar Demo Device Name Displayed in Device Manager.........................................................29
Figure 4.1. Relationship between the Hardware and Software Components....................................................................33
Figure 4.2. PCIe Colorbar Demo SW Design........................................................................................................................34
Figure 4.3. Top Level Architecture of FPGA Design ............................................................................................................35
Figure 5.1. PCIe Colorbar Demo Device Info Tab................................................................................................................36
Figure 5.2. Drop-Down Menu .............................................................................................................................................37
Figure 5.3. PCIe Device Info................................................................................................................................................37
Figure 5.4. Video Frames ....................................................................................................................................................38
Figure 5.5. Set Video Param................................................................................................................................................38
Figure 7.1. TCK Frequency Setting ......................................................................................................................................40
Figure 7.2. Port Selection....................................................................................................................................................40
Figure 7.3. User Interface with No Device Driver ...............................................................................................................41
Figure 7.4. Error Message...................................................................................................................................................42
Figure 7.5. lspci -vnm for CrossLink-NX Output Image .......................................................................................................42
Figure 7.6. lspci -vnm for Certus-NX Output Image............................................................................................................42

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02149-1.1 5
Figure 7.7. Content List of Demonstration/Linux Directory. ..............................................................................................43
Figure 7.8. Content List of Software/Linux Directory .........................................................................................................43
Tables
Table 3.1. CrossLink-NX Status LED Description .................................................................................................................14

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-UG-02149-1.1
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
DMA
Direct Memory Access
BAR
Base Address Register
FDSOI
Fully Depleted Silicon on Insulator
FPGA
Field-Programmable Gate Array
LED
Light-emitting diode
MIPI
Mobile Industry Processor Interface
PCIe
PCI Express
PHY
Physical Layer
SPI
Serial Peripheral Interface
USB
Universal Serial Bus

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02149-1.1 7
1. Introduction
This guide describes how to set up and run the PCIe Colorbar Demo using devices built on the Lattice Nexus™platform,
specifically CrossLink™-NX and Certus™-NX.
For CrossLink-NX, the demo is targeted to the CrossLink-NX PCIe Bridge Board, which features the CrossLink-NX FPGA in
the 400-ball caBGA package (LIFCL-40-8BG400C). For Certus-NX, the demo is targeted towards the Certus-NX Versa
Evaluation Board, which features the Certus-NX FPGA in the 256-ball caBGA package (LFD2NX-40-8BG256C). Both
FPGAs are built on the Lattice Nexus FPGA platform using low power 28 nm FDSOI technology.
This guide familiarizes you with the process of setting up your PCI Express development environment. It is assumed
that you do not have any associated tools installed on your system.
The demo discussed in this document includes the PCI Express Colorbar Demo.
1.1. Learning Objectives
After completing the steps in this guide, you will be able to perform the following:
Set up and install all applicable development tools and PCI Express demos;
Establish communication between the FPGA and the system through the PCI Express link;
Run the PCI Express Colorbar Demo, which displays a series of moving colorbars by streaming the image data using
DMA transfers from the FPGA to the host system.
Modify and rebuild the PCI Express Colorbar Demo.
Become familiar with the software development tools and major design flow steps employed in this kit.
Use other existing documentation in conjunction with this guide.
This document assumes that you have already installed the Lattice Radiant™ design software. This document covers
some of the basic of function of Lattice Radiant software. If you would like to learn more about Lattice Radiant
software, refer to the Lattice Radiant software Help system.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-UG-02149-1.1
2. Hardware and Software Requirements
2.1. Hardware Requirements
To install the kit design and run the demo software, a computer with a PCI Express ×16, ×8, ×4, or ×1 slot is required.
The computer must also have a USB port and be able to run the Lattice Radiant Software. All other hardware and
drivers are included in the kit.
Mini-USB to USB-A cable for programming the bitstream
12 V Power Adapter
Evaluation Board
CrossLink-NX PCIe Bridge Board for CrossLink-NX
Certus-NX Versa Evaluation Board for Certus-NX
2.2. Software Requirements
The following software is required to obtain the expected results for the procedures described in this guide:
Lattice Radiant Software 2.2 or later (available at the Lattice website Design Software and IP page).
PCIe Colorbar Demo for Windows 10 or Linux
Windows 10 or Ubuntu 18.04.6
Bit file for the SPI Flash
LIFCL40_PCIeColorbarDemo.bit for CrossLink-NX
LFD2NX_PCIeColorbarDemo.bit for Certus-NX

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-UG-02149-1.1 9
3. Setting Up the Demo
3.1. Hardware Setup
This section covers the steps in programming the demo to the SPI memory of the CrossLink-NX PCIe Bridge Board.
Make sure the board is plugged into a PCIe slot or connected to the 12 V input supply.
For CrossLink-NX, if the board is plugged into the PCIe slot, external power is provided by the system, and SW2 should
be in the up position to receive power from the PCIe slot. If external 12 V power is provided, then SW2 should be in
the down position to receive power from the external 12 V connection. Connect the board to the PC running the
Lattice Radiant software with the Mini USB Type A cable as shown in Figure 3.1.
Mini
USB
Type A
Cable 12 V Input
Supply
Connector
SW2
Figure 3.1. CrossLink-NX PCIe Bridge Board Connection
For Certus-NX, there is no toggle switch to select the power source, and the board can be powered through the PCIe
slot or from an external 12 V input supply. If the board is powered from the PCIe slot, the external 12 V input supply
connector does not need to be connected. Connect the board to the PC running the Lattice Radiant software with the
Mini USB Type A Cable as shown in Error! Reference source not found..

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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10 FPGA-UG-02149-1.1
12 V Input
Supply
Connection
Mini USB
Type A
Cable
Figure 3.2. Certus-NX PCIe Versa Evaluation Board Connection
3.1.1. Programming the FPGA
To program the FPGA device:
1. Create a new project using the Lattice Radiant Programmer software. In the Getting Started dialog box, indicate
Project Name and Location as shown in Figure 3.3.
2. Select Create a new project from scan. Values are indicated in the Cable, Port, and TCK Divider Setting (0-30×)
fields.
3. Click OK.
Figure 3.3. Creating a New Project from a Scan

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-UG-02149-1.1 11
4. The main interface opens as shown in Figure 3.4.
Figure 3.4. Lattice Radiant Programmer Window
5. If the Programmer settings do not match the settings shown in Figure 3.5 for CrossLink-NX or in Figure 3.6 for
Certus-NX, select these settings manually from drop down menu.
Figure 3.5. CrossLink-NX FPGA Device Settings
Figure 3.6. Certus-NX FPGA Device Settings
To select programming settings:
1. Browse and select the Programming file Demonstration/Bitstream.
a. For CrossLink-NX, select LIFCL40_PCIeColorBarDemo.bit from CL-NX_BridgeBoard_PCIe_BMD\
Demonstration\Bitstream.
b. For Certus-NX, select LFD2NX_PCIeColorBarDemo.bit from CertusNX _PCIe_ColorbarDemo\
Demonstration\Bitstream.
2. Click OK.
3. Double-click under Operation to open the Device Properties dialog box.
4. For CrossLink-NX, select the settings as shown in Figure 3.7.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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12 FPGA-UG-02149-1.1
Figure 3.7. Device Properties Window for CrossLink-NX SPI Flash Programming
5. For Certus-NX, select the settings as shown in Figure 3.8.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-UG-02149-1.1 13
Figure 3.8. Device Properties Window for Certus-NX SPI Flash Programming
6. Click the Programming button from the menu bar shown in Figure 3.9 to start programming.
Figure 3.9. Programmer Menu Bar
When the FPGA programming is successful, the output console shows an Operation Successful message as shown in
Figure 3.10.
Figure 3.10. Programmer Output Window
If the programming operation is not successful, refer to the troubleshooting section of this document.
After programming, power cycle the board and check the status LEDs on the board. For CrossLink-NX, refer to Figure
3.11 and Table 3.1. For Certus NX, refer to Figure 3.12.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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14 FPGA-UG-02149-1.1
3.1.2. Status LED
The three status LEDs are shown in Figure 3.11.
Figure 3.11. Status LED
The description of each status LED is provided in Table 3.1.
Table 3.1. CrossLink-NX Status LED Description
Sl. No
Name
Description
1
125 MHz Clock present
Green –Blinking when clock present (125 MHz Clock)
2
PCIe Link Up
Green –PCIe link up is successful
Red –PCIe link up is not successful
3
DONE
Green –Configuration is successful
Red –Board is not programmed
For Certus-NX, the programming done LED lights up in green if configuration is successful. The LED is located at D29 on
the board, as indicated in Figure 3.12.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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FPGA-UG-02149-1.1 15
Figure 3.12. Certus-NX Programming Done LED

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
User Guide
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16 FPGA-UG-02149-1.1
3.2. Software Setup
This section provides the procedure for installing software onto the host machine.
3.2.1. Software Setup and Installation for Windows
Before installing the driver, driver signature enforcement should be disabled.
3.2.1.1. Disabling Driver Signature Enforcement Permanently
To permanently disable driver signature enforcement:
1. Start the Command Prompt as administrator.
2. Enter the following lines and press Enter.
bcdedit.exe -set loadoptions DISABLE_INTEGRITY_CHECKS
Figure 3.13. Running Disable Integrity Checks Command
bcdedit.exe -set TESTSIGNING ON
Figure 3.14. Running Test Sign On Command
3. Close the Command Prompt and restart your PC.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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FPGA-UG-02149-1.1 17
3.2.1.2. Disabling Driver Signature Enforcement Temporarily
To disable the driver signature enforcement temporarily on Windows 10:
Note: if Driver Signature Enforcement is already disabled, skip this section and proceed to the Driver Installation
section.
1. Press the Windows key and click the power button.
2. Press and hold the Shift key and click Restart.
3. When the Choose an option screen appears as shown in Figure 3.15, release the Shift key.
4. Click Troubleshoot.
Figure 3.15. Troubleshoot Option
5. Select Advanced options and press Enter.
Figure 3.16. Advanced Options
6. Select Startup Settings and press Enter.

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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18 FPGA-UG-02149-1.1
Figure 3.17. Select Startup Settings
7. Press Enter to restart.
Figure 3.18. Restarting Windows
8. After restarting, select Option 7 to disable driver signature verification.
3.2.1.3. Driver Installation
There are two procedures to install the device driver:
Install through user interface installer
Install manually

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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FPGA-UG-02149-1.1 19
Installing the Colorbar Demo Device Driver through the User Interface Installer
The Colorbar Demo device driver is installed during the installation of the user interface as described in the following
section.
The Installer provides a standard packaging format for applications and a standard method for customizing the
applications. The installer helps to install the CrossLink-NX PCIe Bridge Board Colorbar Demo application in your
system.
The Framework supported version is Windows 10, WDF 1.25 or earlier.
To install the Colorbar Demo device driver through user interface:
1. In the Demonstration\Windows10\Application folder, double click setup.exe.
2. The welcome page appears. Click Next.
.
Figure 3.19. Welcome Page

PCIe Colorbar Demo for Lattice Nexus-based FPGAs
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20 FPGA-UG-02149-1.1
3. Provide the location where you want to install the application. Click Next.
Figure 3.20. Destination Folder Page
4. The installation summary page is shown. Click Install.
Note: Administrative access is required to run this command.
Figure 3.21. Summary Page