HP 3000 III Series User manual

HP 3000SERIE5;:11I
COMPUJ"ER SYSTEM
';',.,: .. , .•.• ,. 'r ", ;
REFERENCE/T~AIN1N,G MANUAL
Manual P~rt,No.~30000-90143
Printed in U.S.A. 6179
HEWLETT·PACKARD COMPANY
5303 STEVENS CREEK BLVD., SANTA CLARA, CALIFORNIA, 95060

NOTICE
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATER-
IAL, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS
FOR APARTICULAR PURPOSE. Hewlett-Packard shall not be liable for errors
contained herein or for incidental or consequential damages in connection with the furnishing, perfor-
mance or use of this material.
This document contains proprietary information which is protected by copyright. All rights are reserved.
No
part of this document may be photocopied or reproduced without the prior written consent of
Hewlett-Packard Company.
Copyright©1979 by HEWLETT-PACKARD COMPANY
ii

LIST OF EFFECTIVE PAGES I
The List of Effective Pages gives the date of the current edition and of any pages changed in updates to that edition. Within
the manual, any page changed since the last edition
is indicated by printing the date the changes were made on the bottom
of the page. Changes are marked with avertical bar in the margin. If an update is incorporated when an edition is reprinted,
th.ese bars are removed but the dates remain. No information is incorporated into areprinting unless it appears as a
prior update.
All pages in this manual are original issne.
iii

I PRINTING HISTORY
New editions are complete revisions of the manual. Update packages, which are issued between editions, contain additional
and replacement pages to be merged into the manual by the customer. The date on the title page and back cover
of the
manual changes only when anew edition
is pUblished. When an edition is reprinted, all the prior updates to the edition
are incorporated.
No information is incorporated into areprinting unless it appears as aprior update. The edition does
not change.
First Edition Jun 1979
iv

PREFACE I
This manual contains hardware-oriented reference information for
the HP 3000 Series III Computer Systems. Specifically, this man-
ual contains reference reading material for all persons that are
to attend Hewlett-Packard's 3000 Series III Computer System Hard-
ware Training Courses. Since the information contained in this
manual is approximately the same as that presented during class-
room lectures, this manual should be used for classroom refer-
ence, note taking purposes, and post school reference.
The HP 3000 Series III Computer Systems are divided into two pro-
duct lines; the HP 3242lA Series III and the HP 32435A Series
III. Unless otherwise stated, the content of this manual applies
equally to both product lines.
v

CONTENTS
SECTION I
Paragraph
INTRODUCTION
Page
SYSTEM FEATURES •••••••••••••••
Stack Architecture ••••••••
Microprogrammed Operations
Data Base Management Facilities
Five Progrannning Languages
Virtual Memory .
Fault Control Memory
Concurrent I/O and CPU Operations
Reentrant Code and Private Data
Opera ting System
HARDWARE FEATURES
SOFTWARE FEATURES
SYSTEM CONFIGURATIONS
...
1-1
1-1
1-2
1-2
1-2
1-2
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1-2
1-3
1-3
1-3
1-4
1-4
SECTION II
Paragraph
SYSTEM/CPU OVERVIEW
Page
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HARDWARE ORGANIZATION
Bus System
CTL BUS
lOP BUS
SELECTOR CHANNEL BUS
PORT CON'rROLLER BUS
MULTIPLEXER
CHANNEL BUS
POWER BUS ••.•••••••••••
Functional Hardware Elements
CENTRAL PROCESSOR MODULE
MAIN MEMORy .....•.......
MULTIPLEXER CHANNEL ••••••
PORT CON'rROLLER/SELECTOR CHANNEL
DEVICE CONTROLLERS
CTL
Bus Pr ior i ty
OPERATING ENVIRONMENT
Virtual Memory
Variable-Length Segmentation
Processes
Data Stacks
CPU Registers
CODE SEGMENT REGISTERS
DATA SEGl-1ENT REG! STERS
Basic Table Structures
CODE SEGMENT TABLE AND CODE SEGMEN'I'
vi
EXTENSION
2-1
2-1
2-1
2-2
2-2
2-3
2-3
2-3
2-3
2-3
2-4
2-5
2-6
2-6
2-7
2-7
2-7
2-8
2-9
2-9
2-11
2-12
2-13
2-15
2-15

CONTENTS (continued)
SECTION II (CaNT)
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Page
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2-16
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2-22
2-27
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DA'rA SEGHENT TABLE
Code Segment Linkage
Stack Operation ••••••
INSTRUCTION AND STAlJ:IUS WORD FORMATS •••••
Instruction Formats ••••••••••••
GENERAL FORttJA'Il
STACK OP •••••••
SHIFT
BRANCH
BIT 'I1EST
MOVE •••••
SPECIAL
IMMEDIATE
FIELD
REGISTER
CONTROL
PROGRAM CON'I'ROL
I/O AND INTERRUPT
LOOP CONTROL
MEMORY ADDRESS
Status Word Format
Condi tion Codes
OPERATING MODES
ADDRESSING CONVENTIONS
Memory Addressing
Indirect Addressing
CODE INDIRECT
DATA INDIRECT
Indexing ••••••••
CODE INDEXING
DATA INDEXING •••••
Byte Addres sing ••••••
DIRECT BYTE ADDRESSING
DIRECT, INDEXED BYTE ADDRESSING
INDIRECT BYTE ADDRESSING •••••••
INDIRECT, INDEXED BYTE ADDRESSING
Double-Word Indexing
Accessing DB- Area
WORD ADDRESSING
BYTE ADDRESSING ••••••
Bounds Checking •••••••••
PROGRAM TRANSFER LIMIT
PROGRAM REFERENCE LIMITS ••••
DATA REFERENCE LIMITS
STACK OVERFLOW LIMIT •••
STACK UNDERFLOW LIMIT
CPU OVERVIEW
Pipel ines
DATA PIP EL IN E
MICROCODE PIPELINE
CPU Component Descriptions
N I R ••••••••••••••••••••
vii

CONTENTS (continued)
SECTION II (CONT)
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2-50
2-51
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Page
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CIR
CMUX AND Cr.1UX CON'rROL
MAPPER AND MAPPER CONTROL
LUT ROM ••••••••••••••••••
VBUS MUX AND VBUS CONTROL
.RA.R ••••••••••••••••••
SAVE REGISTER
ROM ••••••••••
RORI AND ROR2 ••••••••••
Microcode Jumps
S-Bus Fie Id Decoder (S)
Store Field Decoder (STORE)
Function Field Decoder (FCN)
Skip Field Decoder (SKIP) ••••••••
Shift Field Decoder (SHIFT) •••••
Special Field Decoder (SP)
MCU Option Field Decoder (MeU)
R-Bus Field Decoder (R)
PROCESSOR REGISTERS
Renamer Logic •••••••
TO S Re gis te r s •••••••
Index Reg iste r (X) ••
Stack Limit Register (Z)
Program Limit Register (PL)
Scratch Pad 0 Register (SPO)
Scratch Pad 1 Register (SPl)
S ta c k Re g i s te r (S R) ,
Program Base Register (PB)
Data Limit Register (DL)
Stac kMemory Register (8M)
Data Base Register (DB)
Q Re gis te r (Q )
Scratch Pad 2 Register (SP2)
Scratch Pad 3 Register (SP3) •••••
Proces s Clock Regi ste r (PCLOC K)
Program Cbunter Register (P) •••••••••••••••••
Operand Register (OPND)
Status Register (STA)
Counte rReg iste r (CNTR)
OVERFLOW FLIP-FLOP (OVFL)
CARRY FLIP-FLOP (CRRY)
CONDITION CODE LOGIC (CCO AND CCl) ••••
PRE-ADDER •••••
R-BUS REGISTER ••••
S-BUS REGISTER ••••
ALU •••••••••••
SHIFTER ••••••••••••••••
DE CI MAL CORRE CTOR •••••••••••••••••••••
ADDRESS COMPUTER OUTPUT REGISTER (ACOR)
DATA COMPUTER OUTPUT REGISTER (DCOR) ••
INTERRUPT STATUS REGISTER 1(CPXl) ••••••••••••••
Paragraph
viii

CONTENTS (continued)
SECTION II (CONT)
Paragraph Page
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INTERRUPT STATUS REGIS'I'ER 2(CPX2) ••••••••••••••••••
CPU Servicing Information ••••••••••••
READ-ONLY MEMORY (ROM) PCA ••••••••
SKIP AND SPECIAL FIELD (SSF) PCA
S-BUS PCA ••••••••••••••••••••••••••
CURRENT INSTRUCTION REGISTER (CIR) PCA ••••••••••••••
2-61
2-61
2-61
2-62
2-63
2-64
SECTION III - SYSTEM VERIFICATION AND TROUBLESHOOTING
Paragraph Page
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3-1
3-1
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3-6
3-23
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3-26
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3-28
DIAGNOSTIC AND VERIFICATION PROGRAMS ••••.•••••••••••••••••
On-Line Verification Programs ••••••••••••••••••••••••
Stand-Alone Diagnostic Programs ••••••••••••••••••••••
Microdiagnostics •••••••••••••••••••••••••••••••••••••
SLEu'rH 3000
SYSTEM TROUBLESHOOTING AND REPAIR •••••••••••••••••••••••••
SYSTEM CONTROL Ph~EL
MAINTENANCE PANEL
Switch/Lamp Identification and Description ••••••••••
Op era t i ng Pre ca uti on s ••••••••••••••••••••••••••••••••••
Preparation For Use ••••••••••••••••••••••••••••••••
General Operating Method •••••••••••••••••••••••••••
Using Maintenance Panel and System Gbntrol Panel
Stack Register Loading •••••••••••••••••••••••••••••
CPU Register Displays ••••••••••••••••••••••••••••••••••
General-Use Di splay .
Ma intenance Panel Tes t •••••••••••••••••••••••••••••••••
LAMP TEST •••••••••••••••••••••••••••
SW ITCH TEST •••••••••••••••••••••••••
SECTION IV - MACHINE INSTRUCTIONS AND STACK OPERATIONS
Paragr aph Page
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4-1
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4-3
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4-10
4-11
4-12
4-13
4-13
4-14
4-15
4-17
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INSTRU CTION DECODING
TRAPS
AND INTERRUPTS
CONDITION
CODE
INSTIU CTION FORMATS
INSTRU CTION DEF INITIONS
Stack Op Instructions ••••••••••••••••••••••••••••••••••
Shift Instructions •••••••••••••••••••••••••••••••••••••
Branch Instr uctions ••••••••••••••••••••••••••••••••••••
lvbve Instructions ••••••••••••••••••••••••••••••••••••••
Privileged Memory Reference Instructions •••••••••••••••
Immed ia te In s tr uct ions •••••••••••••••••••••••••••••••••
Register Control Instructions ••••••••••••••••••••••••••
Program Control and Special Instructions •••••••••••••••
I/O Instructions •••••••••••••••••••••••••••••••••••••••
ix

CONTENTS (continued)
SECTION IV (CONT)
Paragraph
Memory Address Instructions
Instruction Commentary
STACK OPERATION EXAMPLES
Basic Ar ithme tic
Procedure Calls
Re cur s ion ••••••
MAIN PROGRAM CALL
TEST FOR ZERO
FIRST RECURSIVE CALL
SUCCESSIVE RECURSIONS
FIRST EXIT •••••••••••
FIRST RECURSIVE EXIT •••
SUCCESSIVE EXITS •••••
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SECTION V
SYSTEM MICROCODE
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Page
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GENERAL INFORMATION •••••••
Stack Element Locations
PUSH •••
POP
QUP
QDWN
Reading Microprogram Listings
MI CROINSTRU CTION DESCRIPTIONS
R-Bus Field
S-Bus Field
Function Fie ld
Shift Field
Store Field
Special Fie ld
MCU Option Field ••
Skip Field
MICRODIAGNOSTICS
Paragr aph
SECTION VI - MODULE CON'rROL UNIT/MAIN MEMORY OVERVIEW
Paragraph
Page
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MCU OPERATIONS
Fetch Next Instruction Operations
CPU ADDRESS TRANSMIT ••••••••
MEMORY RECEIVE AND TRANSMIT
CPU RECEIVE •••••••••••••
Fetch An Operand Operations
CPU ADDRESS TRANSMIT
MEMORY RECEIVE AND TRANSMIT
CPU RECE IVE •••••••••••••••••
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