Alpha Data ADM-XRC-7Z2 User manual

ADM-XRC-7Z2
User Manual
Document Revision: 1.2
24th Fe 2020

ADM-XRC-7Z2 User Manual
V1.2 - 24th Fe 2020
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ADM-XRC-7Z2 User Manual
V1.2 - 24th Fe 2020
able Of Contents
1 Overview ........................................................................................................................................... 1
1.1 Introd ction .................................................................................................................................... 1
1.2 Key Feat res ................................................................................................................................. 1
1.3 Order Code .................................................................................................................................... 1
1.4 References & Specifications .......................................................................................................... 2
2 PCB Information .............................................................................................................................. 3
2.1 Physical Specifications .................................................................................................................. 3
2.2 Motherboard / Carrier Req irements ............................................................................................. 3
2.3 Power Req irements ..................................................................................................................... 3
3 Installation ........................................................................................................................................ 4
3.1 Software Installation ...................................................................................................................... 4
3.2 Hardware Installation ..................................................................................................................... 4
3.2.1 Handling Instr ctions ................................................................................................................. 4
3.2.2 Installation in ADC-XMC-Breako t Carrier ................................................................................. 4
4 Functional Description .................................................................................................................... 5
4.1 Overview ........................................................................................................................................ 5
4.1.1 Switch Definitions ...................................................................................................................... 5
4.1.2 LED Definitions .......................................................................................................................... 7
4.2 Primary XMC Connector P5 .......................................................................................................... 8
4.2.1 XMC Platform Interface ............................................................................................................. 8
4.2.1.1 IPMI I2C ................................................................................................................................. 8
4.2.1.2 MBIST# .................................................................................................................................. 8
4.2.1.3 MVMRO ................................................................................................................................. 8
4.2.1.4 MRSTI# .................................................................................................................................. 8
4.2.1.5 MRSTO# ................................................................................................................................ 8
4.2.1.6 MPRESENT# ......................................................................................................................... 9
4.2.1.7 JTAG ...................................................................................................................................... 9
4.2.2 P5 HSSIO Links ......................................................................................................................... 9
4.3 Secondary XMC Connector P6 ...................................................................................................... 9
4.4 JTAG Interfaces ............................................................................................................................. 9
4.4.1 On-board Interface ..................................................................................................................... 9
4.4.2 XMC Interface ............................................................................................................................ 9
4.4.3 JTAG Voltages ........................................................................................................................... 9
4.5 Clocks ............................................................................................................................................ 9
4.5.1 PCIe Reference Clock (PCIEREFCLK) ................................................................................... 10
4.5.2 MGTCLK250M ......................................................................................................................... 10
4.5.3 PROGCLK ............................................................................................................................... 10
4.5.4 REFCLK200M .......................................................................................................................... 11
4.5.5 PS_CLK33M3 .......................................................................................................................... 11
4.5.6 USB_REFCLK24M .................................................................................................................. 11
4.5.7 ETH_CLK25M .......................................................................................................................... 11
4.5.8 ETH1_CLK125M ...................................................................................................................... 11
4.5.9 BU_REFCLK40M ..................................................................................................................... 11
4.5.10 BU_HOST_CLK ....................................................................................................................... 12
4.6 Resets .......................................................................................................................................... 12
4.7 Zynq PS Block ............................................................................................................................. 13
4.7.1 Boot Modes .............................................................................................................................. 13
4.7.2 PS Memory Interfaces ............................................................................................................. 13
4.7.2.1 Q ad SPI Flash Memory ..................................................................................................... 13
4.7.2.2 MicroSD Flash Memory ....................................................................................................... 13
4.7.2.3 PS DDR3 Memory ............................................................................................................... 13
4.7.3 Ethernet Interfaces .................................................................................................................. 13

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4.7.4 Serial COM Ports ..................................................................................................................... 15
4.7.5 USB Interfaces ......................................................................................................................... 15
4.8 Zynq PL Block .............................................................................................................................. 15
4.8.1 PL DDR3 Memory .................................................................................................................... 15
4.8.2 1553 B s Controller ................................................................................................................. 15
4.8.3 Rear GPIO Interface ................................................................................................................ 15
4.9 System Monitoring ....................................................................................................................... 15
4.9.1 A tomatic Temperat re Monitoring .......................................................................................... 16
4.9.2 System Monitor Stat s LEDs ................................................................................................... 16
Appendix A Rear Connector Pinouts ............................................................................................................... 19
A.1 Primary XMC Connector, P5 ........................................................................................................ 19
A.2 Secondary XMC Connector, P6 ................................................................................................... 20
List of ables
able 1 Build Options ..................................................................................................................................... 2
able 2 References ........................................................................................................................................ 2
able 3 Physical Specifications ...................................................................................................................... 3
able 4 Switch 1 Definitions ........................................................................................................................... 6
able 5 Switch 2 Definitions ........................................................................................................................... 6
able 6 Main LED Definitions ......................................................................................................................... 7
able 7 Ethernet LED Definitions ................................................................................................................... 8
able 8 PCIEREFCLK Connections ............................................................................................................. 10
able 9 MG CLK250M Connections ............................................................................................................ 10
able 10 PROGCLK Connections .................................................................................................................. 10
able 11 REFCLK200M Connections ............................................................................................................. 11
able 12 PS_CLK33M3 Connections ............................................................................................................. 11
able 13 E H1_CLK125M Connections ......................................................................................................... 11
able 14 BU_REFCLK40M Connections ........................................................................................................ 12
able 15 Boot Mode Selection ........................................................................................................................ 13
able 16 Ethernet Status LEDs ...................................................................................................................... 14
able 17 Voltage and emperature Monitors (in microcontroller) ................................................................... 16
able 18 emperature Limits .......................................................................................................................... 16
able 19 System Monitor Status LEDs ........................................................................................................... 17
able 20 XMC Connector P5 .......................................................................................................................... 19
able 21 XMC Connector P6 .......................................................................................................................... 20
List of Figures
Figure 1 ADM-XRC-7Z2 Block Diagram .......................................................................................................... 5
Figure 2 DIP Switch Locations ......................................................................................................................... 5
Figure 3 LED Locations ................................................................................................................................... 7
Figure 4 Ethernet Interfaces .......................................................................................................................... 13
Figure 5 Serial COM Ports ............................................................................................................................. 15
Figure 6 USB Interfaces ................................................................................................................................. 15

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1 Overview
1.1 Introduction
he ADM-XRC-7Z2 ("7Z2") is a high-performance Processor XMC for applications using Zynq-7000 SoCs from
Xilinx.
1.2 Key Features
Key Features
• Single-width XMC, compliant to VI A Standard 42.0 and 42.3
• Zynq Z-7045 EPP in FFG900 package
• Processing System (PS) Block consisting of:
. 1 bank of DDR3 SDRAM, 512MB
. Quad SPI Flash memory, 512Mb
. Removable Secure Digital (SD) Flash memory (Commercial Spec Option)
. Ethernet interface to rear-panel P6 connector
. Serial COM port connection to rear P6 connector
. wo USB ports to rear P6 connector
. One USB port to micro USB connector (Commercial Spec Option)
• Programmable Logic (PL) Block consisting of:
. 2 banks of DDR3 SDRAM, 256MB per bank
. Ethernet interface to rear-panel P6 connector
. Serial COM port connection to rear P6 connector
. Optional single-channel, dual-redundant MIL-S D-1553 Bus interface to P6 connector
. 32 GPIO to P6 connector, 3.3V compatible, configurable as single-ended or differential signals
. 20 GPIO to P6 connector, 3.3V, single-ended
• XMC Rear IO Interface P5:
. VI A 42.3 Pinout
. 8 HSSIO links to FPGA for PCI Express or user defined interface
. PCI Express reference clock input
• XMC Rear IO Interface P6:
. wo Gigabit Ethernet interfaces
. wo USB Ports
. wo Serial COM ports
. 52 GPIO (16 diff-pairs and 20 single-ended)
• Platform manager with system monitoring
1.3 Order Code
ADM-XRC-7Z2/z-y( )(c)(a)(t)
Page 1Overview
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Name Symbol Configurations
Kintex-7 Device z Z045 , Z100
Kintex-7 Speed y 1 , 2 , 3
MIL-S D-1553 c blank = no 1553 interface
/B = 1553 Bus Interface Fitted
Cooling c
blank = air cooled commercial
/ACE = Extended air cooled commercial
/AC1 = air cooled industrial
/CC1 = conduction cooled industrial
Conformal Coating a blank = No Coating /A = Acrylic (Humiseal 1B31)
/P = Polyurethane (Arathane 5750)
XMC Connector ype t blank = XMC (VI A 42) Connectors
/X2 = XMC2 (VI A 61) Connectors
Ta le 1 : Build Options
1.4 References & Specifications
ANSI/VI A 42.0 XMC Standard, December 2008, VI A, ISBN 1-885731-49-3
ANSI/VI A 42.3 XMC PCI Express Protocol Layer Standard, June 2006, VI A, ISBN 1-885731-43-4
ANSI/IEEE 1386-2001 IEEE Standard for a Common Mezzanine Card (CMC) Family, October 2001, IEEE,
ISBN 0-7381-2829-5
ANSI/IEEE 1386.1-2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC),
October 2001, IEEE, ISBN 0-7381-2831-7
ANSI/VI A 20-2001
(R2005) Cond ction Cooled PMC, February 2005, VI A, ISBN 1-885731-26-4
Ta le 2 : References
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2 PCB Information
2.1 Physical Specifications
Form Factor Single Width XMC
Length (conduction-cooled) 143.75 mm
Width 74.0 mm
Height 10.0 mm
Weight (conduction-cooled) BD
Ta le 3 : Physical Specifications
2.2 Mother oard / Carrier Requirements
he 7Z2 is a single width XMC.3 mezzanine with P5 and P6 connectors.
he 7Z2 is compatible with either 5V or 12V on the "VPWR" power rail.
he Primary XMC connector, P5, is compatible with the XMC.3 (VI A 42.3) specification for PCI Express
applications.
he Secondary XMC connector, P6 is not compatible with XMC.3 or XMC.10 (GPIO). It is important to check
compatibility prior to installation. If in doubt, please contact Alpha Data for assistance.
IMPORTANT
It is important to check compatibility with the carrier card prior to installation.
he Secondary XMC connector, P6 has +5V (power) -/+6V (serial port) levels. It is not compatible with XMC.3
or XMC.10 (GPIO). It must not be connected to the Alpha Data ADM-EMC-II or ADM-XMC-II carrier cards.
Please contact Alpha Data for carrier card compatibility.
2.3 Power Requirements
he power dissipation of the board is highly dependent on the arget FPGA application. A power estimator
spreadsheet is available on request from Alpha Data. his should be used in conjunction with Xilinx™ power
estimation tools to determine the exact current requirements for each power rail.
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3 Installation
3.1 Software Installation
Please refer to the Software Development Kit (SDK) installation CD. he SDK contains drivers, examples for
host control and FPGA design and comprehensive help on application interfacing.
3.2 Hardware Installation
3.2.1 Handling Instructions
he components on this board can be damaged by electrostatic discharge (ESD). o prevent damage, observe
ESD precautions:
- Always wear a wrist-strap when handling the card
- Hold the board by the edges
- Avoid touching any components
- Store in ESD safe bag.
3.2.2 Installation in ADC-XMC-Breakout Carrier
Note:
Note: his operation should only be performed while the ADC-XMC-Breakout carrier is not powered.
Ensure that the ADC-XMC-Breakout carrier is fitted with the AD-BREAKOUT-7Z2 wiring adaptor.
he 7Z2 should be secured to the ADC-XMC-Breakout carrier using M2.5 screws in the four holes provided.
Refer to the ADC-XMC-Breakout carrier documentation for switch configurations.
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4 Functional Description
4.1 Overview
Xilinx Zynq SoC
XC7Z045
XC7Z100
Processing System (PS)
DDR3 SDRAM
(256MB)
1553
(BU-67301)
Local Bus
A
microSD
Flash(Soc et)
QSPI Flash
(2 x 128Mb)
Programmable Logic (PL)
Sw
microUSB
(8:11) (15:12)
Platform
Manager
COM0
IPMI
EPROM
V & T
Sensors
Ref
Cloc s
Power
Supplies
(7:0)
GTX Transceivers
VPWR
(5V or 12V)
I2C
3.3V
PCIE
RefCl
PCIE/HSSIO (7:0)
P5
P6
P6 RefCl
P6
PHY
PHY
PHYMAGS
ETH1
ETH0
USB1
COM1 (RS-232)
COM2 (RS-232)
USB2
PHY
DDR3 SDRAM
(512MB)
DDR3 SDRAM
(256MB)
PHY
USB0
USB3
GPIO (x48)
1553 A & B
B
TX-INH
MVMRO
Figure 1 : ADM-XRC-7Z2 Block Diagram
4.1.1 Switch Definitions
here are two sets of 8-way DIP switches for configuring the board.
heir locations are shown in Figure 2
Figure 2 : DIP Switch Locations
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Switch 1 Ref. Function OFF State ON State
SW1-1 Reserved - -
SW1-2 Flash Boot
Inhibit Allow PS to boot PL from flash Prohibit PS booting PL from flash
SW1-3 Systom Monitor
Upgrade Normal Operation Reserved for factory use
SW1-4 Reserved - -
SW1-5 XMC J AG Isolate J AG chain from P5 Connect J AG chain to P5
SW1-6 Reserved - -
SW1-7 Reserved - -
SW1-8 BU J AG En Exclude BU67301 from J AG chain Include BU67301 in J AG chain
Ta le 4 : Switch 1 Definitions
Switch 1 Ref. Function OFF State ON State
SW2-1 BootSel 0 See able 15
SW2-2 BootSel 1 See able 15
SW2-3 Independent
J AG Single (cascaded) J AG chain at J4 Independent J AG chains
SW2-4 PLL Bypass PS PLL is used PS PLL is bypassed
SW2-5 InhExtRst Do not mask MRS I
SW2-6 Reserved - -
SW2-7 USB3 Mode Zynq PS is USB Host and USB3 is
downstream port USB3 is O G port
SW2-8 System Reset Normal operation PS System Reset
Ta le 5 : Switch 2 Definitions
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4.1.2 LED Definitions
here are seven LEDs to provide a visual indication of the board status.
heir locations are shown in Figure 3
Figure 3 : LED Locations
Comp. Ref. Function ON State Off State
D5 (Green) System Monitor
Status See able 19
D6 (Red) System Monitor
Status See able 19
D8 (Green) FPGA (PL)
Done PL is configured PL is not configured
D9 (Green) Flash Boot
Enable Enable PS booting PL from flash Disable PS booting PL from flash
D10 (Amber) MVMRO Enable writes to non-volatile memories Inhibit writes to non-volatile memories
D11 (Red) Power Good Power Supplies off or faulty Power Supplies operating correctly
D12 (Green) System Reset PS is in Reset PS is not in Reset
Ta le 6 : Main LED Definitions
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A further two sets of three LEDs provide an indication of the status of the two Ethernet interfaces
Comp. Ref. Function ON State Off State
D23 (Green) Ethernet 0
LED0 See able 16
D22 (Green) Ethernet 0
LED1 See able 16
D21 (Amber) Ethernet 0
LED2 See able 16
D20 (Green) Ethernet 1
LED0 See able 16
D19 (Green) Ethernet 1
LED1 See able 16
D17 (Amber) Ethernet 1
LED2 See able 16
Ta le 7 : Ethernet LED Definitions
4.2 Primary XMC Connector P5
Full pinout information for this connector is listed in able 20
4.2.1 XMC Platform Interface
4.2.1.1 IPMI I2C
A 2 Kbit I2C EEPROM (type M24C02) is connected to the XMC IPMI. his memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
4.2.1.2 MBIST#
Built-In Self est. his output signal is driven active (low) by the Zynq PS signal MIO9 (pin A24). It should be
used to indicate that the board is performing self-test or that the Programmable Logic (PL) section of the SoC is
unconfigured.
4.2.1.3 MVMRO
XMC Write Prohibit. his signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. Amber LED D10 indicates a warning when this signal is not set and writes to
non-volatile memory are enabled. he signal has a 100k pull-up resistor to assert it by default.
his signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the Zynq
PS at MIO50 (pin A19).
4.2.1.4 MRSTI#
XMC Reset In. his signal is an active low input from the carrier and should be used to reset any PCIE endpoint.
he MRS I# signal is translated to 1.5V levels and connected to the Zynq PL at pin K2.
4.2.1.5 MRSTO#
XMC Reset Out. his optional output signal is connected to the Zynq PL at pin J4. It should only be driven when
the board is connected to a master or Root Complex carrier slot.
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4.2.1.6 MPRESENT#
Module Present. his output signal is connected directly to 0V.
4.2.1.7 JTAG
See Section Section 4.4
4.2.2 P5 HSSIO Links
Eight pairs of HSSIO links from the Zynq PL are routed to XMC connector P6.
he pinout and coupling of these links are compatible with PCI Express.
he ransmit ( x) side of all eight lanes are AC coupled by 100nF capacitors, placed at the output from the PL.
he Receive (Rx) side of all eight lanes are directly connected from the connector to the PL.
Alternative coupling options are available as a special ordering option. Please contact Alpha Data for details.
4.3 Secondary XMC Connector P6
Full pinout information for this connector is listed in able 21
4.4 JTAG Interfaces
4.4.1 On- oard Interface
By default, the 7Z2 is configured to have a single (cascaded) J AG scan chain connected to header J4. his
allows the connection of the Xilinx J AG cable for debug using the Xilinx ChipScope tools.
he board can also be set to have two independent scan chains using DIP switch SW2-3. (See able 5. In
independent mode, the main chain (with the Zynq PL, CPLD and XRM interface) is connected to J4, while the
Zynq PS is connected to header J3.
If the cascaded or main scan chain is connected to the XMC connector (when SW1-5 is ON), header J4 should
not be used.
4.4.2 XMC Interface
he J AG interface on the XMC connector is normally unused and XMC_ DI connected directly to XMC_ DO.
he interface can be connected to the cascaded or main interface (through level-translators) by switching SW1-5
ON. See able 4
4.4.3 JTAG Voltages
he on-board J AG scan chains uses 1.8V. he Vcc supply provided on J3 and J4 to the J AG cable is +1.8V
and is protected by a poly fuse rated at 350mA. 3.3V signals must not be used at header J3 or J4.
he J AG signals at the XMC interface use 3.3V signals and are connected through level translators to the
on-board scan chain.
he J AG signals at the XRM2 interface use the adjustable voltage XRM_VIO.
4.5 Clocks
he board has nine reference clocks: one from the carrier, and eight generated on-board.
he clocks MG CLK250M, PROGCLK, REFCLK200M and E H_CLK25M are generated by a single Silicon
Labs Si5338B and are all synchronous.
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Note:
Clock ermination
he LVDS clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute "DIFF_ ERM = RUE". his can either be set in the source code when
instantiating the buffer, or in the User Constraints File (UCF).
4.5.1 PCIe Reference Clock (PCIEREFCLK)
he 100MHz PCI Express reference clock is provided by the carrier card through the Primary XMC connector,
P5, at pins A19 and B19. his is connected to the Zynq PL via 10nF AC coupling capacitors. On the Zynq PL, it
is connected to G X Quad 112 to allow its use as reference for the eight G X lanes on Quads 111 and 112.
Signal arget FPGA Input IO Standard "P" pin "N" pin
PCIEREFCLK MG REFCLK0_112 HSCL N8 N7
Ta le 8 : PCIEREFCLK Connections
4.5.2 MGTCLK250M
he fixed 250.0MHz reference clock, MG CLK250M, is a differential clock signal using LVDS. It is connected to
MG REFCLK inputs on the Zynq PL at G X Quad 111. (See Figure Figure MG Links.)
Signal arget FPGA Input IO Standard "P" pin "N" pin
MG CLK250M MG REFCLK0_111 LVDS_25 U8 U7
Ta le 9 : MGTCLK250M Connections
4.5.3 PROGCLK
he programmable clock, PROGCLK, is a differential clock signal using LVDS. It is connected to MG REFCLK
inputs on the Zynq PL at G X Quad 111. (See Figure Figure MG Links.)
Signal arget FPGA Input IO Standard "P" pin "N" pin
PROGCLK MG REFCLK1_111 LVDS_25 W8 W7
Ta le 10 : PROGCLK Connections
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4.5.4 REFCLK200M
he fixed 200MHz reference clock, REFCLK200M, is a differential clock signal using LVDS. hree
phase-matched copies are distributed to Global Clock inputs on the Zynq PL.
his clock can be used to generate application-specific clock frequencies using the PLLs within the Virtex-6
FPGA. It is also suitable as the reference clock for the IO delay control block (IDELAYC RL) and memory
interfaces.
Signal arget FPGA Input IO Standard "P" pin "N" pin
REFCLK200M_A IO_L13_MRCCC_10 LVDS_25 AG17 AG16
REFCLK200M_B IO_L12_MRCC_33 SS L15 G5 G4
REFCLK200M_C IO_L13_MRCC_33 SS L15 F5 E5
Ta le 11 : REFCLK200M Connections
4.5.5 PS_CLK33M3
he Zynq PS is provided with a 33.333MHz reference clock at the PS_CLK input on pin A22. his clock is
asynchronous to the clocks generated by the Si5338B.
Signal arget FPGA Input IO Standard "P" pin "N" pin
PS_CLK33M3 PS_CLK_500 LVCMOS18 A22 -
Ta le 12 : PS_CLK33M3 Connections
4.5.6 USB_REFCLK24M
he USB PHY and hub are provided with a 24.0MHz reference clock. his clock is asynchronous to the clocks
generated by the Si5338B and is not connected to the Zynq SoC.
4.5.7 ETH_CLK25M
he Ethernet PHYs are provided with 25.0MHz reference clocks generated by the Si5338B. hese are not
connected to the Zynq SoC.
4.5.8 ETH1_CLK125M
he Ethernet PHY 1 generates a 125MHz reference clock that is connected to the Zynq PL at pin AF14.
Signal arget FPGA Input IO Standard "P" pin "N" pin
E H1_CLK125M IO_L12_MRCC_10 LVCMOS25 AF14 -
Ta le 13 : ETH1_CLK125M Connections
4.5.9 BU_REFCLK40M
he BU-67301 and Zynq PL are provided with a 40.0MHz reference clock. It is connected to the PL on
clock-capable pin AE28. his clock is asynchronous to the clocks generated by the Si5338B.
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Signal arget FPGA Input IO Standard "P" pin "N" pin
BU_REFCLK40M IO_L13_MRCC_12 LVCMOS33 AE28 -
Ta le 14 : BU_REFCLK40M Connections
4.5.10 BU_HOST_CLK
In addition to the reference clocks, there is an additional clock, BU_HOS _CLK, used for the local bus interface
between the Zynq PL and the BU-67301. wo phase-matched copies of BU_HOS _CLCK_OU should be
generated by the Zynq PL on pins AD25 and AE26.
BU_HOS _CLK_OU _A on pin AD25 is connected to the HOS _CLK input on the BU-67301.
BU_HOS _CLK_OU _B on pin AE26 is connected back in to the PL on pin AC28 as "BU_HOS _CLK".
4.6 Resets
he Zynq PS can be reset using the System Reset switch, SW2-8.
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4.7 Zynq PS Block
4.7.1 Boot Modes
BootSel1
(SW2-2) BootSel0 (SW2-1) Boot Mode
OFF OFF J AG
OFF ON Quad SPI
ON OFF SD Flash
ON ON Reserved
Ta le 15 : Boot Mode Selection
4.7.2 PS Memory Interfaces
4.7.2.1 Quad SPI Flash Memory
512Mb of QSPI flash memory (Micron N25Q256A11E1240E/M 41K128M16J ) is attached to the PS, and is
used to store Zynq boot images, FPGA bitstreams and data.
4.7.2.2 MicroSD Flash Memory
An on-board microSD card holder is available to store Zynq boot images, FPGA bitstreams and data.
4.7.2.3 PS DDR3 Memory
he PS has one bank of DDR3 memory, constisting of 2 16-bit wide memory devices in parallel to provide a
32-bit datapath capable of running up to 533MHz (DDR-1066). 2Gb devices (Micron M 41K128M16J -125) are
fitted as standard to provide 512MB per bank.
4.7.3 Ethernet Interfaces
he 7Z2 has two Ethernet Interfaces at rear connector P6. Interface E H0 is connected to the Zynq PS, while
E H1 is connected to the PL
Both interfaces have a Marvell 88E1512 PHY, connected to the Zynq via RGMII.
PL
P4
PHY
SGMII / 1000BASE-X RGMII
PS
PHYMagnetics
MDI RGMII
ETH0
ETH1
Figure 4 : Ethernet Interfaces
Each interface has three status LEDs. he functions of these are shown in able 16below.
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LED Colour Function
0 Green .
1 Green .
2 Amber .
Ta le 16 : Ethernet Status LEDs
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4.7.4 Serial COM Ports
PL
P4
PHY
PS
PHY
COM1
COM2
Platform Mgr
COM0I2C
RS-232
RS-232
COM1
COM2
Figure 5 : Serial COM Ports
4.7.5 USB Interfaces
PL
PHY ULPI
4 port
Hub
P4
USB1
USB2
Micro
USB
0
0 0
ExtHostSel
Figure 6 : USB Interfaces
4.8 Zynq PL Block
4.8.1 PL DDR3 Memory
he PL has two banks of DDR3 memory, each constisting of a single 16-bit wide memory device, capable of
running up to 800MHz (DDR-1600). 2Gb devices (Micron M 41J64M16-187E) are fitted as standard to provide
256MB per bank.
he memory banks are arranged for compatibility with the Xilinx Memory Interface Generator (MIG). Full details
of the interface, signaling standards are provided in the example design.
4.8.2 1553 Bus Controller
he PL is connected to a BU-67301B 1553 bus controller. he pinout is available in the example design.
4.8.3 Rear GPIO Interface
here are 20 single ended GPIO and 16 differential pairs connected to the P6 connector. he pinout is available
in the example design.
4.9 System Monitoring
he 7Z2 has the ability to monitor temperature and voltage to maintain a check on the operation of the board.
he monitoring is implemented using an Atmel AVR microcontroller (uC).
he microcontroller continually measures all voltage rails and temperature sensors and transmits the results to
the FPGA, where they are stored in blockram.
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ADM-XRC-7Z2 User Manual
V1.2 - 24th Fe 2020
he following voltage rails and temperatures are monitored by the microcontroller:
Monitor P rpose
VPWR Board Input Supply (either 5.0V or 12.0V)
12V0 12V Board Input Supply
5V0 5V Board Input Supply
3V3 Board Input Supply
2V5 FPGA IO Supply
AUX_IO_2V0 FPGA Aux IO Supply
1V8 FPGA Aux Supply, Flash Memory
MG _AUX_1V8 FPGA MG Aux Supply
1V5 DDR3 SDRAM, arget FPGA memory I/O
1V0 FPGA Core Supply (VccIN )
MG _1V2 FPGA MG Vtt Supply
MG _1V0 FPGA MG Vcc Supply
3V3_IN Internal 3.3V Supply
emp1 microcontroller internal temperature
emp2 MP422 internal temperature
emp3 FPGA on-die temperature (measured in MP422)
Ta le 17 : Voltage and Temperature Monitors (in microcontroller)
he SDK includes an example application ("monitor") that reads the system monitor sensor values.
4.9.1 Automatic Temperature Monitoring
he system monitor checks that the board and FPGA are being operated within the specified limits. If the
temperature is close to the limit, a "Warning Alarm" interrupt is set.
If a limit is exceeded, a "Critical Alarm" interrupt is set. After the Critical Alarm is set, there is a 5 second delay
before the system monitor unconfigures the FPGA by asserting its "PROG" pin.
he purpose of this mechanism is to protect the card from damage due to over-temperature. It is possible that it
will cause the user application and, possibly, the host computer to "hang".
he temperature limits are shown in able emperature Limits. Note that the Min and Max values include a 5°C
margin to prevent measurement errors triggering a false alarm.
.arget FPGA Board (uC and PCB)
Min Lower
Warning Upper Warning Max Min Lower Warning Upper Warning Max
Commercial -5°C +5°C +80°C +90°C -5°C +5°C +65°C +75°C
Extended -5°C +5°C +95°C +105°C -5°C +5°C +80°C +90°C
Industrial -45°C -35°C +95°C +105°C -45°C -35°C +80°C +90°C
Ta le 18 : Temperature Limits
4.9.2 System Monitor Status LEDs
LEDs D5 (Green) and D6 (Red) indicate the microcontroller status.
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