Lattice ECP2 Series Parts list manual

www.latticesemi.com 15-1 tn1108_02.5
June 2013 Technical Note TN1108
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The configuration memory in the LatticeECP2™ and LatticeECP2M™ FPGAs is built using volatile SRAM; there-
fore, an external non-volatile configuration memory is required to maintain the configuration data when the power is
removed. This non-volatile memory supplies the configuration data to the LatticeECP2/M when it powers-up, or any
other time the device needs to be updated.
To support multiple configuration options the LatticeECP2/M supports the Lattice sysCONFIG™ interface, as well
as the dedicated ispJTAG™ port. The available configuration options, or ports, are listed in Table 15-1.
Table 15-1. Supported Configuration Ports
This technical note covers all of the configuration options available for LatticeECP2/M.
General Configuration Flow
The LatticeECP2/M will enter configuration mode when one of three things happens, power is applied to the chip,
the PROGRAMN pin is driven low, or when a JTAG Refresh instruction is issued. Upon entering configuration mode
the INITN pin and the DONE pin are driven low to indicate that the device is initializing, i.e. getting ready to receive
configuration data.
Once the LatticeECP2/M has finished initializing, the INITN pin will be driven high. The low to high transition of the
INITN pin causes the CFG pins to be sampled, telling the LatticeECP2/M which port it is going to configure from.
The LatticeECP2/M then begins reading data from the selected port and starts looking for the preamble, BDB3
(hex). All data after the preamble is valid configuration data.
When the LatticeECP2/M has finished reading all of the configuration data, assuming there have been no errors,
the DONE pin goes high and the LatticeECP2/M enters user mode, in other words the device begins to function
according to the user’s design.
Note that the LatticeECP2/M may also be programmed via JTAG. When programming via JTAG, the INITN and
DONE signals have no meaning, because JTAG, per the IEEE standard, takes complete control of the chip and it’s
I/Os.
The Lattice ECP2/M devices are also available in an "S" version which supports the use of an encrypted bitstream
configuration file. These versions have the same configuration options as the standard versions, except where
noted in this document. When using these devices, the user should refer to the LatticeECP2/M Family Data Sheet
and TN1109, LatticeECP2/M Configuration Encryption Usage Guide, in addition to this document, to understand
the configuration requirements.
The following sections define each configuration pin, each configuration mode, and all of the configuration options
for the LatticeECP2/M.
Interface Port
sysCONFIG
SPI
SPIm
Slave Serial
Slave Parallel
ispJTAG JTAG (IEEE 1149.1 and IEEE 1532 compliant)
LatticeECP2/M sysCONFIG
Usage Guide

15-2
LatticeECP2/M sysCONFIG Usage Guide
Configuration Pins
The LatticeECP2/M supports two types of configuration pins, dedicated and dual-purpose. The dedicated pins are
used exclusively for configuration; the dual-purpose pins, when not being used for configuration, are available as
extra I/O pins. If a dual-purpose pin is to be used both for configuration and as a general purpose I/O (GPIO) the
user must adhere to the following:
• The I/O type must remain the same, in other words if the pin is a 3.3V CMOS pin (LVCMOS33) during configura-
tion it must remain a 3.3V CMOS pin as a GPIO.
• The user must select the correct CONFIG_MODE setting and set the PERSISTENT bit to OFF in order to use
the dual-purpose sysCONFIG pins as GPIO after configuration. In ispLEVER®these preferences can be set in
the Design Planner. If you are using Lattice Diamond™ design software, select Tools > Spreadsheet View and
then select the Global Preferences tab in the Spreadsheet View.
• The user is responsible for insuring that no internal or external logic will interfere with device configuration.
Also, if slave parallel configuration mode is not being used then one or both of the parallel port chip selects (CSN,
CS1N) must be high or tri-state during configuration.
Programmable options control the direction and type of each dual-purpose configuration pin. These options are
controlled via pin preferences in Lattice ispLEVER and Diamond software, or as HDL source file attributes.
The LatticeECP2/M also supports ispJTAG for configuration, transparent read back, and JTAG testing. The follow-
ing sections describe the function of the various sysCONFIG and JTAG pins. Table 15-2 is provided for reference.
Table 15-2. Configuration Pins for the LatticeECP2/M
Pin Name I/O Type Pin Type Mode Used
CFG[2:0] Input, weak pull-up Dedicated All
PROGRAMN Input, weak pull-up Dedicated All
INITN Bi-Directional Open Drain, weak pull-up Dedicated All
DONE Bi-Directional Open Drain with weak pull-
up, or Active Drive Dedicated All
CCLK Input or Output Dedicated All
DI/CSSPI0N2Input, weak pull up Dual-Purpose Serial, SPI, SPIm
DOUT/CSON2Output Dual-Purpose Parallel, Serial, SPI
CSN2Input, weak pull-up Dual-Purpose Parallel
CS1N2Input, weak pull-up Dual-Purpose Parallel
WRITEN2Input, weak pull-up Dual-Purpose Parallel
BUSY/SISPI2Output, tri-state, weak pull-up Dual-Purpose Serial, SPI, SPIm
D[0]/SPIFASTN2
Input or Output Dual-Purpose
Parallel, SPI, SPIm
D[1:6]2Parallel
D[7]/SPID02Parallel, SPI, SPIm
TDI Input, weak pull-up Dedicated JTAG
TDO Output, weak pull-up Dedicated JTAG
TCK Input with Hysteresis Dedicated JTAG
TMS Input, weak pull-up Dedicated JTAG
1. Weak pull-ups consist of a current source of 30µA to 150µA. The pull-ups for sysCONFIG dedicated and dual-purpose pins track VCCIO8;
the pull-ups for TDI, TDO, and TMS track VCCJ.
2. The sysCONFIG pins on the LatticeECP2M50/M70/M100 are dedicated sysCONFIG pins. The sysCONFIG output pins are actively driven
during normal device operation.

15-3
LatticeECP2/M sysCONFIG Usage Guide
Dedicated Control Pins
The following sub-sections describe the LatticeECP2/M dedicated sysCONFIG pins. These pins are powered by
VCCIO8.
While the device is under IEEE 1149.1 or 1532 JTAG control the dedicated programming pins have no meaning.
This is because a boundary scan cell will control each pin, per JTAG 1149.1, rather than normal internal logic.
CFG[2:0]
The Configuration Mode pins, CFG[2:0], are dedicated inputs with weak pull-ups. The CFG pins are sampled on
the rising edge of INITN and are used to select the configuration mode, i.e. what type of device the LatticeECP2/M
will configure from. As a consequence the CFG pins determine which groups of dual-purpose pins will be used for
device configuration (see the right-most column in Table 15-2). See Table 15-3 for a list of Configuration Modes.
Table 15-3. Configuration Modes
PROGRAMN
The PROGRAMN pin is a dedicated input with a weak pull-up. This pin is used to initiate a non-JTAG SRAM config-
uration sequence.
A high to low signal applied to PROGRAMN takes the device out of user mode and sets it into configuration mode.
The low to high transition will initiate the configuration process. The PROGRAMN pin can be used to trigger config-
uration at any time.
INITN
The INITN pin is a bidirectional open drain control pin. INITN is capable of driving a low pulse out as well as detect-
ing a low pulse driven in.
When the PROGRAMN pin is driven low, or a JTAG Reset instruction is received, or after the internal Power-On-
Reset signal is released during power-up, the INITN pin will be driven low to reset the internal configuration cir-
cuitry. Once the PROGRAMN pin is driven high, the configuration initialization begins. Once the configuration ini-
tialization is completed, the INITN pin will go high. To delay configuration the INITN pin can be held low externally.
The device will not enter configuration mode as long as the INITN pin is held low. A low to high transition on INITN
causes the CFG pins to be sampled, telling the LatticeECP2/M which port to use, and starts configuration.
During configuration the INITN pin becomes an error detection pin. If a CRC error is detected during configuration
INITN will be driven low. The error will be cleared at the beginning of the next configuration.
Configuration Mode CFG[2] CFG[1] CFG[0] D[0]/SPIFASTN
SPI Normal (0x03) 0 0 0 Pull-Up
Fast (0x0B) 0 0 0 Pull-Down
Reserved 001X
SPIm Normal (0x03) 0 1 0 Pull-Up
Fast (0x0B) 0 1 0 Pull-Down
Reserved 011X
Reserved 100X
Slave Serial 1 0 1 X
Reserved 110X
Slave Parallel 1 1 1 D0
Notes:
JTAG is always available for IEEE 1149.1 and 1532 support.

15-4
LatticeECP2/M sysCONFIG Usage Guide
DONE
The DONE pin is a dedicated bi-directional open drain with a weak pull-up (default), or it is an actively driven pin.
DONE goes low when INITN goes low, when INITN and PROGRAMN go high, and the internal Done bit is pro-
grammed at the end of configuration, the DONE pin will be released (or driven high, if it is an actively driven pin).
The DONE pin can be held low externally and, depending on the wake-up sequence selected, the device will not
become functional until the DONE pin is externally brought high. Externally delaying the wake-up sequence using
the DONE pin is a good way to synchronize the wake-up of multiple FPGAs; it is also required when configuring
multiple FPGAs from a single configuration device.
Sampling the DONE pin is a good way for an external device to tell if the FPGA has finished configuration. How-
ever, when using IEEE 1532 JTAG to configure SRAM the DONE pin is driven by a boundary scan cell, so the state
of the DONE pin has no meaning during IEEE 1532 JTAG configuration (once configuration is complete, DONE
reverts to internal logic and will be high).
CCLK
CCLK is a dedicated bi-directional pin; direction depends on whether a Master or Slave mode is selected. If a Mas-
ter mode (SPI or SPIm) is selected, via the CFG pins, the CCLK pin becomes an output; otherwise CCLK is an
input.
If the CCLK pin becomes an output, the internal programmable oscillator is connected to CCLK and is driven out to
slave devices. CCLK will stop 120 clock cycles after the DONE pin is brought high. The extra clock cycles ensure
that enough clocks are provided to wake-up other devices in the chain. When stopped, CCLK becomes an input
(tri-stated output). CCLK will restart (become an output again) on the next configuration initialization sequence.
The MCCLK_FREQ parameter (one of the global preferences in the Design Planner of ispLEVER or the Spread-
sheet View in Diamond) controls the CCLK master frequency (see data sheet On-Chip Oscillator section for the fre-
quency selection). The software default setting for the configuration CCLK is 2.5 MHz. For a complete list of the
supported Master Clock frequencies, please see the LatticeECP2/M Family Data Sheet. One of the first operations
during configuration is the MCCLK_FREQ parameter; once this parameter is loaded the frequency changes to the
selected value. Care should be exercised not to exceed the frequency specification of the slave devices or the sig-
nal integrity capabilities of the PCB layout.
When downloading an encrypted bitstream file to the LatticeECP2/M S-Series devices, the user must adhere to the
appropriate conditions for the CCLK signal. These conditions are shown in TN1109, LatticeECP2/M Configuration
Encryption Usage Guide.
Dual-Purpose sysCONFIG Pins
The following is a list of the dual-purpose sysCONFIG pins. If any of these pins are used for configuration and for
user I/O, the user must adhere to the requirements listed at the start of the Configuration pin sections. On
LatticeECP2M50/M70/M100 devices, the sysCONFIG pins described below are dedicated pins. When using the
same pins to access the external boot Flash, the system design must take care of tri-stating these output pins while
driving these pins from a different I/O pin.
These pins are powered by VCCIO8.
DI/CSSPI0N
The DI/CSSPI0N dual-purpose pin is designated as DI (Data Input) for Serial configurations. DI has an internal
weak pull-up. DI captures data on the rising edge of CCLK.
In SPI or SPIm mode the DI/CSSPI0N becomes a low true Chip Select output that drives the SPI Serial Flash chip
select.
DOUT/CSON
The DOUT/CSON pin is an output pin and has two purposes.

15-5
LatticeECP2/M sysCONFIG Usage Guide
For serial and parallel configuration modes, when BYPASS mode is selected, this pin becomes DOUT (see
Figure 15-9). When the device is fully configured a Bypass instruction in the bitstream is executed and the data on
DI, or D[0:7] in the case of a parallel configuration mode, will then be routed to the DOUT pin. This allows data to
be passed, serially, to the next device. In a parallel configuration mode D0 will be shifted out first followed by D1,
D2, and so on.
For parallel configuration mode there is a Flowthrough option as well. When Flowthrough mode is selected this pin
becomes Chip Select Out (CSON). When the device is fully configured, and the Flowthrough instruction in the bit-
stream is executed, the CSON pin is driven low to enable the next device. The data pins, D[0:7], are wired in paral-
lel to each device in the chain (see Figure 15-10).
In SPIm mode, the sysCONFIG daisy chaining mode of configuration is not supported.
The DOUT/CSON drives out a high on power-up and will continue to do so until the execution of the Bypass/Flow
Through instruction within the bitstream, or until the I/O Type is changed by the user code.
CSN and CS1N
Both CSN and CS1N are active low input pins with weak pull-ups and are used in parallel mode only. These inputs
are OR’ed and used to enable the D[0:7] data pins to receive or output a byte of data. Note: In the 144-pin TQFP
and 208-pin PQFP packages, CSN, CS1N and WRITEN are not bonded out.
When CSN or CS1N is high, the D[0:7], and BUSY pins are tri-stated. CSN and CS1N are interchangeable when
controlling the D[0:7], and BUSY pins. Driving both CSN and CS1N high causes the LatticeECP2/M to exit Bypass
or Flowthrough mode and resets the Bypass register. If Bypass or Flowthrough mode will not be used then CSN or
CS1N may be tied low, i.e. in this case it is only required that one of these pins be driven. The CSN and CS1N pins
must remain low while the configuration bitstream is being sent to the device or the configuration will fail.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve these pins as CSN and CS1N.
CSN and CS1N are not connected in the 100-pin TQFP and 208-pin PQFP devices. Note that SRAM may only be
read using JTAG or Slave Parallel mode.
WRITEN
The WRITEN pin is an active low input with a weak pull-up and used for parallel mode only. Note: In the 144-pin
TQFP and 208-pin PQFP packages, CSN, CS1N and WRITEN are not bonded out.
The WRITEN pin is used to determine the direction of the data pins D[0:7]. The WRITEN pin must be driven low in
order to clock a byte of data into the device and driven high to clock data out of the device.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve this pin as WRITEN. WRITEN
is not connected in the 100-pin TQFP and 208-pin PQFP devices. Note that SRAM may only be read using JTAG or
Slave Parallel mode.
BUSY/SISPI
The BUSY/SISPI pin has two functions.
In parallel configuration mode, the BUSY pin is a tri-stated output. The BUSY pin will be driven low by the device
only when it is ready to receive a byte of data on D[0:7] or a byte of data is ready for reading. The BUSY pin allows
the LatticeECP2/M to pause transfers on the parallel port.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve this pin as BUSY. Note that
SRAM may only be read using JTAG or Slave Parallel mode.
In SPI or SPIm configuration modes, the BUSY/SISPI pin becomes an output that drives control and data to the
SPI Serial Flash. Control and data are output on the falling edge of CCLK. If SPI memory needs to be accessed

15-6
LatticeECP2/M sysCONFIG Usage Guide
using the SPI port while the part is in user mode (the DONE pin is high) then the PERSISTENT preference must be
set to ON to preserve this pin as SISPI.

15-7
LatticeECP2/M sysCONFIG Usage Guide
D[0]/SPIFASTN
The D[0]/SPIFASTN pin has two functions.
In parallel mode this pin is D[0] and operates in the same way as D[1:6] below. Taken together D[0:7] form the par-
allel data bus, D[0] is the most significant bit in the byte. As with D[1:6], if SRAM (configuration memory) needs to
be accessed using the parallel pins while the part is in user mode (the DONE pin is high) then the PERSISTENT
preference must be set to ON to preserve this pin as D[0]. Note that SRAM may only be read using JTAG or Slave
Parallel mode.
In SPI or SPIm mode the D[0]/SPIFASTN pin becomes an input. SPIFASTN is sampled on the rising edge of
INITN. If SPIFASTN is high the LatticeECP2/M will use SPI Serial Flash read op-code 03 (hex). Read op-code 03
(hex) is the standard read command used by all “25” series SPI Serial Flash. If SPIFASTN is low the
LatticeECP2/M will use SPI Serial Flash fast read op-code 0B (hex). The fast read op-code 0B (hex) accommo-
dates higher frequency read clocks, exact clock speeds can be found in the SPI Serial Flash manufacturer’s data
sheet.
If SPI memory needs to be accessed using the SPI port while the part is in user mode (the DONE pin is high) then
the PERSISTENT preference must be set to ON to preserve this pin as SPIFASTN.
When using the SPI or SPIM mode the SPIFASTN pin should either be tied high or low. It must not be left floating
or configuration problems will occur.
Not all SPI Serial Flash support the 0B (hex) fast read op-code, consult the manufacturer’s data sheet. Care must
also be taken not to exceed the signal integrity capabilities of the PCB layout.
D[1:6]
The D[1:6] pins support parallel mode only. The D[1:6] pins are tri-statable bi-directional I/O pins used for data write
and read. When the WRITEN signal is low, and the CSN and CS1N pins are low, the D[1:6] pins become data
inputs. When the WRITEN signal is driven high, and the CSN and CS1N pins are low, the D[1:6] pins become data
outputs. If either CSN or CS1N is high D[1:6] will be tri-state.
If SRAM (configuration memory) needs to be accessed using the parallel pins while the part is in user mode (the
DONE pin is high) then the PERSISTENT preference must be set to ON to preserve this pin as D[1:6]. Note that
SRAM may only be read using JTAG or Slave Parallel mode.
Care must be exercised during read back of EBR or PFU memory. It is up to the user to ensure that reading these
RAMs will not cause data corruption; corruption may be caused when these RAMs are read while being accessed
by user code.
D[7]/SPID0
The D[7]/SPID0 pin has two functions.
In parallel mode this pin is D[7] and operates in the same way as D[1:6] above. Taken together D[0:7] form the par-
allel data bus, D[7] is the least significant bit in the byte. As with D[1:6], if SRAM (configuration memory) needs to
be accessed using the parallel pins while the part is in user mode (the DONE pin is high) then the PERSISTENT
preference must be set to ON to preserve this pin as D[7]. Note that SRAM may only be read using JTAG or Slave
Parallel mode.
In SPI or SPIm mode the D[7]/SPID0 pin becomes an input and should be wired to the output data pin of the SPI
Serial Flash. The data on SPID0 is clocked in on the rising edge of CCLK. If SPI memory needs to be accessed
using the SPI port while the part is in user mode (the DONE pin is high) then the PERSISTENT preference must be
set to ON to preserve this pin as SPID0.
ispJTAG Pins
The ispJTAG pins are standard IEEE 1149.1 TAP (Test Access Port) pins. The ispJTAG pins are dedicated pins and
are always accessible when the LatticeECP2/M device is powered up. While the device is under 1149.1 or 1532

15-8
LatticeECP2/M sysCONFIG Usage Guide
JTAG control the dedicated programming pins INITN, DONE, and CCLK have no meaning. This is because a
boundary scan cell will control each pin, per the IEEE standard, rather than normal internal logic. While the
LatticeECP2/M is under JTAG control the PROGRAMN pin will be ignored.
These pins are powered by VCCJ.
TDO
The Test Data Output pin is used to shift out serial test instructions and data. When TDO is not being driven by the
internal circuitry, the pin will be in a high impedance state. This pin should be wired to TDO of the JTAG connector,
or to TDI of a downstream device in a JTAG chain. An internal pull-up resistor on the TDO pin is provided. The
internal resistor is pulled up to VCCJ.
TDI
The Test Data Input pin is used to shift in serial test instructions and data. This pin should be wired to TDI of the
JTAG connector, or to TDO of an upstream device in a JTAG chain. An internal pull-up resistor on the TDI pin is
provided. The internal resistor is pulled up to VCCJ.
TMS
The Test Mode Select pin controls test operations on the TAP controller. On the falling edge of TCK, depending on
the state of TMS, a transition will be made in the TAP controller state machine. An internal pull-up resistor on the
TMS pin is provided. The internal resistor is pulled up to VCCJ.
TCK
The test clock pin, TCK, provides the clock to run the TAP controller state machine, which loads and unloads the
JTAG data and instruction registers. TCK can be stopped in either the high or low state and can be clocked at fre-
quencies up to that indicated in the device data sheet. The TCK pin supports hysteresis; the typical hysteresis is
approximately 100mV when VCCJ = 3.3V. The TCK pin does not have a pull-up. A pull-down resistor between TCK
and ground on the PCB of 4.7 K is recommended to avoid inadvertent clocking of the TAP controller as VCC ramps
up.
When downloading an encrypted bitstream file to the LatticeECP2/M S-Series devices, the user must adhere to the
appropriate conditions for the TCK signal. These conditions are shown in TN1109, LatticeECP2/M Configuration
Encryption Usage Guide.
Optional TRST
Test Reset, TRST, in not supported on the LatticeECP2/M.
VCCJ
Having a separate JTAG VCC (VCCJ) pin lets the user apply a voltage level to the JTAG port that is independent
from the rest of the device. Valid voltage levels are 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V, but the voltage used must
match the other voltages in the JTAG chain. VCCJ must be connected even if JTAG is not used.
Please see In-System Programming Design Guidelines for ispJTAG Devices for further information.
Configuration and JTAG Pin Physical Description
All of the sysCONFIG dedicated and dual-purpose pins are part of Bank 8. Bank 8 VCCIO determines the output
voltage level of these pins, input thresholds are determined by the I/O Type selected in the ispLEVER Design Plan-
ner (default is 3.3V LVCMOS) or Diamond Spreadsheet View.
JTAG voltage levels and thresholds are determined by the VCCJ pin, allowing the LatticeECP2/M to accommodate
JTAG chain voltages from 1.2V to 3.3V.
Configuration Modes
The LatticeECP2/M devices support many different configuration modes, utilizing either serial or parallel data
paths. On power-up, when a JTAG Refresh instruction is issued, or when the PROGRAMN pin is toggled, the
CFG[2:0] pins are sampled to determine the configuration mode. See Table 15-3 above for a list of available config-
uration modes.

15-9
LatticeECP2/M sysCONFIG Usage Guide
The following sub-sections break down each configuration mode. For more information on the options for each
mode, see the section below entitled Configuration Options.
SPI Mode
The LatticeECP2/M offers a direct connection to memories that support the SPI Serial Flash standard (see
Table 15-6). By setting the configuration pins, CFG[2:0], to all zeros the LatticeECP2/M will configure from the SPI
interface. The SPI interface supports two configuration topologies:
• One FPGA configured from one SPI Serial Flash
• Multiple FPGAs configured from one SPI Serial Flash
The required boot memory size for each of the ECP2/M device sizes is shown in Table 15-4. The values shown are
for a single LatticeECP2/M device. The size for a dual-boot application would be twice that shown.
Table 15-4. Maximum Configuration Bits - SPI Flash Mode Bitstream File
Table 15-5. Maximum Configuration Bits - Serial and Parallel Mode Bitstream File
Device Bitstream Size (Mb) SPI Flash (Mb) Dual Boot SPI Flash (Mb)
ECP2-6 1.5 2 4 / 82
ECP2-12 2.9 4 8
ECP2-20 4.5 8 16
ECP2-35 6.3 8 16
ECP2-50 8.9 16 32
ECP2-70 13.3 16 32
ECP2M-20 5.9 8 16
ECP2M-35 9.8 16 32
ECP2M-50 15.8 16 64
ECP2M-70 19.8 32 64
ECP2M-100 25.6 32 64
1. These values apply for both encrypted and unencrypted bitstream files in the SPI Flash mode except as noted
below.
2. For the LatticeECP2-6 S-Series device, the dual Boot Flash size required is 8 Mb due to the number of sectors
required.
Device
All Modes Slave Serial Mode Slave Parallel Mode
Unencrypted Bitstream
Size (Mb)
Encrypted Bitstream
Size (Mb)
Encrypted Bitstream
Size (Mb)
ECP2-6 1.5 2.3 7.5
ECP2-12 2.9 4.3 14.2
ECP2-20 4.5 6.7 22.0
ECP2-35 6.3 9.4 31.2
ECP2-50 8.9 13.4 44.3
ECP2-70 13.3 20.0 66.1
ECP2M-20 5.9 8.9 29.5
ECP2M-35 9.8 14.8 48.9
ECP2M-50 15.8 23.7 78.6
ECP2M-70 19.8 29.7 98.6
ECP2M-100 25.6 38.5 127.6

15-10
LatticeECP2/M sysCONFIG Usage Guide
The estimated time for configuration can be calculated by dividing the bitstream size (in bits) from Table 15-4 by the
CCLK frequency. The CCLK frequency can be set using the global preferences tab within the ispLEVER Design
Planner or the Spreadsheet View (Global Preferences tab) in Diamond. For more information on setting the CCLK
frequency, please see the Master Clock section and the D[0]/SPIFASTN pin section of this document.
When downloading an encrypted bitstream file to the LatticeECP2/M S-Series devices, the user must adhere to the
appropriate conditions for the CCLK signal. These conditions are shown in TN1109, LatticeECP2/M Configuration
Encryption Usage Guide.
Table 15-6. SPI Serial Flash Vendor List
One FPGA, One SPI Flash
The simplest SPI configuration consists of one SPI Serial Flash connected to one LatticeECP2/M, as shown in
Figure 15-1. This is also the recommended method for use when downloading an encrypted bitstream file to the
LatticeECP2/M S-Series devices.
Figure 15-1. One FPGA, One SPI Serial Flash
Multiple FPGA, One SPI Flash
With a sufficiently large SPI Flash multiple FPGAs can be configured as shown in Figure 15-2. The first FPGA is
configured in SPI mode; the following FPGAs are configured in Slave Serial mode.
Vendor Part Number
ST Microelectronics M25Pxx
Winbond W25Pxx
Silicon Storage Technology SST25VFxx,
SST25LFxx
Spansion S25FLxx
Atmel AT25Fxx
NexFlash NX25Pxx
Macronix MX25Lxx
Note: This is not meant to be an exhaustive list and may be updated
from time to time.
Lattice FPGA
SPI Mode
CCLK
DI/CSSPI0N
BUSY/SISPI
D7/SPID0 DOUT
CFG1
CFG0
SPIFASTN
SPI Serial
Flash
Q
C
CFG2
D0/SPIFASTN
PROGRAMN
DONE
D
/CS