Lexicon MPX - ADDENDUM REV 1 User manual

I
MPX·1™
TECHNICAL MANUAL
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TABLE OF CONTENTS
WARNING • • • • • • • • • . • • • • • • • • • • • • • 5
About MPX-l •••••••••••••••••••• 5
Technical overview • • • • • • • • • • 5
How to use the MPX-l • • •• 6
MPX-l
block diagram ••••••• •••• 6
Local address map •••• 7
Accessing memory on the bus •••• 7
Accessing I/O ports on the bus ••••• •••• 8
Getting the MPX-l attention 8
Getting the main system CPU's attention •••• 8
Interrupt acknowledge response on the bus • • •• 9
Hardware switch setting and jumper options • • • • 9
Switch settings ••••• ••••• 9
Switch 1 - ATTN port address select •••••• 9
Standard ATTN port address selection •9
Swi tch 2••••••• •• ••• • •••• 9
Interrupt "CALL" jumpers •••••••••••• 10
Selecting and using 4K or 16K RAM chips • • • • 10
Using 2147 4K x 1 type RAM chips •10
Using 2167 16K x 1 type RAM chips •••• 11
Configuring the MPX-l for different size EPROMS •• •••• 11
Using a2716 or 2732 EPROM •••••••••••••••• 11
Using a2764 EPROM •••••••••• 11
Standard software supplied with MPX-l • 12
Basic command structure and protocol • • • • • • 12
Opcode
byte ••••••••••••• • • •• 12
Status indication-''byte ••••• •• ••••• •13
General purpose parameter bytes 0 through 8 • • 14
Link address bytes • • • • • • • • • 14
Result 1 and result 2 bytes ••••••••••••14
General notes • • •• •••••• • • 14
Command descriptions •••• •••••••••• • 15
NOP - no operation •••• •••• 15
RESET - reset the MPX-l •••••• 15
SET MASK -mask or unmask interrupt inputs to MPX-l 15
SENDDEOI - send end-of-interrupt command
to interrupt controller ••••••
READREG - read interrupt controller registers
SETRESPONSE - set interrupt response byte
SIZE - indicate whether 4K or 16K MPX-l
LOADRAM - load MPX local RAM from system RAM
EXRAM - execute a program in local RAM •
BLKMOV - move block of RAM of system bus ••••
FASTMOV - move block of RAM on system bus - fast •
RESERV&p - opcode •••••••••••••••
3

~ .. . . . . . . .19
-------------------------- DISCLAIMER --------------------------
Godbout Electronics makes no representations or warranties with
respect to the contents hereof and specifically disclaims any
implied warranties of merchantability or fitness for any
particular purpose. Further, Godbout Electronics reserves the
right to revise this publication and to makes any changes from
time to time in the content hereof without obligation of Godbout
Electronics to notify any person of such revision or changes.
-------------~---------------------------------------- ---------
This document was proofread with the aid
of SpellGuard T M from ISA, Menlo Park, CA.
4

FIRST - A WORD OR TWO OF WARNING!
This manual is intended to guide the sophisticated systems integrator or
OEM through the hardware features of the MPX-l. This manual is not intended for
novice or inexperienced users. If you are an end-user who has purchased an MPX-
t:ne J.nt:errupt: response 1.S nanuJ.eu oy LIlt= UU-UU<:lJ.U .LLlLCL L up'" ... VLl ... LV ............ ~ •• - -~ -,
taking up no processing time on the bus.
When needed, the MPX-1 can access any system resource on the bus. This
means that it can talk to any I/O port or memory location on the bus. It does
this by requesting the bus from the permanent master on a cycle-by-cycle basis.
This request/grant procedure is fully arbitrated to 16 levels as provided for by
the IEEE 696/5-100 bus standard. This allows up to 16 such devices to exist in
a system at any given time. Multiple MPX-ls could even be used.
The uses of the MPX-l are vast. Obvious uses would include terminal inter-
rupt handlers, print spoolers, task allocation and management, and resource
control. A unique feature of the MPX-l allows it to load execution code from
the system memory so that the MPX-l's function can be altered dynamically.
5

HOW TO USE THE HPX-l
A simplified block diagram of the MPX-1 appears in Figure 1. In the
following discussions, it may be useful to refer to the block diagram.
J - - _ •• z -t._~ ... A_,H,.t-\7 n .... rview of how the MPX-1 works: When the on-
I/O accesses, the on-boara .1ogl.C ~a~t::t> Io'G" '" ...... ~ .. __ •••• __ ~ •
the actual running of the bus cycle. The 8085 will "stall" until the operation
is completed allowing program operation to continue.
Sounds simple, doesn't it? Well, it is. The following sections discuss
the above overview in greater detail. First is a local address ~ap showing
where everything lives on the MPX-l.
Figure 1. MPX-l BLOCK DIAGRAM -.,
ADDRESS, STATUS
& CONTROL BUSES
DATA BUSES
DMA HANDSHAKE
5-100
BUS
VECTORED INTERRUPTS
CONTROL INPUTS
INTERRUPT OUTPUT
-i I
8-100
LOCAL
BUS ROM
INTERFACE
AND 8085
DMA LOGIC
CPU
LOCAL
RAM
INTERRUPT
CONTR.
RST.
7.5 SOD
t ATTN
PORT
6

LOCAL ADDRESS MAP
FROM
TO
SIZE
FUNCTION
NOT~S
------------------------------------------------------------------
0000 3FFF 4-16K
RAM
1,4
4000
SFFF 2-8K
EPROM
1,2,5
8000 8001 28259A
Registers
8002 1
Set
Interrupts Latch
2
8004 1
DMA
Address Bits 8-15
3
8005 1
DMA Address Bits
16-23 3
8007 1
Interrupt Response Byte 3
COOO
FFFF
16K
External
Window 6
All I/O Ports 256 External
Window 6
Notes: 1. RAM and EPROM exchange locations for power-on-jump.
2. Read Only.
3. Write Only.
4. 4K or 16K depending on chips used.
5. 2K fo~ 2716, 4K for 2732, 8K for 2764.
6. Lower 8 address bits (AO-7) pass through.
ACCESSING MEMORY ON THE BUS
An access to memory that resides on the 5-100 Bus will be performed if the
CPU makes an access to th~ range noted as the external window in the address map
above (addresses COOO to FFFF). The low order 8 bits of the address (AO-7) will
be taken from the CPU's address lines directly, while the high order 16 bits
(A8-23) will come from the address that has been previously written to the DMA
address registers. So the procedure for accessing memory on the bus would be:
1. Write desired AB-15 bits to memory location B004.
2.
Write desired A16-23 bits to memory location BOOS.
3. Perform amemory reference to COXX to FOXX, where XX
represents the low order B bits (AO-7) of the desired address.
If the memory reference to the external window is a read operation, then a
memory
read will occur on the bus. If the memory reference is write operation,
data will be written to the memory on the bus. Note that Ml cycles may also be
executed on the bus meaning that the MPX-1 may actually execute a small amount
of code (less than 256 bytes) directly from the bus.
Note that the high order byte of the external window is insignificant. Any
address in the range COOO to FFFF will be treated identically. For example,
C083, BD83, A9B3, and FFB3 would all access the same external memory location -
XXXX83 , where XXXX are the two bytes from the DMA address registers.
7

ACCESSING I/O PORTS ON THE BUS
All of the "I/O Ports" local to the MPX-l are "memory mapped". This means
they are decoded in the memory address space rather than in the I/O space. This
leaves all 256 I/O addresses free. Any input or output cycle performed by the
CPU will cause a corresponding cycle to be executed on the S-lOO Bus. Since the
lower 8 bits of the DMA Address pass through from the actual lower 8 address
bits from the CPU, the port address specified in the I/O instruction will be the
one accessed on the bus.
The high order 8 bits of the I/O access will come from the DMA address
register as in a memory reference. This allows the port aduress to be
"mirrored" in A8-lS as early S-lOO (8080) processors did, or thit> byte may be
loaded with different data to emulate Z-80 I/O modes (the 2-8U passes the
accumulator contents on A8-l5). This also allows the MPX-1 to emulate the
current generation of 16 bit processors such as the CPU 8085/88, CPU 86/87 and
the CPU 68K, which can put out 16 bit I/O addresses.
If an input instruction is executed, then an input cycle will be performed
on the S-lOO Bus. If an output instruction is executed, then an output cycle
will be performed on the bus.
GE'ITING THE HPX-l's ATTENTION
In any system it will be necessary for the main CPU in the sydcem to get
the attention of the MPX-l. This can be for initial start-up of the MPX-l, or
to "interrupt" its current task to be given another. This is done through a
mechanism called the ATTN port. This port is on the S-100 Bus and its address
is selec ted by swi tch S1. When the system CPU executes an output to the ATTN
port, a RST 7.5 will be generated to the on-board 8085. Note that no data is
accepted by the MPX-l. .~
GET'l'ING THE MAIN SYSTEM CPIrS ATTENTION
The MPX-1 may need to get the attention of the system CPU to tell it that a
task is complete, a buffer is nearing full, or many other reasons. The MPX-1
may
signal the main CPU by causing an interrupt on the bus. This interrupt may
occur on the INT*, NMI* or any of the vectored interrupt lines. A hardware
jumper is used to select which of the ten possible lines are used.
Two methods of causing this interrupt are available, again selected by a
jumper. The first type uses the Serial Output Data (SOD) line from the 8085 to
cause the interrupt. The state of this line is set and reSet by the Set Inter-
rupt Mask (SIM) instruction. The state of the interrupt request must be reset
in software.
The second method uses a one bit latch that is set by performing a read
from address 8002 (set Interrupt Latch in the address map above). This latch is
automatically reset by the occurrence of an interrupt acknowledge cycle.
Note that if one of the vectored interrupt lines is selected to cause the
system interrupt, the corresponding interrupt input to the 8259A should be
masked, unless you want the MPX-l to interrupt itself.
8

INTERRUPT ACKNOWLEDGE RESPONSE ON THE BUS
The MPX-1 may provide a single byte of data during bus interrupt acknow-
ledge cycles. This response must be enabled by a switch. The data to be passed
during interrupt acknowledge cycles is written to the latch a~ address B007
~ . - -~--- - ~ n - - -~_"~ U" .. a ~ nr hp ;In d~r"",e-",s-",s---"m ... a.,.p,---,a"-,b,,-,o,-,v,-,e-1)~' _
PADDLE
IF ADDRESS
BIT
1······ · ·
A7
2·· ·
A6
3
A5
"ON"
"a ..
4··· · ····
A4
5·· ·
A3
6
... ,.
A2
"OFF"
"1"
7· · ·· · ···
A1
8· · •·
AO
STANDARD ATTN PORT ADDRESS SELECTION
The COlRpuPro "standard" port address for MPX ATTN calls is Fl hex. To set
the MPX-1 to respond to ATTN calls on port F1 hex. set Sl as follows: Paddles 1-
4 and paddle 8 should be OFF. Paddles 5-7 should ON.
S2
PADDLE if
FUNCTION
1.-.· · "ON"
enables EPROM wait state •
2·
"ON"
enables
interrupt
response byte.
3
DMA
priority address
3
4··
DMA priority
address 2
"ON '"'
"0"
·
5·
DMA priority
address 1
6
DMA priority
address a
"OFF"
'"'
"1"
7··· "ON"
enables
SLAVE CLR*
to
reset MPX-l.
8...··
not used
9

INTElUlUPT "CALL" JUMPERS
The MPX-1 "calls" the system CPU by causing an interrupt on the bU:;l. There
are ten possible interrupt lines that the MPX-1 may assert. They are: INT*,
NMI* or any of the eight vectored interrupt lines (VIO*-VI7*). There are also
two methods by which the MPX-1 can assert the interrupt request - the SOD line
or by setting a hardware latch (described above in the section entitled "Getting
the Main System CPU's Attention").
The interrupt line asserted and the method of asserting it are selected by
Jumpers J1-10. These jumpers are implemented with push-on shorting plugs and
pins soldered into the board. Each jumper has three pins labeled A, B andC.
The "A" pin of each jumper is connected to the SOD interrupt source. The "c"
pin of each jumper is connected to the interrupt response latch. The "B" pin of
each jumper is connected to an interrupt line on the bus according to the chart
below:
JUMPER
/1 LEGEND MARKING
"B"
POSITION CONNECTION
17VI7*
2 6 VI6*
3 5 VI5*
4 4 VI4*
53VI3*
6 2 VI2*
71
VIl*
8aVIa*
9
NMI NMI*
10
INT
INT*
EXAMPLE: To connect the MPX-1 interrupt request output to the INT* line on the
bus with the interrupt source' from the SOD line, a shorting plug should be
installed at J1a from the "A" to "B" position (left of center).
EXAMPLE: To connect the MPX-1 interrupt request output to the VI3* line on the
bus with the interrupt source from the interrupt latch, a shorting plug should
be installed at J5 from the "B" to "c" position (right of center).
NOTE: The software supplied with the MPX-1 assumes the use of the SOD interrupt
mode, so if you wish to use the MPX in an interrupt driven mode with the
standard software, use only the SOD interrupt source.
SELECTING AND USING 4K OR 16K RAM. CHIPS
The MPX-1 can use either 2147 4Kxl RAM chips, or 2167 16Kx1 RAM chips. The
MPX-1 should have come from the factory already jumpered correctly for the type
of chip that was originally ordered with the board. Should it become necessary
to change these jumpers once the board is in the field, here is how different
RAMs are jumpered and inserted:
USING 2147 4Kxl TYPE BAM CHIPS
To use 2147 type RAM chips, jumpers J11 through J17 should be installed and
J18 should be open. Jl1 through J17 are located in-between the RAM array (U10-
10

17), and J18 is located at the right-hand side of the RAM array.. The RAM chips
come in 18 pin packs, but the sockets are 20 pin to accomodate 2167 type RAMs.
When using 2147 type RAMs, plug them in so that the chips are in the bottom-most
part of the socket, that is pins 1and 20 are blank.
USING 2167 16lCx1 TYPE RAM CHIPS
To use 2167 type RAM chips, jumper J18 should be installed and jumpers Jll-
17 should be open. Jumper J18 is located at the far right-hand side of the Rfu~
array and jumpers Jll-17 are located in-between the RAM chips.
CONFIGURING THE MPX-l FOR DIFFERENT SIZE EPROMS
The MPX-1 has a JEDEC 28 pin socket for the EPROM (U27). With the use of
one jumper, this socket can accomodate a2716, 2732 or a2764 type EPROM. This
gives 2K, 4K or 8K of storage, respectively.
USING A2716 or 2732 EPROM
To use a 2716 or 2732 type EPROM, jumper J19 should have a shorting plug
installed connecting pins "A" and "c" (left of center). J19 is located just
above U26. The 2716 or 2732 should be installed at location U27 such that it
uses the bottom-most pins of the socket, that is pins 1,2,27 and 28 are left
blank.
USING A2764 EPROM
To use a2764 type EPROM, jumper J19 should have a shorting plug installed
connecting pins "c" and "B" (right of center). J19 is located just above U26.
The 2764
should be installed at location U27, and all the pins of the socket are
used.
11

STANDARD SOFTWARE SUPPLIED WITH HPX-l
The
HPX-l is supplied wi th an EPROM that contains some general purpose
utility routines. It contains code to initialize the interrupt controllers (to
a benign state). several useful subroutines and a general purpose command
interpreter that implements a "channel protocol". Included are several built-in
commands to perform useful tasks such as loading and executing programs from
system memory. changing the interrupt controller parameters and block memory
moves on system RAM. The command structure includes a sophisticated "link"
protocol that allows chaining of command sequences and recursion.
Note that no representation is made that this is the most efficient way to
program or use an MPX board. Rather. it is intended as partly tutorial and
partly a useful way to get "up and running" with the MPX in aminimum amount of
time.
What follows is a discussion of the basic command structure and then
descriptions of the actual commands. Following that is a discussion of the code
itself that explains how to add custom commands and describes several useful
subroutines.
BASIC COMMAND STRUCTURE AND PROTOCOL
When the MPX-1 powers up. it masks all its interrupt inputs, does some
internal initialization and waits quietly for an ATTN on its ATTN port. When it
receives an ATTN it will read in 16 bytes from the system memory starting at
address 50 hex. The meaning of the bytes follows:
Byte 0:
Byte 1:
Byte 2:
Byte 10:
Byte 11:
Byte 12:
Byte 13:
Byte 14:
Byte 15:
Opcode Byte
Status Indication Byte
General Purpos~,Parameter Byte 0
General Purpose Parameter Byte 8
Link Address (least significant byte)
Link Address
Link Address (most significant byte)
Result 1 byte
Result 2 byte
The following is amore detailed description of the bytes shown above:
OPCODE BYTE
The opcode byte contains the information that tells the MPX what command to
execute. and also contains two bits that control the completion interrupt and
link structures. T~e actual bit coding of the opeode byte is shown below:
Bit 7
Bit 0
---------------------------------------------------------------
CONT IINT IoI
BIT 4I BIT 3I BIT 2I BIT 1I BIT 0I
---------------------------------------------------------------
12

Bits 0 through 4 of the opcode contain the "command number" of which there
are a possible 31 (one command is reserved). The first 10 commands have already
been defined and the remaining 21 may be implemented by you.
Command "OF" is reserved, and if invoked will be translated internally to a
NOP command.
The INT
bit (bit 6) of the opcode byte is the INTERRUPT ENABLE bit. If
this bit is set to one in the opcode, the MPX will cause an interrupt (SOD
interrupt) when it has completed the command. If this bit zero, an interrupt
will not be generated when the command has completed execution. Note that in
order for the interrupt to make it to the bus, it must be jumpered to an inter-
rupt line (see the hardware configuration section of this document for further
details) •
The CONT bit (bit 7) of the opcode byte is the CONTINUE bit and is asso-
ciated with the link structure. If the CONT bit is set high, execution of the
next command (pointed to by the link address) will commence immediately after
execution of the current command is complete. If the CONT bit is zero, the MPX
will stop when execution of the current command is complete, and wait for
another ATTN before executing the next command.
There are two considerations when using the CONT bit.
the INT bit is ignored if the CONT bit is set. This means
will only occur if no command is to follow, which is the way
want things to happen when executing a sequence of commands.
The
firs!.. is that
that
an interrupt
one would normally
Secondly, if the link address points to the beginning of this same instruc-
tion (pointing to itself) and the CONT bit is set, endless execution of the
instruction will occur. This could be useful. The way to stop execution would
be to change the opcode so that the CONT bit is zero. The opcode could be
changed to a NOP, or merely the same opcode wi th the CONT bi t zeroed. Ei ther
the system CPU or the MPX could change the opcode. DO NOT try to change the
link address on the fly! .,
Bit 5 is unused and is really a "don't care" bit, but agood practice would
be to always set this bit to zero.
STATUS INDICATION BYTE
This byte is used to "handshake" with the MPX when the use of a completion
interrupt is not desired, or they may be used in conjunction. This byte should
be set to zero before an ATTN is sent to the MPX. When the MPX is done
executing the command, it will set this byte to FF hex. In a non-interrupt
environment, this byte should be checked before another command is sent to the
MPX.
If the CONT bit is set in the command opcode, the status byte for that
particular command will NOT be set to FF hex. This means that in a sequence of
commands, only the status byte in the last command (the one with CONT = 0) will
be set to FF hex •
.
13

GENERAL PURPOSE PARAMETER BYTES 0 through 8
These bytes are used to send parameters to the MPX along with the command.
The
parameter(s) sent vary with the command. Only the block move com~ands use
all nine bytes, and they would contain the starting, ending and destination
addresses for the block move (3 bytes each). Sometimes only a few bytes are
used and sometimes none are used at all. The exact usage of these bytes is
detailed in each individual command description.
LINK ADDRESS BYTES
These three bytes are a pointer to the place at which the next command line
is resident in the system memory. When not executing multiple commands (CONT
bit = 0), this address would normally point to the beginning of the same
command. When executing a sequence of commands, this address would point to the
address of the next command.
The
address is stored low byte first and is a full 24 bit address.
The initial link address is 50 hex, but the NOP instruction may be used to
change the link address to any other system address.
Note that the link address is read only once and at the start of each
command, not at the end. This means that the command itself may modify the link
address, but it will only affect the following command (not the where the next
command will be fetched). The main system CPU should not modify the current
link address unless the MPX is not active.
RESULT 1 AND RESULT 2BYTES
"'-,
Sometimes it is desirable to have the MPX return parameters to the caller,
and that is the purpose of these two bytes. Only two of the built-in commands
return data to these locations, but user generated commands should use these
bytes for that purpose as well.
GENERAL NOTES
Commands are assumed to be resident on 16 byte boundaries ie: SOR, 60R,
180R, etc.
The only bytes in the command line that the MPX modifies are the status
indication and result bytes. All others are left intact.
14

COMMAND DESCRIPTIONS
HOP - No Operation
OPCODE BIT CODING:
Bit 0
Bit 7
CONT I INT
ooooo
Bit 0
1
PARAMETERS PASSED: None.
PARAMETERS RETURNED: None.
DESCRIPTION: This comma:J resets the MPX-l to its initial starting state. The
internal command table will be cleared (so any custom commands you have loaded
into RAM will now be ignored). The address where the MPX picks up its first
command line will be set to SOH. All interrupts will be masked and the inter-
rupt controller will be re-initialized.
SET MASK -Mask or Unmask interrupt inputs to MPX-l
OPCODE BIT CODING:
Bit 7
CONT lINT oo o o1
Bit 0
o
PARAMETERS PASSED: Mask Byte. Link Address.
PARAMETERS RETURNED: None.
DESCRIPTION:
lfhis command is used to mask or unmask interrupt inputs to the
MPX-l. The byte passed in Parameter Byte 0 is written to the mask register of
the 82S9A interrupt controller. If a bit in the mask byte is set to one, the
corresponding interrupt will be masked. Conversely, if a bit is zero, that
15

interrupt will be unmasked. Bit 0 of the mask byte corresponds to VIa. on the
bus, and Bit 7 corresponds to VI7* on the bus. This is the same as sending OCWl
to the interrupt controller (see the 8259A application note in the appendix of
this document for more information).
SENDEOI - SEND END-oF-INTERRUPT COMMAND TO INTERRUPT CONTROLLER
OPCODE BIT CODING:
Bit 7
Bit· 0
---------------------------------------------------------------
CONT lINT
oooo11
PARAMETERS PASSED: EOI Command Byte, Link Address.
PARAMETERS RETURNED: None.
DESCRIPTION: This command is used to send an End-of-Interrupt Command to the
8259A interrupt controller. It is also useful for rotating the interrupt prior-
ity levels. The byte to be sent to the 8259A Is passed in Parameter Byte O.
This is equivalent to sending OCW2 to the 8259~ For more information on what
this byte does to the 8259A, refer to the 8259A application note contained in
the appendix of this document.
READREG - READ INTERRUPT CONTROLLER REGISTERS
OPCODE BIT CODING:
Bit 7
CONT I INT
oo1o
Bit 0
o
PARAMETERS PASSED: Link Address.
PARAMETERS RETURNED: Contents of IS and IR registers in 8259A.
DESCRIPTION: This command is used to read the contents of the Interrupt Request
(IR) and In Service (IS) registers in the 8259~ It returns the contents of the
lR register in the Result 1Byte location and the contents of the IS register in
the Result 2 Byte location. For more information on the meaning of the IS and
lR registers, see the 8259A application note in the appendix of this document.
SETRESPOBSE -SET INTERRUPT RESPONSE BYTE
OPCODE BIT CODING:
Bit 7
CONT I INT. Io o o1o
Bit 0
1
PARAMETERS PASSED: Response Byte, Link Address.
PARAMETERS RETURNED: None.
DESCRIPTION: The MPX-l is capable of putting an 8 bit value on the systam data
16

bus during system interrupt acknowledge cycles. The value is called the inter-
rupt response byte and may be set as desired with this command. Note that this
response will only appear on the bus if this feature in enabled by a hardware
switch. See the hardware section of this document for more information.
SIZE -INDICATE WHETHER 4K OR 16K MPX-l
OPCODE BIT CODING:
Bit 7
CONT I INT
ooo11
Bit 0
a
PARAMETERS PASSED: Link Address.
PARAMETERS RETURNED: Size indication.
DESCRIPTION: This command is used by the system to determine the aollount of
memory installed in this particular MPX-l. The Result IByte is set to 00 hex
if this is a 4K MPX-I and is set to FFH if this is a 16K MPX-l.
LOADRAM - LOAD MPX LOCAL RAM FROM SYSTEM RAIl
OPCODE BIT CODING:
Bit 7
CaNT lINT o o o11
Bit 0
1
PARAMETERS PASSED: Starting Address in System RAM (3 bytes)
Ending~Address in System RAM (3 bytes)
Destination Address in Local RAM (2 bytes)
Link Address
PARAMETERS RETURNED: None.
DESCRIPTION: This command is used to load the MPX local RAM from system RAM.
Three addresses are passed to the MPX: The starting address of the block to be
loaded, its ending address, and the starting address of the place to put it in
local RAM. The starting and ending addresses are 3 bytes long and the destina-
tion address is only two bytes long. All addresses are stored low byte first
and the starting address is at Parameter Bytes 0-2, the ending address is at
Parameter Bytes 3-5, and the destination address is at bytes 6-7.
EXRAH - EXECUTE A PIWGRAM IN LOCAL RAIl
OPCODE BIT CODING:
Bit 7
CaNT I INT
oa
17
1o o
Bit 0
o

PARAMETERS PASSED: Execution Address (2 bytes). Link Address.
PARAMETERS RETURNED: None.
DESCRIPTION: This command is used to cause a routine stored in local RAM on the
MPX-1 to be executed. A "call" is made to the routine, so when it has finished
executing a RETURN instruction will pass control back to the interpreter
(assuming a clean stack). The starting address of the routine is two bytes long
and is stored low byte first at Parameter Bytes 0and 1.
BLKMOV - HOVE A BLOCK OF RAM ON THE SYSTEM BUS
OPCODE BIT CODING:
Bit 7
CONT I INT
o o 1oo
Bit 0
1
---------------------------------------------------------------
PARAMETERS PASSED: Starting Address in System RAM (3 bytes).
Ending Address in System RAM (3 bytes).
Destination Address in System RAM (3 bytes).
Link Address.
PARAMETERS RETURNED: None.
DESCRIPTION:
This command is used to move a block of RAM (of any size) on the
S-100 bus. Three addresses are passed: The starting address of the block to be
moved, its ending address and the destination address of where it's being moved
to. Each address is three by~es long and is stored low byte first. The
starting address should be at Parameter Bytes 0-2, the ending address should be
at Parameter Bytes 3-5 and the destination address should be at Parameter Bytes
6-8. Note that this command is useful for putting code in extended pages that
normal 8 bit processors cannot talk to without a lot of effort.
FASTMOV - MOVE A BLOCK OF RAM ON THE SYSTEM BUS -FAST
OPCODE BIT CODING:
Bit 7
Bit 0
---------------------------------------------------------------
CONT I INT oo1o1o
PARAMETERS PASSED: Starting Address in System RAM (3 bytes).
Ending Address in System RAM (3 bytes).
Destination Address in System RAM (3 bytes).
i:ink Address.
PARAMETERS RETURNED: None.
DESCRIPTION: This command is almost the same as above, except that all blocks
must be a multiple of 256 bytes, and begin on 256 byte boundaries. This allows
18

the transfer to occur at amuch higher rate. Three addresses are passed: The
starting address of the block to be moved. its ending address and the destina-
tion address of where it's being moved to. Each address is three bytes long and
is stored low byte first. The starting address should be at Parameter Bytes 0-
2, the ending address should be at Parameter Bytes 3-5 and the destination
address should be at Parameter Bytes 6-8. Note that even though each aadress is
three bytes long, the low byte is assumed to be 00 hex.
RESERVED - DO NOT USE
OPCODE BIT CODING:
Bit 7
CONT I INT
oo11 1
Bit 0
1
Note: This opcode is reserved and should not be used by custom command
routines. At tempts to call this opcode will be translated internally to NOP
opcodes (link address will still be valid. however). The reason this opcode is
reserved is because its jump table address is used by the ATTN routine.
&lInn", 'PUll' unv I'nnll
J.oca~l.ons are l.nl.[:l.al.l.zeo [:0 pol.n[: [:0 a X-OULl.Tlt:! l;i:l.J • .Lt:U UU."U"l.L. Wll.L"ll .Ll:> llULll.L'-'6
more than a RET instruction. This is where all interrupts and all unused
commands go to. (until you change the table). The next thing that happens is to
patch the command jump table with the addresses of the ten command routines that
are supplied in the ROM. Next the stack pointer is initialized leaving about 77
bytes free for stack usage. That should be more than enough, the routines in
the ROM never get more than about 6 bytes deep •
.
Next the initial link address is set up to point address SOH and then the
ATTN interrupt (RST 7.5) is armed and the MPX sits quietly waiting for an ATTN.
19

ATTN RESPONSE
When an ATTN occurs. first the interrupt output is cleared, the ATTN inter-
rupt input is masked and the last link address is copied into CURRENT. Then 16
bytes are read from the system memory (pointed to by CURRENT) into a buffer
called CMNDBUF. The opcode byte is read from the buffer and decoded. A call is
then made to the address pointed to by the lower 5 bits of the opcode. The
opcode is first checked to see if it is the same as the ATTN jump address. If
it is. a NOP command is substituted instead. Control has now been transfered to
the actual command routine. When the command is done executing, all it need do
is a RET instruction to get back to the main interpreter loop.
When a command is finished. the program branches to CHECK. This routine
checks to see if the CONT bit was set in that opcode. If it was, a jump occurs
to the ATTN routine and the next command is executed. If the CONT bit is not
set, the INT bit is checked. If it is set, the status byte is set to FFH and
the SOD interrupt output is set and the MPX then waits for the next ATTN. If
the INT bit is not set, the status byte is set to FFH and the MPX waits for the
next ATTN.
GENERAL PURPOSE SUBROUTINES

LISTING OF STANDARD SOFTWARE SUPPLIED WITH THE MPX-l
jMPX PROM VERSION 1.0
jWRITT£N 1-7-82 BY ~~RK GARETZ
jCDPYRIGHT 1982 BY GODBOUT ELECTRONICS
Multiple command linking bug fixed-Ilo
jVERSlON
1.1
jEQUATES
8000
INTCLA EQU
8001
1NTCLB
EQU
8004 ...
m1ALO EQU
8005 = DMAH1
EQU
8007
INTRSP EQU
OOCO ...
WINDOW
EQU
0000 =
CMNDTBL EQU
0080 ...
1NTTBL EQU
OOAD
CMNDBUF EQU
00A2
STRTAD EQU
00A5
ENDAD EQU
00A8
DESTAD EQU
OOAB
LlNKAD
EQU
OOAE ...
RESULT1 EQU
OOAF ...
RESULT2 EQU
OOBO
...
CURRENT EQU
DOFF
STACK EQU
0100 ...
BUFFER
EQU
0030
S1M
EQU
8000H
8001H
8004H
8005H
8007H
oeOH
OOOOH
0080H
OOAOH
CMNDBUF+2
STRTAD+3
ENDAD+3
DESTAD+3
LlNKAD+3
RESULT 1+1
OOBOH
OOFFH
0100H
30H
jInterrupt Controller
jDHA Addr. Bits A8-15
jDMA Addr. Bits A16-23
jlnterrupt Response Byte Reg.
jExternal Window
jCommand Jump Table
jInterrupt Response Jump Table
jTemporary Command Buffer
jStarting Address, 3 bytes
jEnding Address, 3 bytes
jDestination Address, 3 bytes
jLink Address, 3 bytes
jResult byte 1
;Result byte 2
;Current Command Address, 3 bytes
;Stack Space
;Fast Block Move Buffer
;S1M INSTRUCTION
;Beginning of Code
4000
OR'G 4000H
4000 C33140
JMP
START
;3
Init Bytes
4003 564552532E
DB
'VERSo
1.0'
400e 434F505952
DB 'COPYRIGHT
1982
BY GODBOUT ELECTRONICS'
4031 3E9E
START: MVI A,9EH ;ICW1
4033 320080
STA INTCLA
4036 3EOO MVI
A,O
jICW2
4038 320180
STA 1NTCLB
403B 320180 STA INTCLB
jICW3 too
403E 3EFF
MVI A,OFFH
jOCWI Mask
all interrupts
4040 320180 STA
INTCLB
jDone with
interrupt controllers
jTbe following code initializes the Command Jump Table and
;Interrupt Jump Table. Unused entries jump to DU}lliY
;Note: all entries are first initialized to DUMMY, then
jpatched for commands and ATTN.
4043 210000
4046 117B42
4049 0100e3
404C 7D
LXI
LXI
LOOPl: LXI
!'lOV
H,CMNDTBL
D,DUHMY
B.OC300H
A,L
21
jD gets DU}lliY addr.
jJUMP and a NOP