Lexicon MPX - ADDENDUM REV 1 User manual

I
MPX·1™
TECHNICAL MANUAL
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TABLE OF CONTENTS
WARNING • • • • • • • • • . • • • • • • • • • • • • • 5
About MPX-l •••••••••••••••••••• 5
Technical overview • • • • • • • • • • 5
How to use the MPX-l • • •• 6
MPX-l
block diagram ••••••• •••• 6
Local address map •••• 7
Accessing memory on the bus •••• 7
Accessing I/O ports on the bus ••••• •••• 8
Getting the MPX-l attention 8
Getting the main system CPU's attention •••• 8
Interrupt acknowledge response on the bus • • •• 9
Hardware switch setting and jumper options • • • • 9
Switch settings ••••• ••••• 9
Switch 1 - ATTN port address select •••••• 9
Standard ATTN port address selection •9
Swi tch 2••••••• •• ••• • •••• 9
Interrupt "CALL" jumpers •••••••••••• 10
Selecting and using 4K or 16K RAM chips • • • • 10
Using 2147 4K x 1 type RAM chips •10
Using 2167 16K x 1 type RAM chips •••• 11
Configuring the MPX-l for different size EPROMS •• •••• 11
Using a2716 or 2732 EPROM •••••••••••••••• 11
Using a2764 EPROM •••••••••• 11
Standard software supplied with MPX-l • 12
Basic command structure and protocol • • • • • • 12
Opcode
byte ••••••••••••• • • •• 12
Status indication-''byte ••••• •• ••••• •13
General purpose parameter bytes 0 through 8 • • 14
Link address bytes • • • • • • • • • 14
Result 1 and result 2 bytes ••••••••••••14
General notes • • •• •••••• • • 14
Command descriptions •••• •••••••••• • 15
NOP - no operation •••• •••• 15
RESET - reset the MPX-l •••••• 15
SET MASK -mask or unmask interrupt inputs to MPX-l 15
SENDDEOI - send end-of-interrupt command
to interrupt controller ••••••
READREG - read interrupt controller registers
SETRESPONSE - set interrupt response byte
SIZE - indicate whether 4K or 16K MPX-l
LOADRAM - load MPX local RAM from system RAM
EXRAM - execute a program in local RAM •
BLKMOV - move block of RAM of system bus ••••
FASTMOV - move block of RAM on system bus - fast •
RESERV&p - opcode •••••••••••••••
3

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-------------------------- DISCLAIMER --------------------------
Godbout Electronics makes no representations or warranties with
respect to the contents hereof and specifically disclaims any
implied warranties of merchantability or fitness for any
particular purpose. Further, Godbout Electronics reserves the
right to revise this publication and to makes any changes from
time to time in the content hereof without obligation of Godbout
Electronics to notify any person of such revision or changes.
-------------~---------------------------------------- ---------
This document was proofread with the aid
of SpellGuard T M from ISA, Menlo Park, CA.
4

FIRST - A WORD OR TWO OF WARNING!
This manual is intended to guide the sophisticated systems integrator or
OEM through the hardware features of the MPX-l. This manual is not intended for
novice or inexperienced users. If you are an end-user who has purchased an MPX-
t:ne J.nt:errupt: response 1.S nanuJ.eu oy LIlt= UU-UU<:lJ.U .LLlLCL L up'" ... VLl ... LV ............ ~ •• - -~ -,
taking up no processing time on the bus.
When needed, the MPX-1 can access any system resource on the bus. This
means that it can talk to any I/O port or memory location on the bus. It does
this by requesting the bus from the permanent master on a cycle-by-cycle basis.
This request/grant procedure is fully arbitrated to 16 levels as provided for by
the IEEE 696/5-100 bus standard. This allows up to 16 such devices to exist in
a system at any given time. Multiple MPX-ls could even be used.
The uses of the MPX-l are vast. Obvious uses would include terminal inter-
rupt handlers, print spoolers, task allocation and management, and resource
control. A unique feature of the MPX-l allows it to load execution code from
the system memory so that the MPX-l's function can be altered dynamically.
5

HOW TO USE THE HPX-l
A simplified block diagram of the MPX-1 appears in Figure 1. In the
following discussions, it may be useful to refer to the block diagram.
J - - _ •• z -t._~ ... A_,H,.t-\7 n .... rview of how the MPX-1 works: When the on-
I/O accesses, the on-boara .1ogl.C ~a~t::t> Io'G" '" ...... ~ .. __ •••• __ ~ •
the actual running of the bus cycle. The 8085 will "stall" until the operation
is completed allowing program operation to continue.
Sounds simple, doesn't it? Well, it is. The following sections discuss
the above overview in greater detail. First is a local address ~ap showing
where everything lives on the MPX-l.
Figure 1. MPX-l BLOCK DIAGRAM -.,
ADDRESS, STATUS
& CONTROL BUSES
DATA BUSES
DMA HANDSHAKE
5-100
BUS
VECTORED INTERRUPTS
CONTROL INPUTS
INTERRUPT OUTPUT
-i I
8-100
LOCAL
BUS ROM
INTERFACE
AND 8085
DMA LOGIC
CPU
LOCAL
RAM
INTERRUPT
CONTR.
RST.
7.5 SOD
t ATTN
PORT
6

LOCAL ADDRESS MAP
FROM
TO
SIZE
FUNCTION
NOT~S
------------------------------------------------------------------
0000 3FFF 4-16K
RAM
1,4
4000
SFFF 2-8K
EPROM
1,2,5
8000 8001 28259A
Registers
8002 1
Set
Interrupts Latch
2
8004 1
DMA
Address Bits 8-15
3
8005 1
DMA Address Bits
16-23 3
8007 1
Interrupt Response Byte 3
COOO
FFFF
16K
External
Window 6
All I/O Ports 256 External
Window 6
Notes: 1. RAM and EPROM exchange locations for power-on-jump.
2. Read Only.
3. Write Only.
4. 4K or 16K depending on chips used.
5. 2K fo~ 2716, 4K for 2732, 8K for 2764.
6. Lower 8 address bits (AO-7) pass through.
ACCESSING MEMORY ON THE BUS
An access to memory that resides on the 5-100 Bus will be performed if the
CPU makes an access to th~ range noted as the external window in the address map
above (addresses COOO to FFFF). The low order 8 bits of the address (AO-7) will
be taken from the CPU's address lines directly, while the high order 16 bits
(A8-23) will come from the address that has been previously written to the DMA
address registers. So the procedure for accessing memory on the bus would be:
1. Write desired AB-15 bits to memory location B004.
2.
Write desired A16-23 bits to memory location BOOS.
3. Perform amemory reference to COXX to FOXX, where XX
represents the low order B bits (AO-7) of the desired address.
If the memory reference to the external window is a read operation, then a
memory
read will occur on the bus. If the memory reference is write operation,
data will be written to the memory on the bus. Note that Ml cycles may also be
executed on the bus meaning that the MPX-1 may actually execute a small amount
of code (less than 256 bytes) directly from the bus.
Note that the high order byte of the external window is insignificant. Any
address in the range COOO to FFFF will be treated identically. For example,
C083, BD83, A9B3, and FFB3 would all access the same external memory location -
XXXX83 , where XXXX are the two bytes from the DMA address registers.
7

ACCESSING I/O PORTS ON THE BUS
All of the "I/O Ports" local to the MPX-l are "memory mapped". This means
they are decoded in the memory address space rather than in the I/O space. This
leaves all 256 I/O addresses free. Any input or output cycle performed by the
CPU will cause a corresponding cycle to be executed on the S-lOO Bus. Since the
lower 8 bits of the DMA Address pass through from the actual lower 8 address
bits from the CPU, the port address specified in the I/O instruction will be the
one accessed on the bus.
The high order 8 bits of the I/O access will come from the DMA address
register as in a memory reference. This allows the port aduress to be
"mirrored" in A8-lS as early S-lOO (8080) processors did, or thit> byte may be
loaded with different data to emulate Z-80 I/O modes (the 2-8U passes the
accumulator contents on A8-l5). This also allows the MPX-1 to emulate the
current generation of 16 bit processors such as the CPU 8085/88, CPU 86/87 and
the CPU 68K, which can put out 16 bit I/O addresses.
If an input instruction is executed, then an input cycle will be performed
on the S-lOO Bus. If an output instruction is executed, then an output cycle
will be performed on the bus.
GE'ITING THE HPX-l's ATTENTION
In any system it will be necessary for the main CPU in the sydcem to get
the attention of the MPX-l. This can be for initial start-up of the MPX-l, or
to "interrupt" its current task to be given another. This is done through a
mechanism called the ATTN port. This port is on the S-100 Bus and its address
is selec ted by swi tch S1. When the system CPU executes an output to the ATTN
port, a RST 7.5 will be generated to the on-board 8085. Note that no data is
accepted by the MPX-l. .~
GET'l'ING THE MAIN SYSTEM CPIrS ATTENTION
The MPX-1 may need to get the attention of the system CPU to tell it that a
task is complete, a buffer is nearing full, or many other reasons. The MPX-1
may
signal the main CPU by causing an interrupt on the bus. This interrupt may
occur on the INT*, NMI* or any of the vectored interrupt lines. A hardware
jumper is used to select which of the ten possible lines are used.
Two methods of causing this interrupt are available, again selected by a
jumper. The first type uses the Serial Output Data (SOD) line from the 8085 to
cause the interrupt. The state of this line is set and reSet by the Set Inter-
rupt Mask (SIM) instruction. The state of the interrupt request must be reset
in software.
The second method uses a one bit latch that is set by performing a read
from address 8002 (set Interrupt Latch in the address map above). This latch is
automatically reset by the occurrence of an interrupt acknowledge cycle.
Note that if one of the vectored interrupt lines is selected to cause the
system interrupt, the corresponding interrupt input to the 8259A should be
masked, unless you want the MPX-l to interrupt itself.
8

INTERRUPT ACKNOWLEDGE RESPONSE ON THE BUS
The MPX-1 may provide a single byte of data during bus interrupt acknow-
ledge cycles. This response must be enabled by a switch. The data to be passed
during interrupt acknowledge cycles is written to the latch a~ address B007
~ . - -~--- - ~ n - - -~_"~ U" .. a ~ nr hp ;In d~r"",e-",s-",s---"m ... a.,.p,---,a"-,b,,-,o,-,v,-,e-1)~' _
PADDLE
IF ADDRESS
BIT
1······ · ·
A7
2·· ·
A6
3
A5
"ON"
"a ..
4··· · ····
A4
5·· ·
A3
6
... ,.
A2
"OFF"
"1"
7· · ·· · ···
A1
8· · •·
AO
STANDARD ATTN PORT ADDRESS SELECTION
The COlRpuPro "standard" port address for MPX ATTN calls is Fl hex. To set
the MPX-1 to respond to ATTN calls on port F1 hex. set Sl as follows: Paddles 1-
4 and paddle 8 should be OFF. Paddles 5-7 should ON.
S2
PADDLE if
FUNCTION
1.-.· · "ON"
enables EPROM wait state •
2·
"ON"
enables
interrupt
response byte.
3
DMA
priority address
3
4··
DMA priority
address 2
"ON '"'
"0"
·
5·
DMA priority
address 1
6
DMA priority
address a
"OFF"
'"'
"1"
7··· "ON"
enables
SLAVE CLR*
to
reset MPX-l.
8...··
not used
9

INTElUlUPT "CALL" JUMPERS
The MPX-1 "calls" the system CPU by causing an interrupt on the bU:;l. There
are ten possible interrupt lines that the MPX-1 may assert. They are: INT*,
NMI* or any of the eight vectored interrupt lines (VIO*-VI7*). There are also
two methods by which the MPX-1 can assert the interrupt request - the SOD line
or by setting a hardware latch (described above in the section entitled "Getting
the Main System CPU's Attention").
The interrupt line asserted and the method of asserting it are selected by
Jumpers J1-10. These jumpers are implemented with push-on shorting plugs and
pins soldered into the board. Each jumper has three pins labeled A, B andC.
The "A" pin of each jumper is connected to the SOD interrupt source. The "c"
pin of each jumper is connected to the interrupt response latch. The "B" pin of
each jumper is connected to an interrupt line on the bus according to the chart
below:
JUMPER
/1 LEGEND MARKING
"B"
POSITION CONNECTION
17VI7*
2 6 VI6*
3 5 VI5*
4 4 VI4*
53VI3*
6 2 VI2*
71
VIl*
8aVIa*
9
NMI NMI*
10
INT
INT*
EXAMPLE: To connect the MPX-1 interrupt request output to the INT* line on the
bus with the interrupt source' from the SOD line, a shorting plug should be
installed at J1a from the "A" to "B" position (left of center).
EXAMPLE: To connect the MPX-1 interrupt request output to the VI3* line on the
bus with the interrupt source from the interrupt latch, a shorting plug should
be installed at J5 from the "B" to "c" position (right of center).
NOTE: The software supplied with the MPX-1 assumes the use of the SOD interrupt
mode, so if you wish to use the MPX in an interrupt driven mode with the
standard software, use only the SOD interrupt source.
SELECTING AND USING 4K OR 16K RAM. CHIPS
The MPX-1 can use either 2147 4Kxl RAM chips, or 2167 16Kx1 RAM chips. The
MPX-1 should have come from the factory already jumpered correctly for the type
of chip that was originally ordered with the board. Should it become necessary
to change these jumpers once the board is in the field, here is how different
RAMs are jumpered and inserted:
USING 2147 4Kxl TYPE BAM CHIPS
To use 2147 type RAM chips, jumpers J11 through J17 should be installed and
J18 should be open. Jl1 through J17 are located in-between the RAM array (U10-
10

17), and J18 is located at the right-hand side of the RAM array.. The RAM chips
come in 18 pin packs, but the sockets are 20 pin to accomodate 2167 type RAMs.
When using 2147 type RAMs, plug them in so that the chips are in the bottom-most
part of the socket, that is pins 1and 20 are blank.
USING 2167 16lCx1 TYPE RAM CHIPS
To use 2167 type RAM chips, jumper J18 should be installed and jumpers Jll-
17 should be open. Jumper J18 is located at the far right-hand side of the Rfu~
array and jumpers Jll-17 are located in-between the RAM chips.
CONFIGURING THE MPX-l FOR DIFFERENT SIZE EPROMS
The MPX-1 has a JEDEC 28 pin socket for the EPROM (U27). With the use of
one jumper, this socket can accomodate a2716, 2732 or a2764 type EPROM. This
gives 2K, 4K or 8K of storage, respectively.
USING A2716 or 2732 EPROM
To use a 2716 or 2732 type EPROM, jumper J19 should have a shorting plug
installed connecting pins "A" and "c" (left of center). J19 is located just
above U26. The 2716 or 2732 should be installed at location U27 such that it
uses the bottom-most pins of the socket, that is pins 1,2,27 and 28 are left
blank.
USING A2764 EPROM
To use a2764 type EPROM, jumper J19 should have a shorting plug installed
connecting pins "c" and "B" (right of center). J19 is located just above U26.
The 2764
should be installed at location U27, and all the pins of the socket are
used.
11