Linear Technology Dust Networks Eterna LTP5901 Quick setup guide

Dust Networks
Eterna LTP5901 / LTP5902 Integration Guide

2 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
Table of Contents
About This Guide .................................................................................................................... 3
Audience ....................................................................................................................................................................3
Related Documents....................................................................................................................................................3
Conventions and Terminology....................................................................................................................................3
Revision History.........................................................................................................................................................3
1Design Guidelines...............................................................................................................4
Schematic Design ......................................................................................................................................................4
Manager Variations –IPRA, -IPRB, -IPRC ..............................................................................................................4
PCB Layout ................................................................................................................................................................8
Eterna LTP5901 Recommended Land Pattern (Chip Antenna)...............................................................................9
Eterna LTP5902 Recommended Land Pattern (MMCX) .......................................................................................11
Antenna ESD Considerations....................................................................................................................................13
Supply Design..........................................................................................................................................................13
Voltage Supervision and Reset.................................................................................................................................13
2Manufacturing Guidelines ....................................................................................................14
Reflow......................................................................................................................................................................14
Solder Paste/Cleaning ..............................................................................................................................................14
Packaging ................................................................................................................................................................14
List of Figures
Figure 1 Eterna Example Schematic................................................................................ 4
Figure 2 Eterna Extended Memory Example Schematic (page 1 of 2) ............................................. 6
Figure 3 Eterna Extended Memory Example Schematic (page 2 of 2) ............................................. 7
Figure 4 LTP5901 Land Pattern (Chip Antenna) ..................................................................10
Figure 5 LTP5902 Land Pattern (MMCX) .........................................................................12
List of Tables
Table 1 Programming Header ..................................................................................... 4
Table 2 External Memory Reference Bill of Materials ............................................................. 7

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 3
About This Guide
This document provides the design guidelines essential for incorporating either an Eterna
LTP5901 or LTP5902 module. The document covers design, layout, EMI, and some
manufacturing considerations.
Audience
This document is intended for system developers, hardware designers, and layout engineers.
Related Documents
The following related documents are available:
Eterna Serial Programmer Guide
ETERNA2 User’s Guide
Conventions and Terminology
This guide uses the following text conventions:
•Computer type indicates information that you enter, such as a URL.
•Bold type indicates buttons, fields, and menu commands.
•
Italic type is used to introduce a new term.
•Note: Notes provide more detailed information about concepts.
•Caution: Cautions advise about actions that might result in loss of data.
•Warning: Warnings advise about actions that might cause physical harm to the hardware
or your person.
Revision History
Revision Date Description
040-0119 rev 1 6/7/2012 Initial version
040-0119 rev 2 7/18/2012 Updated references
040-0119 rev 3 8/20/2012 Corrected keep out for LTP5901 land pattern
040-0119 rev 4 4/2/2013 Added support documentation for external SRAM.
040-0119 rev 5 5/8/2013 Added hyper link to programmer.
040-0119 rev 6 10/24/2013 Update SDRAM schematics and BOM

4 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
1 Design Guidelines
Schematic Design
The LTP5901 and LTP5902 require little external circuitry, as the devices references,
decoupling and power supply filtering are integrated. The LTP5901 and LTP5902 have been
modularly certified for operation in many geographies – see the ETERNA2 User’s Guide for the
currently supported geographies and regulatory related specifications. If further certifications
may be necessary, it is essential to provide a method to deliver specific radio test APIs via the
API UART interface during testing. Test connections should be included in the schematic if the
product does not provide a natural means of delivering the API calls.
During the design phase, it is recommended to include a header to allow for updating of
Eterna’s software.
The schematic shown in Figure 1 includes the signal connections necessary for the
programming header. The part number for the header is provided in Table 1.
Figure 1
Table 1
Eterna Example Schematic
Programming Header
Reference Value Vendor Vendor P/N
J3 5x2 header Molex 87831-1020
Manager Variations –IPRA, -IPRB, -IPRC
Without the addition of external SRAM, Eterna IP managers are limited to supporting networks
of 32 or fewer motes. Eternal memory may be added to Eterna IP Manager products to:
a. manage networks of up to 100 motes – and / or –
b. increase throughput of the manager from 24 to 36 packets per second
The LTP5901/LTP5902-IPRA is limited to supporting a maximum of 32 motes and a maximum
throughput of 24 packets per second. The LTP5901/LTP5902-IPRA does not support the use
of external RAM.
The LTP5901/LTP5902-IPRC natively supports up to 32 motes with a maximum throughput of
36 packets per second. A license key can be purchased to raise the limit of the
LTP5901/LTP5902-IPRC maximum network size to 100 motes. Contact your Linear Sales

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 5
representative for details on how to order license key certificates. The certificate contains a
product key and instructions for requesting the generation of a license key, which typically
takes one to two business days to receive a license key. License keys are entered via either the
set config command documented in SmartMesh IP Manager CLI Guide or the setLicense
command documented in the SmartMesh IP Manager API Guide. The LTP5901/LTP5902-
IPRC requires the use of external RAM.
The LTC5800-IPRB supports networks of up to 100 motes and has a maximum throughput of
36 packets per second The LTP5901/LTP5902-IPRB requires the use of external RAM.
The schematic shown in Figure 2 and Figure 3 includes all the external connections and
components necessary to add the external RAM. The connections differ from the LTP5901-
IPRA as follows:
1) CLI access is on UARTC1, not UARTC0
2) Mapping of external bus signals to Eterna’s general purpose function pins
3) The Memory, latches and pulse generators shown in Figure 3
The reference Bill of Materials (BOM) for the addition components needed for the external
memory interface is shown in Table 2.

6 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
eb_data_0
DP4
eb_io_le0 eb_data_1
R2
100k
0201
IPCS_MISO IPCS_MOSI IPCS_SCK
RADIO_INHIBIT
TIMEn
UART_TX
UART_TX_CTSn
UART_TX_RTSn
UART_RX
UART_RX_CTSn
UART_RX_RTSn
VSUPPLY
eb_io_le1
eb_io_oen
eb_io_wen
R3
100k
NoStuff
0201
UARTC1_RX
UARTC1_TX
eb_io_cs0n
eb_data_5
eb_data_2
eb_data_3
eb_addr_0
eb_addr_1
IPCS_SSn
eb_io_le2
VSUPPLY
eb_data_4
eb_data_6
eb_data_7
TCK
TMS
M1
LPT5901IPC-IPRB
290-0007
ATL_PN=290-0003
RADIO_INHIBIT 64
RESERVED
2
GPIO17
4
GPIO18
5
GPIO19
6
RESERVED
12 AI_0
10 AI_1
8
AI_3
9AI_2
7
RESETn
15
TDI
16
TDO
17
TMS
18
TCK
19
DP4
21
RESERVED
22
RESERVED
23
RESERVED
24
EB_DATA_7
25
EB_DATA_6
26
EB_DATA_4
27
EB_DATA_0
28
UARTC0_TX/EB_IO_LE0
31
UARTC0_RX/EB_DATA_1
32
EB_IO_LE2 38
IPCS_MISO
33
EB_ADDR_1 40
IPCS_MOSI
35
EB_ADDR_0 41
IPCS_SCK
36
IPCS_SSn 39
EB_DATA_3 43
EB_DATA_2 44
EB_DATA_5 45
EB_IO_CS0n 46
RESERVED/UARTC1_TX 47
RESERVED/UARTC1_RX 48
EB_IO_WEn 49
EB_IO_OEn 50
FLASH_P_ENn/EB_IO_LE1 51
RESERVED 54
VSUPPLY 55
UART_RX_RTSn 57
UART_RX_CTSn 58
UART_RX 59
UART_TX_RTSn 60
UART_TX_CTSn 61
UART_TX 62
TIMEn 63
GND 66 GND
1
NC 65
NC
3
GND
11 GND 56
NC
13
NC
14
GND
20
NC 52
NC 53
TDO
TDI
RESETn
GND 42
GND
30 NC
29
GND 37
GND
34
P1 Target SPI
HDR_2X5_2MM
2
4
6
8
10
1
3
5
7
9UARTC1_RXUARTC1_TX
IPCS_SSn FLASH_P_ENn
VSUPPLY
IPCS_MISO
IPCS_SCK RESETn IPCS_MOSI R1
1k
0201
eb_io_le1
Eterna Extended Memory Example Schematic (page 1 of 2)Figure 2

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 7
Place R27, C5, and R29, C7,
close to U4 and U5,
respectively
eb_data_7
VSUPPLY
eb_data_0
eb_data_4
eb_data_6
eb_data_7
eb_io_cs0n eb_io_cs0n
eb_io_le1
eb_addr_0
eb_io_le2
eb_io_le1
C2
0.1uF
0402
eb_addr_1
eb_addr_0
eb_data_3
eb_data_2
eb_data_5
eb_data_0
eb_addr_1 eb_data_1
eb_io_le2
eb_data_4
eb_data_3
eb_data_2
eb_data_1
eb_data_6
eb_data_5
Note:
Cypress STSOP-32 pin 1
is at pin 9, or A17
C3
0.1uF
0402
eb_addr_9
eb_addr_11 eb_addr_10
eb_io_le0
eb_io_cs0n
eb_io_le0 eb_io_oen
eb_addr_13
eb_io_le1_p
U4
74AUP1G58
SOT886
3
21
4
5
6
eb_io_le1
U3
74AHC573
DHVQFN20
OEn
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
GND
10 LE 11
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
VCC 20
GND
21
U1
74AHC573
DHVQFN20
OEn
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
GND
10 LE 11
Q7 12
Q6 13
Q5 14
Q4 15
Q3 16
Q2 17
Q1 18
Q0 19
VCC 20
GND
21
VSUPPLY_M
eb_addr_17
eb_addr_11
eb_addr_10
eb_addr_12
eb_addr_13
eb_io_le1_p
eb_addr_14
eb_addr_15
eb_addr_16
VSUPPLY_M
eb_data_6
eb_data_7
eb_io_le2_p
eb_addr_3
eb_data_4
eb_addr_2
eb_data_5
eb_addr_5
eb_data_2 eb_addr_4
eb_data_3 eb_addr_6
eb_addr_7
eb_data_1
eb_addr_9
eb_addr_8
eb_addr_7
eb_data_0
eb_data_1
eb_data_0 VSUPPLY_M
eb_data_6
eb_data_5
eb_data_4
eb_data_3
eb_data_2
R12 0
0201
eb_data_7
eb_io_le2_p
U5
74AUP1G58
SOT886
3
21
4
5
6
VSUPPLY_M
eb_io_wen eb_data_5
eb_data_4
eb_addr_6
eb_data_3
eb_data_7
eb_data_6
Pulse Generator Circuits
eb_addr_5
eb_addr_4
eb_io_le2
VSUPPLY_M
R13 0
0201
eb_data_1
eb_data_0
eb_addr_16
eb_addr_14
eb_addr_12
R15 0
0201
eb_data_2
eb_addr_15
U2
CY62138FV30LL-45ZAXI
STSOP32
A0 20
A1 19
A2 18
A3 17 A4
16
CEn 30
IO0 21
IO1 22
VCC
8
IO2 23
IO3 25
WEn
5
A5
15 A6
14 A7
13
A8
3A9
2A10 31
A11
1
A12
12
A13
4
A14
11
IO4 26
IO5 27
VSS 24
IO6 28
IO7 29
OEn 32
A15
7
A16
10 A17
9
A18
6
eb_addr_17
eb_addr_1
eb_addr_0
eb_addr_8
eb_addr_3
eb_addr_2
C4
0.1uF
0402
C6
0.1uF
0402
eb_io_oen
eb_io_wen
eb_io_oen eb_io_wen
R16 499
0201
R14 499
0201
25 mil traces for VSUPPLY_M
VSUPPLY_M
NoStuff R25 for 128KB
Place R26 and R28 close to U4 and U5,
respectively
R11
100k
0201
C5
30PF
0201
C1
0.1uF
0402
VSUPPLY_M
C7
30PF
0201
Figure 3
Table 2
Eterna Extended Memory Example Schematic (page 2 of 2)
Eterna’s External memory function has been tested with the BOM options shown in Table 2.
The RAM components shown have been selected for low power operation and their use will
result in an increase of a few μA of current consumption. For designs that are not energy
constrained, substitution of general purpose RAMs with equal or faster speed grades should
be possible. Substitution of the multi-function logic and octal latch components should be
done carefully to maintain the timing generated by the pulse generation circuits.
External Memory Reference Bill of Materials
Reference Value Vendor Vendor P/N
R12, R13,
R15
0 Panasonic ERJ-1GE0R00C

8 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
Reference Value Vendor Vendor P/N
R2, R3, R11 100 kOhm Panasonic ERJ-1GEJ104C
R14, R16 499 Ohm Vishay CRCW0201499RFKED
R1 1 kOhm Panasonic ERJ-1GEJ102C
R10 237 Ohm Vishay CRCW0402237RFKED
C5, C7 30 pF Murata GRM0335C1E300JD01
D
C1, C2, C3,
C4, C6
100 nF Murata GRM155R71C104KA88
D
U2 128K x 8-bit RAM Cypress CY62128EV30LL-
45ZAXI
U2 Alternate 128K x 8-bit RAM Renesas R1LV0108ESA-5SI#B0
U4, U5 Multifunction Logic NXP 74AUP1G58GM, 132
U1, U3 Octal Latch NXP 74AHC573BQ,115
P1 5x2 header Molex 87831-1020
M1 ETERNA Module (32-mote
network, chip antenna)
Linear LTP5901IPC-IPRC
M1 (alt.
application)
ETERNA Module (100-mote
network, chip antenna)
Linear LTP5901IPC-IPRB
M1 (alt.
application)
ETERNA Module (32-mote
network, MMCX connector)
Linear LTP5902IPC-IPRC
M1 (alt.
application)
ETERNA Module (100-mote
network, MMCX connector)
Linear LTP5902IPC-IPRB
PCB Layout
Eterna-based designs should adhere to the following layout-sensitive guidelines:
1. The Eterna modules include exposed test points, and pads on the bottom (mounting) side
of the PCB. Exposed metal should be avoided in the on the top surface of the mating PCB
in the area where the module will be mounted.
2. The LTP5901 includes a chip antenna with layout designed to work over 1 mm thick FR4,
as used in the LTP5902. It is recommended to maintain an opening free of FR4 and any
conductive material as far as practically possible to maximize the radio performance.
3. The LTP5902 includes a through hole mounted MMCX connector. A sufficient opening in
the mating PCB must be provided – see the LTP5902 recommended land pattern later in
this document for details.
4. Eterna’s radios can be sensitive to EMI generated by DC/DC converters. It is
recommended that such inductors are placed a minimum of 2 inches from the radio and
antenna or MMCX connector. If space constraints prevent this degree of separation,
inductor selection can reduce the EMI generated. Different core materials and shapes will
change the size/ current and price/current relationship of an inductor. Toroid or shielded
pot cores in ferrite or permalloy materials are small and don’t radiate much energy but

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 9
generally cost more than powdered iron core inductors with similar electrical
characteristics.
Eterna LTP5901 Recommended Land Pattern (Chip Antenna)
Two common practices for defining land patterns are Non Solder Mask Defined, NSMD, and
Solder Mask Defined, SMD. Given the lead pitch of the LTP5901 and that tolerances for metal
etch are commonly more precise than solder mask deposition, it is recommended to use
NSMD land patterns. The solder mask opening should provide sufficient margin for
registration tolerance to avoid solder mask infringing on the pad, typically 60 to 75 um from
the edge of the pad and the solder mask.
Land Pattern dimensions are illustrated in Figure 4.

10 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
LTP5901 Land Pattern (Chip Antenna)Figure 4

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 11
Eterna LTP5902 Recommended Land Pattern (MMCX)
Two common practices for defining land patterns are Non Solder Mask Defined, NSMD, and
Solder Mask Defined, SMD. Given the lead pitch of the LTP5902 and that tolerances for metal
etch are commonly more precise than solder mask deposition, it is recommended to use
NSMD land patterns. The solder mask opening should provide sufficient margin for
registration tolerance to avoid solder mask infringing on the pad, typically 60 to 75 um from
the edge of the pad and the solder mask.
Land Pattern dimensions are illustrated in Figure 5.

12 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
LTP5902 Land Pattern (MMCX)Figure 5

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 13
Antenna ESD Considerations
The antenna pin is a particularly sensitive node for electro-static discharge (ESD) since it must
detect small, high-frequency signals. ESD damage may result in decreased receive or transmit
performance, or other system failure. Many applications for Eterna have an exposed antenna
that provides an entry point for ESD events. Proper consideration of antenna design as well as
antenna protection can substantially improve ESD robustness in harsh environments.
A radome (protective covering) made of highly resistive material may be used to prevent direct
contact with the antenna and/or dissipate charge. To avoid ESD events caused by triboelectric
charging generated by wind passing over the antenna in dry climates, the radome design
should consider bulk and surface resistivity as well as the size of the gap between the antenna
metal and the interior of the radome.
In general, DC-grounded antennas (the antenna and ground have a DC short) provide superior
protection to ESD events. DC-grounded antennas are highly recommended in harsh
environments. Additionally, a DC path-to-earth ground should be provided whenever possible
to help bleed off accumulated charge from the antenna as well as leak charge from the
radome.
While these general guidelines should improve robustness to ESD events, individual
implementations may have unique factors that complicate ESD protection.
Supply Design
Due to the heavy duty cycling, Eterna’s current consumption can change substantially over a
short period. This does not represent an issue for systems with supplies having low source
impedance (less than 5 Ohms). Regulated supplies, however, may have difficulty in the sudden
changes in current consumption (more than an order of magnitude in less than 1 μs), resulting
in transient voltages on the supply co-incident with the higher current consumption of the
radio operation. To ensure proper operation of the radio, a supply should be able to ramp from
250 μA to 10 mA in less than 1 μs without generating a transient greater than 200 mV. For
systems with regulated supplies, consultation with Linear Technology is strongly
recommended.
Eterna can be configured to support current limited supplies. Contact Linear Technology for
details.
Voltage Supervision and Reset
Eterna includes a power-on reset to safely set its own state during power up, and includes a
brown-out circuit that immediately halts flash erase cycles and interrupts flash write cycles at
the next 32-bit boundary, generating an interrupt to the CPU and maintaining state for the CPU
to correct should the power supply return to normal operating levels. In the interest of
avoiding flash corruption, it is not considered best practice to connect the RESETn lead to a
voltage supervisor or to asynchronously assert RESETn without previously suspending
network and flash activity.

14 ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE
2 Manufacturing Guidelines
Reflow
Given that Eterna modules are assembled using either “SAC305”, "Alpha OM-338 CSP" or "
SMIC ECO M705-GRN360" No Clear Solder Paste, careful adherence to J-STD-020 to avoid
reflowing the modules during the assembly process is necessary. The solder joint quality of
the “castellations” where they contact the mating PCB should meet IPC-A-610 Acceptability of
Electronic Assemblies, section 8.2.4 Castellated Terminations.
Solder Paste/Cleaning
“No Clean” soldering paste is strongly recommended, as it does not require cleaning following
the soldering process. Cleaning the populated modules is strongly discouraged due to the
potential issues that may result. Residuals under the module are difficult to remove with any
cleaning process. Cleaning with water can lead to capillary effects where water is absorbed
into the gap between the host board and the module, potentially resulting in combination with
soldering flux residuals leading to short circuits between neighboring pads. Cleaning with
alcohol or a similar organic solvent will likely flood soldering flux residuals under the shield,
which is not accessible for post-washing inspection. Ultrasonic cleaning could damage the
module permanently.
Packaging
The LTP5901 and LTP5902 modules are MSL3, however baking is required when parts are
packaged in individual ESD bags.

ETERNA LTP5901 AND LTP5902 INTEGRATION GUIDE 15
Trademarks
SmartMesh Industrial and Eterna are trademarks of Dust Networks, Inc. The Dust Networks logo, Dust, Dust Networks, and SmartMesh are
registered trademarks of Dust Networks, Inc. The Linear logo is a registered trademark of Linear Technology Corporation. All third-party brand
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ARM and Cortex are trademarks or registered trademarks of ARM Limited in the EU and other countries.
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© Dust Networks, Inc. 2012. All Rights Reserved.
Document Number: 040-0119 Eterna LTP5901 and LTP5902 Integration Guide
Last Revised: October 24, 2013