Linear Technology DC1763A Quick setup guide

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DC1763A-F
ANALOG DEVICES
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1
dc1763af
DEMO MANUAL DC1763A
DESCRIPTION
LTC2195, LTC2194, LTC2193,
LTC2192, LTC2191, LTC2190
16-Bit, 25Msps to 125Msps Dual ADCs
Demonstration circuit 1763A supports a family of 16-Bit
25Msps to 125Msps ADCs. Each assembly features one
of the following devices: LTC
®
2195, LTC2194, LTC2193,
LTC2192, LTC2191, LTC2190 high speed, dual ADCs.
The versions of the 1763A demo board are listed in Table1.
Depending on the required resolution and sample rate,
the DC1763A is supplied with the appropriate ADC. The
L, LT, LTC, LTM, μModule, Linear Technology and the Linear logo are registered trademarks
and PScope is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
circuitry on the analog inputs is optimized for analog input
frequencies from 5MHz to 140MHz. Refer to the data sheet
for proper input networks for different input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
Table 1. DC1763A Variants
DC1763A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY
1763A-A LTC2195 16-Bit 125Msps 5MHz to 140MHz
1763A-B LTC2194 16-Bit 105Msps 5MHz to 140MHz
1763A-C LTC2193 16-Bit 80Msps 5MHz to 140MHz
1763A-D LTC2192 16-Bit 65Msps 5MHz to 140MHz
1763A-E LTC2191 16-Bit 40Msps 5MHz to 140MHz
1763A-F LTC2190 16-Bit 25Msps 5MHz to 140MHz
PERFORMANCE SUMMARY
(TA= 25°C)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage – DC1763A Depending on Sampling Rate and the A/D Converter
Provided, this Supply Must Provide up to 500mA.
3 3.6 6 V
Analog Input Range Depending on SENSE Pin Voltage 1 2 VP-P
Logic Input Voltages Minimum Logic High
Maximum Logic Low
1.3
0.6
V
V
Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
Common Mode
350
1.25
247
1.25
mV
V
mV
V
Sampling Frequency (Convert Clock Frequency) See Table 1
Encode Clock Level Single-Ended Encode Mode (ENC–Tied to GND)
Differential Encode Mode (ENC–Not Tied to GND)
0
0.2
3.6
3.6
V
V
Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet

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dc1763af
DEMO MANUAL DC1763A
TO PROVIDED
USB CABLE
TO PROVIDED
POWER SUPPLY
ANALOG INPUTS
CHANNEL 1
PARALLEL/SERIAL SINGLE-ENDED
ENCODE CLOCK
(USE PROVIDED DC1075,
DIVIDE BY 4-CLOCK BOARD)
dc1763a F01
CHANNEL 2
3V TO 6V
QUICK START PROCEDURE
Figure 1. Demo Board Setup
Demonstration circuit 1763A is easy to set up to evaluate
the performance of the LTC2195 A/D converterfamily. Refer
to Figure 1 for proper measurement equipment setup and
follow the procedure below:
Setup
If a DC1371 PStache Data Acquisition and Collection
System was supplied with the DC1763A demonstration
circuit, follow the DC1371 Quick Start Guide to install the
required software and for connecting the DC1371 to the
DC1763A and to a PC.
DC1763A Demonstration Circuit Board Jumpers
The DC1763A demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
J1 PAR/SER: Selects parallel or serial programming
mode. (default: serial)
Optional Jumpers:
J8 Term: Enables/Disables optional output termination.
(default: removed)
J5 ILVDS: Selects either 1.75mA or 3.5mA of output
current for the LVDS drivers. (default: removed)
J14 LANE: Selects either 1-lane or 2-lane output modes
(default:removed)NOTE:TheDC1371doesnotsupport
1-lane operation.
J15 SHDN: Enables and disables the LTC2195. (default:
removed)
J2 WP: Enable/Disables write protect for the EEPROM.
(default: removed)
Note: optional jumper should be left open to ensure proper
serial configuration.

3
dc1763af
DEMO MANUAL DC1763A
QUICK START PROCEDURE
Applying Power and Signals to the DC1763A
Demonstration Circuit
If a DC1371 is used to acquire data from the DC1763A,
the DC1371 must FIRST be connected to a powered USB
port and have 5V applied power BEFORE applying 3.6V to
6V across the pins marked V+and GND on the DC1763A.
DC1763A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1763A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC1763A should not be removed, or connected to
the DC1371 while power is applied.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the LTC2195 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1763A demonstration circuit board
marked J3 AIN1 and J4 AIN2. These inputs correspond
with channels one and two of the ADC respectively. These
inputs are capacitively coupled to balun transformers
ETC1-1-13(leadfreepartnumberMABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1763A demonstration circuit board marked J11
CLK+. As a default the DC1763A is populated to have a
single-ended input.
For the best noise performance, the ENCODE INPUT must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3VP-P or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2195. Using band pass filters on the clock and
the analog input will improve the noise performance by
reducing the wideband noise power of the signals. In
the case of the DC1763A a band pass filter used for the
clock should be used prior to the DC1075. Data sheet FFT
plots are taken with 10-pole LC filters made by TTE (Los
Angeles, CA) to suppress signal generator harmonics,
non-harmonically related spurs and broadband noise.
Low phase noise Agilent 8644B generators are used for
both the clock input and the analog input.
Digital Outputs
The data outputs, data clock, and frame clock signals are
available on J1 of the DC1763A. This connector follows the
VITA-57/FMC standard, but all signals should be verified
when using an FMC carrier card other than the DC1371.
Software
The DC1371 is controlled by the PScope™ System Soft-
ware provided or downloaded from the Linear Technology
website at http://www.linear.com/software/.
To start the data collection software if PScope.exe, is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.

4
dc1763af
DEMO MANUAL DC1763A
QUICK START PROCEDURE
If the DC1763Ademonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC1763A, and configure itself accordingly. If everything is
hooked up properly, powered and a suitable convert clock
is present, clicking the Collect button should result in time
and frequency plots displayed in the PScope window. Ad-
ditional information and help for PScope is available in the
DC1371 Quick Start Guide and in the online help available
within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1763A board
serially through the DC1371. There are several options
available in the LTC2195 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 2).
Figure 3. Demobd Configuration Options
Figure 2. PScope Toolbar
Two’s Complement: Enables two’s complement mode
• Off (Default): Selects offset binary mode
• On: Selects two’s complement mode
Sleep Mode: Selects between normal operation, sleep
mode:
• Off (Default): Entire ADC is powered, and active
• On: The entire ADC is powered down.
This will bring up the menu shown in Figure 3.
This menu allows any of the options available for the
LTC2195 family to be programmed serially. The LTC2195
family has the following options:
Randomizer: Enables data output randomizer
• Off (Default): Disables data output randomizer
• On: Enables data output randomizer

5
dc1763af
DEMO MANUAL DC1763A
QUICK START PROCEDURE
Channel 1 Nap: Selects between normal operation and
putting channel 1 in nap mode.
• Off (Default): Channel one is active
• On: Channel one is in nap mode
Channel 2 Nap: Selects between normal operation and
putting channel 2 in nap mode.
• Off (Default): Channel two is active
• On: Channel two is in nap mode
Output Current: Selects the LVDS output drive current
• 1.75mA (Default): LVDS output driver current
• 2.1mA: LVDS output driver current
• 2.5mA: LVDS output driver current
• 3.0mA: LVDS output driver current
• 3.5mA: LVDS output driver current
• 4.0mA: LVDS output driver current
• 4.5mA: LVDS output driver current
Internal Termination: Enables LVDS internal termination
• Off (Default): Disables internal termination
• On: Enables internal termination
Outputs: Enables digital outputs
• Enabled (Default): Enables digital outputs
• Disabled: Disables digital outputs
Test Pattern: Selects digital output test patterns. The
desired test pattern can be entered into the text boxes
provided.
• Off(default): ADC input data is displayed
• On: Test pattern is displayed.
Once the desired settings are selected hit OK and PScope
will automatically update the register of the device on the
DC1763A demo board.

6
dc1763af
DEMO MANUAL DC1763A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 1 CN1 Capacitor, Array, 0508, 2.2μF, 20%, 4V, X5R AVX, W2L14D225MAT1A
2 13 C2, C3, C5, C7, C8, C9, C15, C16, C18,
C28, C36, C48, C52
Capacitor, X5R, 0.1μF, 10V, 10%, 0402 AVX, 0402ZD104KAT2A
3 1 C4 Capacitor, X5R, 1μF, 10V, 10%, 0402 AVX, 0402ZD105KAT2A
4 1 C6 Capacitor, Tantalum, 100μF, 16V, 10%, 6032 AVX, TPSC107K016R0200
5 3 C10, C53, C54 Capacitor, X7R, 1μF, 10V, 10%, 0603 AVX, 0603ZC105KAT2A
6 1 C17 Capacitor, X5R, 2.2μF, 10V, 20%, 0603 AVX, 0603ZD225MAT2A
7 4 C25, C26, C33, C34 Capacitor, X7R, 0.01μF, 50V, 10%, 0603 AVX, 06035C103KAT2A
8 2 C27, C35 Capacitor, COG, 4.7pF, 50V, 5%, 0402 AVX, 04025A4R7JAT2A
9 2 C29, C37 Capacitor, X5R, 2.2μF, 6.3V, 20%, 0402 AVX, 04026D225MAT2A
10 7 C30, C38, C43-C47 Capacitor, X7R, 0.01μF, 16V, 10%, 0402 AVX, 0402YC103KAT2A
11 4 C31, C32, C39, C40 Capacitor, COG, 8.2pF, 50v, 5%, 0402 AVX, 04025A8R2JAT2A
12 1 C49 Capacitor, X7R, 0.01μF, 25V, 10%, 0402 AVX, 04023C103KAT2A
13 1 C51 Capacitor, X5R, 4.7μF, 6.3V, 20%, 0603 AVX, 06036D475MAT2A
14 1 J1 BGA Connector, 40 ×10 Samtec, SEAM-40-02.0-S-10-2-A
15 6 JP2, JP5, JP8, JP13, JP14, JP15 Header, 3-Pin, 0.079, Single Row Samtec, TMM-103-02-L-S
16 2 J3, J4 Connector, SMA 50Ω, Edge-Launch E. F. Johnson, 142-0701-851
17 2 J11, J12 Connector, SMA Jack, Straight, Thru-Hole Amphenol Connex, 132134
18 2 L4, L5 Inductor, 56nH, 0603 Murata, LQP18MN56NG02D
19 1 L7 Ferrite Bead, 0603 Murata, BLM18BB470SN1D
20 2 L9, L11 Ferrite Bead, 1206 Murata, BLM31PG330SN1L
21 2 R1, R63 Resistor, Chip, 0Ω 0402 Yageo, RC0402FR-070RL
22 0 R2, R57-R59, R61, R62, R64, R65 OPT, Resistor, Chip, 0402
23 12 R4, R5, R10, R36, R102-R109 Resistor, Chip, 10k, 1/16W, 5%, 0402 Yageo, RC0402JR-0710KL
24 2 R8, R92 Resistor, Chip, 100Ω, 1/16W, 1%, 0402 Yageo, RC0402FR-07100RL
25 6 R9, R11, R14, R72, R73, R74 Resistor, Chip, 1k, 1/16W, 5%, 0402 Yageo, RC0402JR-071KL
26 1 R12 Resistor, Chip, 31.6k, 1/16W, 1%, 0402 Yageo, RC0402FR-0731K6L
27 4 R26, R29, R39, R46 Resistor, Chip, 33.2Ω, 1/16W, 1%, 0402 Yageo, RC0402FR-0733R2L
28 9 R30, R47, R56, R60, R95-R99 Resistor, Chip, 100Ω, 1/16W, 5%, 0402 Yageo, RC0402JR-07100RL
29 8 R31, R32, R33, R34, R48-R51 Resistor, Chip, 10.0Ω, 1/16W, 1%, 0402 Yageo, RC0402FR-0710RL
30 2 R35, R52 Resistor, Chip, 86.6Ω, 1/16W, 1%, 0402 Yageo, RC0402FR-0786R6L

7
dc1763af
DEMO MANUAL DC1763A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
31 4 R37, R38, R53, R54 Resistor, Chip, 86.6Ω, 1/16W, 1%, 0603 Yageo, RC0603FR-0786R6L
32 2 R40, R41 Resistor, Chip, 49.9Ω, 1/16W, 1%, 0402 Yageo, RC0402FR-0749R9L
33 2 R42, R43 Resistor, Chip, 5.1Ω, 1/16W, 1%, 0402 Yageo, RC0402FR-075R1L
34 8 R110-R117 Resistor, Chip, 33k, 1/16W, 1%, 0402 Yageo, RC0402FR-0733KL
35 3 TP1, TP6, TP7 Testpoint, Turret, .094, PBF Mill-Max, 2501-2-00-80-00-00-07-0
36 3 T5, T9, T11 Transformer, RF~SMT~1:1 Balun Macom, MABA-007159-000000
37 2 T8, T10 Transformer, Flux-Coupled Balun Macom, MABAES0060
38 1 U2 IC, LT1763CS8-1.8 SO8 Linear Technology, LT1763CS8-1.8#PBF
39 1 U3 IC, EEPROM 32KBIT 400khz 8TSSOP Microchip, 24LC32A-I/ST
40 6 XJ2, XJ5, XJ8, XJ13, XJ14, XJ15 Shunt, 0.079" Center Samtec, 2SN-BK-G
41 2 Stencil (Top & Bottom) Stencil 1763A

8
dc1763af
DEMO MANUAL DC1763A
SCHEMATIC DIAGRAM
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
AIN1
EXT REF
V+
3V - 6V
GND
CLK+
CLK-
*
AIN2
ASSY
LTC2195CUKG
ASSEMBLY TABLE
U1
65 40
80
125
25
105
Msps
LTC2194CUKG LTC2193CUKG LTC2192CUKG LTC2191CUKG LTC2190CUKG
-B -C -D -E -F -A
2. INSTALL SHUNTS AS SHOWN. 1. ALL RESISTORS ARE IN OHMS, 0402. ALL CAPACITORS ARE IN MICROFARADS, 0402. NOTE: UNLESS OTHERWISE SPECIFIED
0508
6032
0603
0603 0603
0603
0603
0603
0603
0603
0603
1- FIRST PROTOTYPE CLARENCE M. 10/22/2010
*
AIN1- AIN1+
AIN2+ AIN2-
VDD OVDD
VDD
VDD
VDD
OVDD
OVDDVDD
PAR/!SER
MISO
OUT1B- OUT1B+ OUT1A- OUT1A+
MOSI SCK CS0
OUT2B- OUT2A+ OUT2A- OUT2B+ DCO+ DCO- FR+ FR-
OUT1C+
OUT1C- OUT1D+ OUT1D-
OUT2C+ OUT2C- OUT2D+ OUT2D-
REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV REVISION HISTORY DESCRIPTION DATEAPPROVEDECO REV
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
1
Tuesday, October 26, 2010
12
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
M.H.
CLARENCE M.
N/A
LTC219XCUKG FAMILY
DEMO CIRCUIT 1763A
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
1
Tuesday, October 26, 2010
12
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
M.H.
CLARENCE M.
N/A
LTC219XCUKG FAMILY
DEMO CIRCUIT 1763A
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
1
Tuesday, October 26, 2010
12
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
M.H.
CLARENCE M.
N/A
LTC219XCUKG FAMILY
DEMO CIRCUIT 1763A
C39
8.2pF
C39
8.2pF
C16
0.1uF
C16
0.1uF
R46 33.2 R46 33.2
C29
2.2uF
C29
2.2uF
R53 86.6 R53 86.6
R49 10 R49 10
R35 86.6 R35 86.6
C40
8.2pF
C40
8.2pF
R43 5.1 R43 5.1
R65 OPT R65 OPT
T5
MABA-007159-000000
T5
MABA-007159-000000
5 4 3
1 2
R52 86.6 R52 86.6
C17
2.2uF
C17
2.2uF
R37 86.6 R37 86.6
C28
0.1uF
C28
0.1uF
T8
MABAES0060
T8
MABAES0060
4 5 1
3 2
TP1TP1
R48 10 R48 10
C27
4.7pf
C27
4.7pf
R33 10 R33 10
J4J4
U2
LT1763CS8-1.8
U2
LT1763CS8-1.8
OUT 1
SEN/ADJ 2
GND
3
BYP 4
SHDN
5
GND
6
GND
7
IN
8
R38 86.6 R38 86.6
C2
0.1uF
C2
0.1uF
T11
MABA-007159-000000
T11
MABA-007159-000000
5 4 3
1 2
L5 56nH L5 56nH
TP7TP7
C32
8.2pF
C32
8.2pF
C46 0.01uFC46 0.01uF
C3
0.1uF
C3
0.1uF
L4
56nH
L4
56nH
R60
100
R60
100
R41 49.9 R41 49.9
CN1 2.2uF CN1 2.2uF
81 72 63 54
R56
100
R56
100
C36
0.1uF
C36
0.1uF
C31
8.2pF
C31
8.2pF
R34 10 R34 10
J11J11
R59 OPT R59 OPT
C52
0.1uF
C52
0.1uF
R42 5.1 R42 5.1
C54
1uF
C54
1uF
J12J12
R63 0R63 0
R31 10 R31 10
C9
0.1uF
C9
0.1uF
C43
0.01uF
C43
0.01uF
R61
OPT
R61
OPT
T9
MABA-007159-000000
T9
MABA-007159-000000
5 4 3
1 2
TP6TP6
C53
1uF
C53
1uF
C33
0.01uF
C33
0.01uF
T10
MABAES0060
T10
MABAES0060
4 5 1
3 2
C8
0.1uF
C8
0.1uF
C47 0.01uFC47 0.01uF
C44
0.01uF
C44
0.01uF
C51
4.7uF
C51
4.7uF
L11
BEAD
L11
BEAD
C49
0.01uF
C49
0.01uF
C4
1uF
C4
1uF
R50 10 R50 10
R14 1K R14 1K
J3J3
R32 10 R32 10
C15
0.1uF
C15
0.1uF
C34
0.01uF
C34
0.01uF
R26 33.2 R26 33.2 R39 33.2 R39 33.2 R29 33.2 R29 33.2
R40 49.9 R40 49.9
C35
4.7pf
C35
4.7pf
C7
0.1uF
C7
0.1uF
R47
100
R47
100
LTC2195UKG
U1
LTC2195UKG
U1
VCM1
1
GND
2
AIN1+
3
AIN1-
4
GND
5
REFH
6
REFL
7
REFH
8
REFL
9
PAR/SER
10
AIN2+
11
AIN2-
12
GND
13
VCM2
14
Vdd
15
Vdd
16
ENC+
17
ENC-
18
CS
19
SCK
20
SDI
21
GND
22
OUT2D-
23
OUT2D+
24
OUT2C-
25
OUT2C+
26
OUT2B- 27
OUT2B+ 28
OUT2A- 29
OUT2A+ 30
FR- 31
FR+ 32
OGND 33
OVdd 34 DCO- 35
DCO+ 36
OUT1D- 37
OUT1D+ 38
OUT1C- 39
OUT1C+ 40
OUT1B- 41
OUT1B+ 42
OUT1A- 43
OUT1A+ 44
GND 45
SDO 46
GND 47
Vref 48
GND 49
SENSE 50
Vdd 51
Vdd 52
EP 53
C26
0.01uF
C26
0.01uF
C37
2.2uF
C37
2.2uF
C30
0.01uF
C30
0.01uF
R92 100 R92 100
R58 OPT R58 OPT
C48
0.1uF
C48
0.1uF
L7
BEAD
L7
BEAD
R64
OPT
R64
OPT
C38
0.01uF
C38
0.01uF
R54
86.6
R54
86.6
C25
0.01uF
C25
0.01uF
R57 OPT R57 OPT
C45
0.01uF
C45
0.01uF
C10
1uF
C10
1uF
+C6
100uF
+C6
100uF
C5
0.1uF
C5
0.1uF
R62 OPT R62 OPT
R8 100 R8 100
R30
100
R30
100
R51 10 R51 10
L9
BEAD
L9
BEAD

9
dc1763af
DEMO MANUAL DC1763A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
CHANNEL 1
CHANNEL 2
FRAME CLOCK
DATA CLOCK
WP EN
DIS
2 1
LANE
TERM
SER
PAR/SER
PAR EN
DIS
ILVDS
SHDN
3.5mA 1.75mASHDN
RUN
C0 C2 C7C4C1 C3 C6C5
C0 C1 C2 C3 C4 C5 C6 C7
VDD
3.3_AUX
VDD
VDDVDD
VDD VDD
3.3_AUX
3.3_AUX
CS0 MISO
FR+
FR-
MOSI SCK
DCO- DCO+
OUT1A- OUT2A- OUT2A+
OUT1A+
OUT2B- OUT2B+
OUT1B+
OUT1B-
CS0
MISOPAR/!SER
OUT1C+
OUT1C-
OUT1D+
OUT1D-
OUT2C+
OUT2C-
OUT2D+
OUT2D-
MOSI SCK
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
1
Tuesday, October 26, 2010
22
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
M.H.
CLARENCE M.
N/A
LTC219XCUKG FAMILY
DEMO CIRCUIT 1763A
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
1
Tuesday, October 26, 2010
22
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
M.H.
CLARENCE M.
N/A
LTC219XCUKG FAMILY
DEMO CIRCUIT 1763A
SIZE DATE:
IC NO. REV.
SHEET OF
TITLE:
APPROVALS
PCB DES.
APP ENG.
TECHNOLOGY Fax: [phone]
Milpitas, CA 95035 Phone: [phone] McCarthy Blvd. LTC Confidential-For Customer Use Only
CUSTOMER NOTICE
LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED
CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT
PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE.
THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND
SCHEMATIC
SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS.
SCALE = NONE
www.linear.com
1
Tuesday, October 26, 2010
22
16-BIT DUAL, HIGH SPEED, SERIAL LVDS ADC
M.H.
CLARENCE M.
N/A
LTC219XCUKG FAMILY
DEMO CIRCUIT 1763A
J1J
SEAM-10X40PIN
J1J
SEAM-10X40PIN
GND J1
CLK1_C2M_P J2
CLK1_C2M_N J3
GND J4 GND J5
HA03_P J6
HA03_N J7
GND J8
HA07_P J9
HA07_N J10
GND J11
HA11_P J12
HA11_N J13
GND J14
HA14_P J15
HA14_N J16
GND J17
HA18_P J18
HA18_N J19
GND J20
HA22_P J21
HA22_N J22
GND J23
HB01_P J24
HB01_N J25
GND J26
PB07_P J27
HB07_N J28
GND J29
HB11_P J30
HB11_N J31
GND J32
HB15_P J33
HB15_N J34
GND J35
HB18_P J36
HB18_N J37
GND J38
VIO_B_M2C J39
GND J40
R73 1K R73 1K
R108 10K R108 10K
R72 1K R72 1K
J1E
SEAM-10X40PIN
J1E
SEAM-10X40PIN
GND E1
HA01_P_CC E2
HA01_N_CC E3
GND E4 GND E5
HA05_P E6
HA05_N E7
GND E8
HA09_P E9
HA09_N E10
GND E11
HA13_P E12
HA13_N E13
GND E14
HA16_P E15
HA16_N E16
GND E17
HA20_P E18
HA20_N E19
GND E20
HB03_P E21
HB03_N E22
GND E23
HB05_P E24
HB05_N E25
GND E26
HB09_P E27
HB09_N E28
GND E29
HB13_P E30
HB13_N E31
GND E32
HB21_P E33
HB21_N E34
GND E35
HB20_P E36
HB20_N E37
GND E38
VADJ E39
GND E40
R5
10K
R5
10K
R102 10K R102 10K
JP15JP15
1
2
3
R107 10K R107 10K
R74 1K R74 1K
J1A SEAM-10X40PIN J1A SEAM-10X40PIN
GND A1
DP1_M2C_P A2
DP1_M2C_N A3
GND A4 GND A5
DP2_M2C_P A6
DP2_M2C_N A7
GND A8 GND A9
DP3_M2C_P A10
DP3_M2C_N A11
GND A12 GND A13
DP4_M2C_P A14
DP4_M2C_N A15
GND A16 GND A17
DP5_M2C_P A18
DP5_M2C_N A19
GND A20 GND A21
DP1_C2M_P A22
DP1_C2M_N A23
GND A24 GND A25
DP2_C2M_P A26
DP2_C2M_N A27
GND A28 GND A29
DP3_C2M_P A30
DP3_C2M_N A31
GND A32 GND A33
DP4_C2M_P A34
DP4_C2M_N A35
GND A36 GND A37
DP5_C2M_P A38
DP5_C2M_N A39
GND A40
R98100R98100
R103 10K R103 10K
R115 33K R115 33K
R10 10K R10 10K
R97 100R97 100
J1K
SEAM-10X40PIN
J1K
SEAM-10X40PIN
VREF_B_M2C K1
GND K2 GND K3
CLK1_M2C_P K4
CLK1_M2C_N K5
GND K6
HA02_P K7
HA02_N K8
GND K9
HA06_P K10
HA06_N K11
GND K12
HA10_P K13
HA10_N K14
GND K15
HA17_P_CC K16
HA17_N_CC K17
GND K18
HA21_P K19
HA21_N K20
GND K21
HA23_P K22
HA23_N K23
GND K24
HB00_P_CC K25
HB00_N_CC K26
GND K27
HB06_P_CC K28
HB06_N_CC K29
GND K30
HB10_P K31
HB10_N K32
GND K33
HB14_P K34
HB14_N K35
GND K36
HB17_P_CC K37
HB17_N_CC K38
GND K39
VIO_B_M2C K40
JP14JP14
1
2
3
R109 10K R109 10K
J1F
SEAM-10X40PIN
J1F
SEAM-10X40PIN
PG_M2C F1
GND F2 GND F3
HA00_P_CC F4
HA00_N_CC F5
GND F6
HA04_P F7
HA04_N F8
GND F9
HA08_P F10
HA08_N F11
GND F12
HA12_P F13
HA12_N F14
GND F15
HA15_P F16
HA15_N F17
GND F18
HA19_P F19
HA19_N F20
GND F21
HB02_P F22
HB02_N F23
GND F24
HB04_P F25
HB04_N F26
GND F27
HB08_P F28
HB08_N F29
GND F30
HB12_P F31
HB12_N F32
GND F33
HB16_P F34
HB16_N F35
GND F36
HB19_P F37
HB19_N F38
GND F39
VADJ F40
R99 100 R99 100
R116 33K R116 33K
J1B
SEAM-10X40PIN
J1B
SEAM-10X40PIN
RES1 B1
GND B2 GND B3
DP9_M2C_P B4
DP9_M2C_N B5
GND B6 GND B7
DP8_M2C_P B8
DP8_M2C_N B9
GND B10 GND B11
DP7_M2C_P B12
DP7_M2C_N B13
GND B14 GND B15
DP6_M2C_P B16
DP6_M2C_N B17
GND B18 GND B19
GBTCLK1_M2C_P B20
GBTCLK1_M2C_N B21
GND B22 GND B23
DP9_C2M_P B24
DP9_C2M_N B25
GND B26 GND B27
DP8_C2M_P B28
DP8_C2M_N B29
GND B30 GND B31
DP7_C2M_P B32
DP7_C2M_N B33
GND B34 GND B35
DP6_C2M_P B36
DP6_C2M_N B37
GND B38 GND B39
RES0 B40
R11 1K R11 1K
R106 10K R106 10K R114 33K R114 33K
R96 100R96 100
R12
31.6K
R12
31.6K
R1
0
R1
0
R95
100
R95
100
J1G SEAM-10X40PIN J1G SEAM-10X40PIN
GND G1
CLK0_C2M_P G2
CLK0_C2M_N G3
GND G4 GND G5
LA00_P_CC G6
LA00_N_CC G7
GND G8
LA03_P G9
LA03_N G10
GND G11
LA08_P G12
LA08_N G13
GND G14
LA12_P G15
LA12_N G16
GND G17
LA16_P G18
LA16_N G19
GND G20
LA20_P G21
LA20_N G22
GND G23
LA22_P G24
LA22_N G25
GND G26
LA25_P G27
LA25_N G28
GND G29
LA29_P G30
LA29_N G31
GND G32
LA31_P G33
LA31_N G34
GND G35
LA33_P G36
LA33_N G37
GND G38
VADJ G39
GND G40
R9 1K R9 1K
JP13JP13
1
2
3
R117 33K R117 33K
J1C
SEAM-10X40PIN
J1C
SEAM-10X40PIN
GND C1
DP0_C2M_P C2
DP0_C2M_N C3
GND C4 GND C5
DP0_M2C_P C6
DP0_M2C_N C7
GND C8 GND C9
LA06_P C10
LA06_N C11
GND C12 GND C13
LA10_P C14
LA10_N C15
GND C16 GND C17
LA14_P C18
LA14_N C19
GND C20 GND C21
LA18_P_CC C22
LA18_N_CC C23
GND C24 GND C25
LA27_P C26
LA27_N C27
GND C28 GND C29
SCL C30
SDA C31
GND C32 GND C33
GA0 C34
12P0V C35
GND C36
12P0V C37
GND C38
3P3V C39
GND C40
R4
10K
R4
10K
JP5JP5
1
2
3
R105 10K R105 10K
R110 33K R110 33K
JP8JP8
1
2
3
R2
OPT
R2
OPT
J1H
SEAM-10X40PIN
J1H
SEAM-10X40PIN
VREF_A_M2C H1
PRSNT_M2C_N H2
GND H3
CLK0_M2C_P H4
CLK0_M2C_N H5
GND H6
LA02_P H7
LA02_N H8
GND H9
LA04_P H10
LA04_N H11
GND H12
LA07_P H13
LA07_N H14
GND H15
LA11_P H16
LA11_N H17
GND H18
LA15_P H19
LA15_N H20
GND H21
LA19_P H22
LA19_N H23
GND H24
LA21_P H25
LA21_N H26
GND H27
LA24_P H28
LA24_N H29
GND H30
LA28_P H31
LA28_N H32
GND H33
LA30_P H34
LA30_N H35
GND H36
LA32_P H37
LA32_N H38
GND H39
VADJ H40
JP2JP2
1
2
3
J1D
SEAM-10X40PIN
J1D
SEAM-10X40PIN
PG_C2M D1
GND D2 GND D3
GBTCLK0_M2C_P D4
GBTCLK0_M2C_N D5
GND D6 GND D7
LA01_P_CC D8
LA01_N_CC D9
GND D10
LA05_P D11
LA05_N D12
GND D13
LA09_P D14
LA09_N D15
GND D16
LA13_P D17
LA13_N D18
GND D19
LA17_P_CC D20
LA17_N_CC D21
GND D22
LA23_P D23
LA23_N D24
GND D25
LA26_P D26
LA26_N D27
GND D28
TCK D29
TDI D30
TDO D31
3P3VAUX D32
TMS D33
TRST_N D34
GA1 D35
3P3V D36
GND D37
3P3V D38
GND D39
3P3V D40
R111 33K R111 33K
R36
10K
R36
10K
R113 33K R113 33K
R104 10K R104 10K
U3
24LC32A-I /ST
U3
24LC32A-I /ST
A0
1A1 2A2 3
VSS
4
SDA
5SCL 6
WP
7
VCC 8
C18
0.1uF
C18
0.1uF
R112 33K R112 33K