Lucent Technologies DSP1617 Quick setup guide

DRAFT COPY
DSP1611/17/18/27/28/29
Digital Signal Processor
Information Manual
January 1998
For additional information, contact your Microelectronics Group Account Manager or the following:
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Copyright © 1998 Lucent Technologies Inc.
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MN97-030WDSP

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A Word About Trademarks . . .
The following Lucent Technologies Inc. trademarks are used in this manual:
Tapdance
®
FlashDSP
®
The following trademarks, owned by entities other than Lucent Technologies Inc., are used in this manual:
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Intel is a registered trademark of Intel Corporation.
Motorola is a registered trademark of Motorola, Inc.
MS-DOS and Windows are registered trademarks of Microsoft Corporation.
TI is a registered trademark of Texas Instruments, Inc.
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X-Windows is a trademark of Massachusetts Institute of Technology.

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Foreword
This manual contains detailed information on the design and application of the DSP1611/17/18/27/28/29 Digital
Signal Processor family, which includes the
FlashDSP
®1618,
FlashDSP 1627, FlashDSP 1628, and
FlashDSP 1629 development devices. The DSP1611-ST, DSP1618-ST, DSP1617-ST, DSP1627-ST,
DSP1628-ST, and DSP1629-ST support software libraries, the
FlashDSP 1600-HDS Development System, and
numerous DSP1611/17/18/27/28/29-specific hardware support tools are also available to aid in developing soft-
ware and integrating the devices into systems.
Additional information on the digital signal processor product line is available in the form of manuals, data sheets,
and application notes.
Conventions Used in this Manual
In general, all registers writable or readable by DSP instructions are lower case. Device flags, I/O pins, and nonpro-
gram-accessible registers are generally upper case. For clarity, register names and DSP instructions are printed in
boldface when used in written descriptions. Variable names that are to be replaced by specific names are itali-
cized, such as
filename . Instruction set notation conventions are defined in Chapter 4.

DSP1611/17/18/27/28/29 Digital Signal Processor
INFORMATION MANUAL
CONTENTS
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➤1 Introduction.................................................................................................................................................. 1-1
➤1.1 General Description .......................................................................................................................... 1-2
➤1.1.1 Architecture ........................................................................................................................ 1-2
➤1.1.2 Instruction Set .................................................................................................................... 1-3
➤1.2 Typical Applications........................................................................................................................... 1-3
➤1.3 Application Support........................................................................................................................... 1-4
➤1.3.1 Support Software Library ................................................................................................... 1-4
➤1.3.2 Hardware Development System ......................................................................................... 1-4
➤1.4 Manual Organization......................................................................................................................... 1-6
➤1.4.1 Applicable Documentation .................................................................................................1-7
➤2 Hardware Architecture................................................................................................................................. 2-1
➤2.1 Device Architecture Overview........................................................................................................... 2-1
➤2.1.1 Harvard Architecture .......................................................................................................... 2-1
➤2.1.2 Concurrent Operations ....................................................................................................... 2-2
➤2.1.3 Device Architecture ............................................................................................................ 2-4
➤2.1.4 Memory Space and Bank Switching ................................................................................ 2-12
➤2.1.5 Internal Instruction Pipeline .............................................................................................. 2-13
➤2.2 Core Architecture Overview............................................................................................................ 2-16
➤2.2.1 Data Arithmetic Unit ......................................................................................................... 2-16
➤2.2.2 Y Space Address Arithmetic Unit (YAAU) ........................................................................ 2-17
➤2.2.3 X Space Address Arithmetic Unit (XAAU) ........................................................................ 2-18
➤2.2.4 Cache ............................................................................................................................... 2-18
➤2.2.5 Control ............................................................................................................................. 2-18
➤2.3 Internal Memories........................................................................................................................... 2-19
➤2.4 External Memory Interface (EMI).................................................................................................... 2-19
➤2.5 Bit Manipulation Unit (BMU)............................................................................................................ 2-20
➤2.6 Serial Input/Output (SIO) Units ....................................................................................................... 2-20
➤2.7 Parallel Input/Output (PIO) (DSP1617 Only)................................................................................... 2-21
➤2.8 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only).......................................................... 2-21
➤2.9 Bit Input/Output (BIO) ..................................................................................................................... 2-22
➤2.10 JTAG ............................................................................................................................................... 2-22
➤2.11 Timer............................................................................................................................................... 2-22
➤2.12 Hardware Development System (HDS) Module.............................................................................. 2-23
➤2.13 Clock Synthesis (DSP1627/28/29 Only) ......................................................................................... 2-23
➤2.14 Power Management........................................................................................................................ 2-23
➤3 Software Architecture.................................................................................................................................. 3-1
➤3.1 Register View of the DSP1611/17/18/27/28/29................................................................................. 3-1
➤3.1.1 Types of Registers .............................................................................................................. 3-1
➤3.1.2 Register Length Definition .................................................................................................. 3-5
➤3.1.3 Register Reset Values ........................................................................................................ 3-6
➤3.1.4 Flags .................................................................................................................................. 3-7
➤3.2 Memory Space and Addressing........................................................................................................ 3-8
➤3.2.1 Y-Memory Space ................................................................................................................ 3-8

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➤3.2.2 X-Memory Space ............................................................................................................. 3-10
➤3.3 Arithmetic and Precision ................................................................................................................. 3-21
➤3.4 Interrupts......................................................................................................................................... 3-27
➤3.4.1 Introduction ...................................................................................................................... 3-27
➤3.4.2 Interrupt Sources ............................................................................................................. 3-29
➤3.4.3 Outputs of Interrupts ........................................................................................................ 3-31
➤3.4.4 Interrupt Operation ........................................................................................................... 3-32
➤3.4.5 Trap Description ............................................................................................................... 3-38
➤3.4.6 Powerdown with the AWAIT State .................................................................................... 3-40
➤3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) ............................................... 3-42
➤3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) ..................................... 3-44
➤3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only).......................................................... 3-47
➤3.5.1 PLL Control Signals ......................................................................................................... 3-48
➤3.5.2 PLL Programming Examples ........................................................................................... 3-50
➤3.5.3 Latency ............................................................................................................................ 3-50
➤3.6 Power Management........................................................................................................................ 3-52
➤3.6.1 powerc Control Register Bits ........................................................................................... 3-52
➤3.6.2 STOP Pin ......................................................................................................................... 3-56
➤3.6.3 The pllc Register Bits (DSP1627/28/29 Only) ................................................................. 3-56
➤3.6.4 AWAIT Bit of the alf Register ........................................................................................... 3-56
➤3.6.5 Power Management Sequencing ..................................................................................... 3-57
➤3.6.6 Power Management Examples ........................................................................................ 3-58
➤4 Instruction Set ............................................................................................................................................. 4-1
➤4.1 Notation............................................................................................................................................. 4-2
➤4.2 Instruction Cycle Timing.................................................................................................................... 4-2
➤4.3 Addressing Modes ............................................................................................................................ 4-3
➤4.3.1 Register Indirect Addressing .............................................................................................. 4-3
➤4.3.2 Compound Addressing ......................................................................................................4-5
➤4.3.3 Direct Data Addressing ...................................................................................................... 4-7
➤4.4 Processor Flags................................................................................................................................ 4-9
➤4.5 Instruction Set................................................................................................................................. 4-11
➤4.5.1 Control Instructions .......................................................................................................... 4-12
➤4.5.2 Cache Instructions ........................................................................................................... 4-14
➤4.5.3 Data Move Instructions .................................................................................................... 4-15
➤4.5.4 Special Function Group ................................................................................................... 4-19
➤4.5.5 Multiply/ALU Group .......................................................................................................... 4-22
➤4.5.6 F3 ALU Instructions ......................................................................................................... 4-29
➤4.5.7 BMU Instructions .............................................................................................................. 4-30
➤4.5.8 Assembler Ambiguities ..................................................................................................... 4-35
➤5 Core Architecture ........................................................................................................................................ 5-1
➤5.1 Data Arithmetic Unit.......................................................................................................................... 5-1
➤5.1.1 Inputs and Outputs ............................................................................................................. 5-2
➤5.1.2 Multiplier Functions ............................................................................................................ 5-2
➤5.1.3 ALU .................................................................................................................................... 5-2
➤5.1.4 Accumulators ..................................................................................................................... 5-3
➤5.1.5 Counters ............................................................................................................................ 5-4
➤5.1.6 DAU Pseudorandom Sequence Generator (PSG) ............................................................. 5-7
➤5.1.7 Control Registers ............................................................................................................... 5-9
➤5.2 X Address Arithmetic Unit (XAAU).................................................................................................. 5-11
➤5.2.1 Inputs and Outputs ........................................................................................................... 5-11

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➤5.2.2 X-Memory Space Segment Selection .............................................................................. 5-11
➤5.2.3 Register Descriptions ....................................................................................................... 5-12
➤5.3 Y Address Arithmetic Unit (YAAU) .................................................................................................. 5-13
➤5.3.1 Inputs and Outputs ........................................................................................................... 5-13
➤5.3.2 Y-Memory Space .............................................................................................................. 5-14
➤5.3.3 Register Descriptions ....................................................................................................... 5-14
➤5.3.4 Addressing Modes ........................................................................................................... 5-14
➤5.4 Cache and Control.......................................................................................................................... 5-17
➤5.4.1 Cache ............................................................................................................................... 5-17
➤5.4.2 Control ............................................................................................................................. 5-19
➤6 External Memory Interface.......................................................................................................................... 6-1
➤6.1 EMI Function..................................................................................................................................... 6-1
➤6.2 Programmable Features.................................................................................................................. 6-13
➤6.3 Functional Timing............................................................................................................................ 6-14
➤6.3.1 Timing Action with Wait-States ........................................................................................ 6-15
➤6.4 Timing Examples ............................................................................................................................ 6-17
➤6.4.1 CKO Timing ...................................................................................................................... 6-17
➤6.4.2 Write, Read, Read, W = 0 ................................................................................................ 6-18
➤6.4.3 Read, Write, Write, W = 0 ................................................................................................ 6-19
➤6.4.4 Read, Write, W = 0, Compound Address ......................................................................... 6-20
➤6.4.5 Read W = 1, Read W = 2 ................................................................................................. 6-21
➤6.4.6 Write W = 1 ...................................................................................................................... 6-22
➤6.4.7 Read, Read with Delayed Enable .................................................................................... 6-23
➤6.4.8 Write, Read, with Delayed Enable .................................................................................... 6-24
➤6.5 Boot-Up from External ROM........................................................................................................... 6-25
➤6.6 Memory Sequencer......................................................................................................................... 6-26
➤6.7 Downloading Code into External Program Memory........................................................................ 6-28
➤7 Serial I/O ..................................................................................................................................................... 7-1
➤7.1 SIO Operation................................................................................................................................... 7-2
➤7.1.1 Active Clock Generator ...................................................................................................... 7-2
➤7.1.2 Input Section ...................................................................................................................... 7-4
➤7.1.3 Output Section ................................................................................................................... 7-6
➤7.2 User-Controlled Features.................................................................................................................. 7-9
➤7.2.1 The sioc Register .............................................................................................................. 7-9
➤7.2.2 Loopback Control ............................................................................................................. 7-11
➤7.2.3 Power Management ......................................................................................................... 7-11
➤7.3 Serial I/O Pin Descriptions.............................................................................................................. 7-12
➤7.4 Codec Interface............................................................................................................................... 7-13
➤7.5 Serial I/O Programming Example ................................................................................................... 7-14
➤7.5.1 Program Segment ............................................................................................................ 7-14
➤7.6 Multiprocessor Mode Description.................................................................................................... 7-15
➤7.6.1 Multiprocessor Mode Overview ........................................................................................ 7-15
➤7.6.2 Detailed Multiprocessor Mode Description ...................................................................... 7-17
➤7.6.3 Suggested Multiprocessor Configuration ......................................................................... 7-24
➤7.6.4 Multiprocessor Mode Initialization .................................................................................... 7-25
➤7.7 Serial Interface #2........................................................................................................................... 7-26
➤7.7.1 SIO2 Features .................................................................................................................. 7-26
➤7.7.2 Programmable Features ................................................................................................... 7-27
➤7.7.3 Instructions Using the SIO2 ............................................................................................. 7-27

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➤8 Parallel I/O (DSP1617 Only)........................................................................................................................ 8-1
➤8.1 PIO Operation................................................................................................................................... 8-2
➤8.1.1 Active Mode ....................................................................................................................... 8-2
➤8.1.2 PIO Interaccess Timing ...................................................................................................... 8-5
➤8.1.3 Passive Mode ..................................................................................................................... 8-6
➤8.1.4 Peripheral Mode (Host Interface) ....................................................................................... 8-9
➤8.2 Programmer Interface ..................................................................................................................... 8-14
➤8.2.1 pioc Register Settings ..................................................................................................... 8-16
➤8.2.2 Latent Reads .................................................................................................................... 8-17
➤8.2.3 Power Management ......................................................................................................... 8-19
➤8.3 Interrupts and the PIO..................................................................................................................... 8-19
➤8.4 PIO Signals..................................................................................................................................... 8-21
➤8.4.1 PIO Pin Multiplexing ......................................................................................................... 8-22
➤8.5 PIO Loopback Test Mode................................................................................................................ 8-22
➤9 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)....................................................................... 9-1
➤9.1 PHIF Operation................................................................................................................................. 9-2
➤9.1.1 Intel Mode, 16-Bit Read ..................................................................................................... 9-3
➤9.1.2 Intel Mode, 16-Bit Write ..................................................................................................... 9-4
➤9.1.3 Motorola Mode, 16-Bit Read .............................................................................................. 9-5
➤9.1.4 Motorola Mode, 16-Bit Write .............................................................................................. 9-6
➤9.1.5 8-Bit Transfers .................................................................................................................... 9-7
➤9.1.6 Accessing the PSTAT Register ........................................................................................... 9-7
➤9.2 Programmer Interface ....................................................................................................................... 9-8
➤9.2.1 phifc Register Settings ...................................................................................................... 9-8
➤9.2.2 Power Management ......................................................................................................... 9-10
➤9.3 Interrupts and the PHIF................................................................................................................... 9-10
➤9.4 PHIF Pin Multiplexing...................................................................................................................... 9-11
➤9.5 Overall Functional Timing ............................................................................................................... 9-12
➤10 Bit I/O Unit................................................................................................................................................. 10-1
➤10.1 BIO Hardware Function................................................................................................................... 10-1
➤10.1.1 BIO Configured as Inputs ................................................................................................. 10-2
➤10.1.2 BIO Configured as Outputs .............................................................................................. 10-2
➤10.1.3 Pin Descriptions ............................................................................................................... 10-3
➤10.1.4 BIO Pin Multiplexing ......................................................................................................... 10-4
➤10.2 Software View................................................................................................................................. 10-4
➤10.2.1 Registers .......................................................................................................................... 10-5
➤10.2.2 Flags ................................................................................................................................ 10-6
➤10.2.3 Instructions ....................................................................................................................... 10-6
➤10.2.4 Examples ......................................................................................................................... 10-6
➤11 The JTAG Test Access Port....................................................................................................................... 11-1
➤11.1 Overview of the JTAG Architecture ................................................................................................. 11-1
➤11.2 Overview of the JTAG Instructions.................................................................................................. 11-3
➤11.3 Elements of the JTAG Test Logic .................................................................................................... 11-4
➤11.3.1 The Test Access Port (TAP) ............................................................................................. 11-4
➤11.3.2 The TAP Controller ........................................................................................................... 11-5
➤11.3.3 The Instruction Register—JIR .......................................................................................... 11-7
➤11.3.4 The Boundary-Scan Register—JBSR .............................................................................. 11-8
➤11.3.5 The Bypass Register—JBPR ......................................................................................... 11-16
➤11.3.6 The Device Identification Register—JIDR ...................................................................... 11-16
➤11.3.7 The JTAG Data Register—jtag ...................................................................................... 11-19

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➤11.3.8 The JTAG Control Register—JCON ............................................................................... 11-19
➤11.3.9 The JTAG Output Stage—JOUT .................................................................................... 11-19
➤11.4 The JTAG Instruction Set.............................................................................................................. 11-19
➤11.4.1 The EXTEST Instruction ................................................................................................ 11-19
➤11.4.2 The INTEST Instruction ................................................................................................. 11-19
➤11.4.3 The SAMPLE Instruction ................................................................................................ 11-20
➤11.4.4 The BYPASS Instruction ................................................................................................ 11-20
➤11.4.5 The IDCODE Instruction ................................................................................................ 11-20
➤12 Timer ......................................................................................................................................................... 12-1
➤12.1 Hardware View................................................................................................................................ 12-1
➤12.2 Programmable Features and Operation.......................................................................................... 12-2
➤12.2.1 timerc Register Encoding ................................................................................................ 12-2
➤12.2.2 timer0 Register ................................................................................................................ 12-3
➤12.2.3 The inc Register .............................................................................................................. 12-3
➤12.2.4 Initialization Conditions .................................................................................................... 12-3
➤12.3 Program Example ........................................................................................................................... 12-4
➤12.4 Timing ............................................................................................................................................. 12-5
➤13 Bit Manipulation Unit (BMU)...................................................................................................................... 13-1
➤13.1 Hardware View................................................................................................................................ 13-1
➤13.2 Software View................................................................................................................................. 13-2
➤13.2.1 Instruction Set .................................................................................................................. 13-2
➤13.2.2 Shifting Operations ........................................................................................................... 13-2
➤13.2.3 Normalization ................................................................................................................... 13-4
➤13.2.4 Extraction ......................................................................................................................... 13-5
➤13.2.5 Insertion ........................................................................................................................... 13-6
➤13.2.6 Shuffle Accumulators ....................................................................................................... 13-8
➤13.2.7 Instruction Encoding ........................................................................................................ 13-9
➤13.2.8 Software Example .......................................................................................................... 13-10
➤14 Error Correction Coprocessor (DSP1618/28 Only) ................................................................................... 14-1
➤14.1 System Description......................................................................................................................... 14-1
➤14.2 Hardware Architecture .................................................................................................................... 14-3
➤14.2.1 Branch Metric Unit ........................................................................................................... 14-3
➤14.2.2 Update Unit ...................................................................................................................... 14-4
➤14.2.3 Traceback Unit ................................................................................................................. 14-4
➤14.2.4 Interrupts and Flags ......................................................................................................... 14-5
➤14.2.5 Traceback RAM ................................................................................................................ 14-5
➤14.3 DSP Decoding Operation Sequence .............................................................................................. 14-6
➤14.4 Operation of the ECCP ................................................................................................................... 14-7
➤14.5 Software Architecture...................................................................................................................... 14-8
➤14.5.1 R-Field Registers ............................................................................................................. 14-8
➤14.5.2 ECCP Internal Memory-Mapped Registers .................................................................... 14-10
➤14.5.3 ECCP Interrupts and Flags ............................................................................................ 14-17
➤14.5.4 Traceback RAM .............................................................................................................. 14-17
➤14.6 ECCP Instruction Timing............................................................................................................... 14-19
➤14.6.1 ResetECCP Instruction .................................................................................................. 14-19
➤14.6.2 UpdateMLSE Instruction with Soft Decision .................................................................. 14-19
➤14.6.3 UpdateMLSE Instruction with Hard Decision ................................................................. 14-21
➤14.6.4 UpdateConv Instruction with Soft Decisions .................................................................. 14-22
➤14.6.5 UpdateConv Instruction with Hard Decision ................................................................... 14-23
➤14.6.6 TraceBack Instruction ..................................................................................................... 14-23

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➤15 Interface Guide.......................................................................................................................................... 15-1
➤15.1 Pin Information................................................................................................................................ 15-1
➤15.2 Signal Descriptions ......................................................................................................................... 15-5
➤15.2.1 System Interface .............................................................................................................. 15-5
➤15.2.2 External Memory Interface ............................................................................................... 15-6
➤15.2.3 Serial Interface #1 ............................................................................................................ 15-7
➤15.2.4 PIO/PHIF or Serial Interface #2 and Control I/O Interface ............................................... 15-9
➤15.2.5 Control I/O Interface ....................................................................................................... 15-11
➤15.2.6 JTAG Test Interface ........................................................................................................ 15-11
➤15.3 Resetting DSP161X and DSP162X Devices................................................................................. 15-12
➤15.3.1 Powerup Reset ............................................................................................................... 15-12
➤15.3.2 Using the TAP to Reset the TAP Controller .................................................................... 15-12
➤15.3.3 RSTB Pin Reset ............................................................................................................. 15-13
➤15.4 Mask-Programmable Options ....................................................................................................... 15-14
➤15.4.1 Input Clock Options ........................................................................................................ 15-14
➤15.4.2 ROM Security Options (DSP1617/18/27/28/29 Only) .................................................... 15-14
➤15.5 Additional Electrical Characteristics and Requirements for Crystal.............................................. 15-15
➤A Instruction Encoding....................................................................................................................................A-1
➤A.1 Instruction Encoding Formats ...........................................................................................................A-1
➤A.2 Field Descriptions .............................................................................................................................A-4
➤B Instruction Set Summary.............................................................................................................................B-1
➤goto JA ....................................................................................................................................................... B-1
➤goto B......................................................................................................................................................... B-2
➤if CON goto/call/return................................................................................................................................ B-3
➤call JA......................................................................................................................................................... B-4
➤icall............................................................................................................................................................. B-5
➤do K {.......................................................................................................................................................... B-6
➤redo K......................................................................................................................................................... B-7
➤R = IM16..................................................................................................................................................... B-8
➤SR = IM9 .................................................................................................................................................. B-10
➤R = aS[l].................................................................................................................................................... B-11
➤aT[l] = R.................................................................................................................................................... B-12
➤R = Y ........................................................................................................................................................ B-13
➤Y = R ........................................................................................................................................................ B-14
➤Z : R.......................................................................................................................................................... B-15
➤DR = *(OFFSET)...................................................................................................................................... B-16
➤*(OFFSET) = DR...................................................................................................................................... B-17
➤if CON F2 ................................................................................................................................................. B-18
➤ifc CON F2................................................................................................................................................ B-19
➤F1 Y....................................................................................................................................................... B-20
➤F1 Y = a0[l] ............................................................................................................................................ B-22
➤F1 Y = a1[l] ............................................................................................................................................ B-22
➤F1 x = Y ................................................................................................................................................. B-24
➤F1 y[l] = Y............................................................................................................................................... B-26
➤F1 y = Y x = *pt++[i] ............................................................................................................................ B-28
➤F1 y = a0 x = *pt++[i]........................................................................................................................... B-30
➤F1 y = a1 x = *pt++[i]........................................................................................................................... B-30
➤F1 aT[l] = Y............................................................................................................................................ B-32
➤F1 Y = y[l]............................................................................................................................................... B-34
➤F1 Z : y[l]................................................................................................................................................ B-36

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➤F1 Z : aT[l] ............................................................................................................................................. B-38
➤F1 Z : y x = *pt++[i].............................................................................................................................. B-40
➤aD = aS OP aT......................................................................................................................................... B-42
➤aD = aS OP p........................................................................................................................................... B-43
➤aD = aS<h,l> OP IM16............................................................................................................................. B-44
➤aD = a SHIFT aS ................................................................................................................................... B-46
➤aD = aS SHIFT arM.................................................................................................................................. B-47
➤aD = aS SHIFT IM16................................................................................................................................ B-48
➤aD = exp (aS)........................................................................................................................................... B-49
➤aD = norm (aS, arM) ................................................................................................................................ B-50
➤aD = extracts (aS, arM)............................................................................................................................ B-51
➤aD = extractz (aS, arM)............................................................................................................................ B-51
➤aD = extracts (aS, IM16) .......................................................................................................................... B-52
➤aD = extractz (aS, IM16) .......................................................................................................................... B-52
➤aD = insert (aS, arM)................................................................................................................................ B-53
➤aD = insert (aS, IM16).............................................................................................................................. B-54
➤aD = aS : aaT........................................................................................................................................... B-55
S