Maxim Integrated MAX32665 User manual

MAX32665–MAX32668 USER GUIDE
UG6971; Rev 0; 6/19
Abstract: This user guide provides application developers information on how to use the memory and peripherals of the
MAX32665–MAX32668 microcontroller. Detailed information for all registers and fields in the device are covered.
Guidance is given for managing all the peripherals, clocks, power and startup for the device family.

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MAX32665—MAX32669 User Guide
Table of Contents
1. Overview----------------------------------------------------------------------------------------------------------------- 24
1.1 Block Diagram ---------------------------------------------------------------------------------------------------------------- 25
2. Resource Protection Unit (RPU) ------------------------------------------------------------------------------------ 26
2.1 Instances----------------------------------------------------------------------------------------------------------------------- 26
2.2 Usage --------------------------------------------------------------------------------------------------------------------------- 28
2.2.1 Reset State -------------------------------------------------------------------------------------------------------------------------------- 28
2.2.2 MPU Implementation ------------------------------------------------------------------------------------------------------------------ 28
2.2.3 MPU Protection Fault ------------------------------------------------------------------------------------------------------------------ 28
2.2.4 RPU Protection Fault-------------------------------------------------------------------------------------------------------------------- 28
2.2.5 RPU Fault Handler----------------------------------------------------------------------------------------------------------------------- 28
2.3 Registers----------------------------------------------------------------------------------------------------------------------- 29
2.4 Register Details -------------------------------------------------------------------------------------------------------------- 31
3. Memory, Register Mapping, and Access ------------------------------------------------------------------------- 34
3.1 Memory, Register Mapping, and Access Overview ----------------------------------------------------------------- 34
3.2 Standard Memory Regions------------------------------------------------------------------------------------------------ 37
3.2.1 Code Space -------------------------------------------------------------------------------------------------------------------------------- 37
3.2.2 SRAM Space------------------------------------------------------------------------------------------------------------------------------- 37
3.2.3 Peripheral Space ------------------------------------------------------------------------------------------------------------------------- 38
3.2.4 External RAM Space -------------------------------------------------------------------------------------------------------------------- 38
3.2.5 External Device Space ------------------------------------------------------------------------------------------------------------------ 39
3.2.6 System Area (Private Peripheral Bus) ---------------------------------------------------------------------------------------------- 39
3.2.7 System Area (Vendor Defined) ------------------------------------------------------------------------------------------------------- 39
3.3 Device Memory Instances------------------------------------------------------------------------------------------------- 39
3.3.1 Main Program Flash Memory -------------------------------------------------------------------------------------------------------- 39
3.3.2 Cache Memories ------------------------------------------------------------------------------------------------------------------------- 39
3.3.3 External Memory Cache Controller (EMCC) -------------------------------------------------------------------------------------- 40
3.3.4 Information Block Flash Memory---------------------------------------------------------------------------------------------------- 40
3.3.5 System SRAM ----------------------------------------------------------------------------------------------------------------------------- 40
3.3.6 AES Key and Working Space Memory---------------------------------------------------------------------------------------------- 40
3.3.7 MAA Key and Working Space Memory -------------------------------------------------------------------------------------------- 40
3.3.8 TPU Memory ------------------------------------------------------------------------------------------------------------------------------ 40
3.4 AHB Interfaces --------------------------------------------------------------------------------------------------------------- 40

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3.4.1 Core AHB Interfaces--------------------------------------------------------------------------------------------------------------------- 40
3.4.2 AHB Masters ------------------------------------------------------------------------------------------------------------------------------ 41
3.5 Peripheral Register Map--------------------------------------------------------------------------------------------------- 41
3.5.1 APB Peripheral Base Address Map-------------------------------------------------------------------------------------------------- 41
3.5.2 AHB Peripheral Base Address Map ------------------------------------------------------------------------------------------------- 42
3.6 Error Correction Coding (ECC) Module--------------------------------------------------------------------------------- 43
3.6.1 SRAM --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.2 FLASH --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.3 Cache --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.4 Limitations--------------------------------------------------------------------------------------------------------------------------------- 43
4. System, Power, Clocks, Reset --------------------------------------------------------------------------------------- 50
4.1 Oscillator Sources and Clock Switching -------------------------------------------------------------------------------- 50
4.1.1 Oscillator Inplementation ------------------------------------------------------------------------------------------------------------- 52
4.1.2 96MHz Internal Main High-Speed Oscillator ------------------------------------------------------------------------------------- 52
4.1.3 60MHz Low Power Internal Oscillator --------------------------------------------------------------------------------------------- 52
4.1.4 32MHz Bluetooth Radio Oscillator-------------------------------------------------------------------------------------------------- 52
4.1.5 7.3728MHz Internal Oscillator ------------------------------------------------------------------------------------------------------- 53
4.1.6 32.768kHz External Crystal Oscillator---------------------------------------------------------------------------------------------- 53
4.1.7 8kHz Ultra-Low Power Nano-Ring Internal Oscillator ------------------------------------------------------------------------- 53
4.2 Operating Modes------------------------------------------------------------------------------------------------------------ 54
4.2.1 ACTIVE Mode ----------------------------------------------------------------------------------------------------------------------------- 54
4.2.2 SLEEP Low Power Mode --------------------------------------------------------------------------------------------------------------- 54
4.2.3 DEEPSLEEP Low Power Mode -------------------------------------------------------------------------------------------------------- 56
4.2.4 BACKUP Low Power Mode ------------------------------------------------------------------------------------------------------------ 58
4.3 Device Resets----------------------------------------------------------------------------------------------------------------- 60
4.3.1 Peripheral Reset ------------------------------------------------------------------------------------------------------------------------- 61
4.3.2 Soft Reset ---------------------------------------------------------------------------------------------------------------------------------- 61
4.3.3 System Reset------------------------------------------------------------------------------------------------------------------------------ 62
4.3.4 Power-On Reset -------------------------------------------------------------------------------------------------------------------------- 62
4.4 Cache --------------------------------------------------------------------------------------------------------------------------- 62
4.5 Instruction Cache Controller---------------------------------------------------------------------------------------------- 63
4.5.1 Enabling ICC0/ICC1/SFCC -------------------------------------------------------------------------------------------------------------- 63
4.5.2 Flushing the ICC0/ICC1/SFCC Cache ------------------------------------------------------------------------------------------------ 64
4.5.3 Flushing SRCC Cache -------------------------------------------------------------------------------------------------------------------- 64
4.6 Instruction Cache Controller Registers--------------------------------------------------------------------------------- 64
4.7 External RAM SPIXR Cache Controller (SRCC) ------------------------------------------------------------------------ 66

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4.8 RAM Memory Management---------------------------------------------------------------------------------------------- 67
4.8.1 RAM Zeroization ------------------------------------------------------------------------------------------------------------------------- 67
4.8.2 RAM Low Power Modes --------------------------------------------------------------------------------------------------------------- 67
4.9 Miscellaneous Control Registers----------------------------------------------------------------------------------------- 68
4.10 Miscellaneous Control Registers Details------------------------------------------------------------------------------- 68
4.11 Single Inductor Multiple Output (SIMO) Power Supply ------------------------------------------------------------ 71
4.11.1 Power Supply Monitor------------------------------------------------------------------------------------------------------------------ 71
4.12 Single Inductor Multiple Output (SIMO) Registers ------------------------------------------------------------------ 72
4.13 Single Inductor Multiple Output (SIMO) Registers Details -------------------------------------------------------- 73
4.14 Power Sequencer and Always-On Domain Registers --------------------------------------------------------------- 78
4.15 Power Sequencer and Always-On Domain Register Details------------------------------------------------------- 79
4.16 Global Control Registers (GCR)------------------------------------------------------------------------------------------- 85
4.17 Global Control Register Details (GCR) ---------------------------------------------------------------------------------- 86
4.18 Function Control Registers ---------------------------------------------------------------------------------------------- 113
4.19 Function Control Register Details ------------------------------------------------------------------------------------- 113
4.20 AES Key Registers---------------------------------------------------------------------------------------------------------- 114
4.21 AES Key Register Details ------------------------------------------------------------------------------------------------- 114
5. Interrupts and Exceptions ------------------------------------------------------------------------------------------115
5.1 Features---------------------------------------------------------------------------------------------------------------------- 115
5.2 Interrupt Vector Table --------------------------------------------------------------------------------------------------- 115
6. General-Purpose I/O and Alternate Function Pins (GPIO)---------------------------------------------------119
6.1 Instances--------------------------------------------------------------------------------------------------------------------- 119
6.2 Usage ------------------------------------------------------------------------------------------------------------------------- 123
6.2.1 Reset State ------------------------------------------------------------------------------------------------------------------------------ 123
6.2.2 Input Mode Configuration----------------------------------------------------------------------------------------------------------- 123
6.2.3 Output Mode Configuration -------------------------------------------------------------------------------------------------------- 123
6.2.4 Alternate Function Configuration ------------------------------------------------------------------------------------------------- 123
6.3 Configuring GPIO (External) Interrupts------------------------------------------------------------------------------- 123
6.3.1 GPIO Interrupt Handling ------------------------------------------------------------------------------------------------------------- 124
6.3.2 Using GPIO for Wakeup from Low Power Modes ----------------------------------------------------------------------------- 124
6.4 Registers--------------------------------------------------------------------------------------------------------------------- 125
6.5 Register Details ------------------------------------------------------------------------------------------------------------ 126
7. Flash Controller (FLC) ------------------------------------------------------------------------------------------------134
7.1 Instances--------------------------------------------------------------------------------------------------------------------- 134
7.2 Usage ------------------------------------------------------------------------------------------------------------------------- 134

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7.2.1 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 135
7.2.2 Lock Protection------------------------------------------------------------------------------------------------------------------------- 135
7.2.3 Flash Write Width --------------------------------------------------------------------------------------------------------------------- 135
7.2.4 Flash Write ------------------------------------------------------------------------------------------------------------------------------ 136
7.2.5 Page Erase------------------------------------------------------------------------------------------------------------------------------- 136
7.2.6 Mass Erase ------------------------------------------------------------------------------------------------------------------------------ 137
7.3 Flash Error Correction Coding ------------------------------------------------------------------------------------------ 137
7.4 Flash Controller Registers ----------------------------------------------------------------------------------------------- 137
7.5 Flash Controller Register Details--------------------------------------------------------------------------------------- 138
8. External Memory -----------------------------------------------------------------------------------------------------142
8.1 Overview--------------------------------------------------------------------------------------------------------------------- 142
8.2 SPI Execute-in-Place Flash (SPIXF)------------------------------------------------------------------------------------- 142
8.2.1 SPIXF Master Controller-------------------------------------------------------------------------------------------------------------- 143
8.2.2 SPIXF Master---------------------------------------------------------------------------------------------------------------------------- 158
8.3 SPI Execute-in-Place RAM (SPIXR)------------------------------------------------------------------------------------- 167
8.3.1 SPIXR Master Controller Registers ------------------------------------------------------------------------------------------------ 168
8.3.2 SPIXR Register Details ---------------------------------------------------------------------------------------------------------------- 169
8.4 SPIXR Cache Controller (SRCC) ----------------------------------------------------------------------------------------- 178
8.4.1 Features---------------------------------------------------------------------------------------------------------------------------------- 178
8.4.2 Enabling the SRCC --------------------------------------------------------------------------------------------------------------------- 178
8.4.3 Disabling the SRCC -------------------------------------------------------------------------------------------------------------------- 178
8.4.4 SRCC Registers-------------------------------------------------------------------------------------------------------------------------- 179
8.4.5 SRCC Register Details ----------------------------------------------------------------------------------------------------------------- 179
8.5 Secure Digital Host Controller------------------------------------------------------------------------------------------ 181
8.5.1 Instances--------------------------------------------------------------------------------------------------------------------------------- 182
8.5.2 SDHC Peripheral Clock Selection--------------------------------------------------------------------------------------------------- 183
8.5.3 Usage ------------------------------------------------------------------------------------------------------------------------------------- 183
8.5.4 SD Command Generation ----------------------------------------------------------------------------------------------------------- 184
8.5.5 SDHC Registers ------------------------------------------------------------------------------------------------------------------------- 185
8.5.6 SDHC Register Details ---------------------------------------------------------------------------------------------------------------- 186
9. Standard DMA (DMAC)----------------------------------------------------------------------------------------------222
9.1 Instances--------------------------------------------------------------------------------------------------------------------- 222
9.2 DMA Channel Operation (DMACH) ----------------------------------------------------------------------------------- 223
9.2.1 DMA Channel Arbitration and DMA Bursts ------------------------------------------------------------------------------------- 223
9.2.2 DMA Source and Destination Addressing --------------------------------------------------------------------------------------- 224
Data Movement From Source to DMA------------------------------------------------------------------------------------------------------- 226

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9.2.3 Data Movement From the DMA to Destination ------------------------------------------------------------------------------- 226
9.3 Usage ------------------------------------------------------------------------------------------------------------------------- 227
9.4 Count-To-Zero (CTZ) Condition ---------------------------------------------------------------------------------------- 227
9.5 Chaining Buffers ----------------------------------------------------------------------------------------------------------- 228
9.6 DMA Interrupts ------------------------------------------------------------------------------------------------------------ 230
9.7 Channel Timeout Detect------------------------------------------------------------------------------------------------- 230
9.8 Memory-to-Memory DMA ---------------------------------------------------------------------------------------------- 231
9.9 DMAC Registers------------------------------------------------------------------------------------------------------------ 231
9.10 DMAC Register Details --------------------------------------------------------------------------------------------------- 231
9.11 DMA Channel Registers-------------------------------------------------------------------------------------------------- 232
9.12 DMAC Channel Registers ------------------------------------------------------------------------------------------------ 232
9.13 DMA Channel Register Details ----------------------------------------------------------------------------------------- 233
10. Cyclic Redundancy Check Engine (CRC)-----------------------------------------------------------------------238
10.1 Instances--------------------------------------------------------------------------------------------------------------------- 239
10.2 Linear Feedback Shift Register (LFSR) -------------------------------------------------------------------------------- 239
10.3 Registers --------------------------------------------------------------------------------------------------------------------- 240
10.4 Register Details ------------------------------------------------------------------------------------------------------------ 241
11. Analog to Digital Converter and Comparators (ADC)------------------------------------------------------246
11.1 Features---------------------------------------------------------------------------------------------------------------------- 246
11.2 Instances--------------------------------------------------------------------------------------------------------------------- 246
11.3 Architecture----------------------------------------------------------------------------------------------------------------- 247
11.4 Clock Configuration ------------------------------------------------------------------------------------------------------- 249
11.5 Power-Up Sequence ------------------------------------------------------------------------------------------------------ 250
11.6 Conversion ------------------------------------------------------------------------------------------------------------------ 250
11.7 Reference Scaling and Input Scaling ---------------------------------------------------------------------------------- 250
11.7.1 AIN0 –AIN7 Scale Limitations------------------------------------------------------------------------------------------------------ 251
11.7.2 Scale Limitations for All Other Input Channels--------------------------------------------------------------------------------- 251
11.7.3 Data Conversion Output Alignment ---------------------------------------------------------------------------------------------- 251
11.7.4 Data Conversion Value Equations------------------------------------------------------------------------------------------------- 252
11.7.5 Data Limits and Out of Range Interrupts---------------------------------------------------------------------------------------- 253
11.7.6 Power-Down Sequence--------------------------------------------------------------------------------------------------------------- 254
11.8 Comparator Operation--------------------------------------------------------------------------------------------------- 254
11.9 Registers --------------------------------------------------------------------------------------------------------------------- 255
11.10 Register Details ------------------------------------------------------------------------------------------------------------ 255
12. UART------------------------------------------------------------------------------------------------------------------260

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12.1 Instances--------------------------------------------------------------------------------------------------------------------- 260
12.2 UART Frame----------------------------------------------------------------------------------------------------------------- 260
12.3 UART Interrupts------------------------------------------------------------------------------------------------------------ 261
12.4 UART Baud Rate Clock Source------------------------------------------------------------------------------------------ 261
12.5 UART Baud Rate Calculation-------------------------------------------------------------------------------------------- 261
12.6 UART Configuration and Operation----------------------------------------------------------------------------------- 263
12.7 Wakeup Time--------------------------------------------------------------------------------------------------------------- 263
12.8 Hardware Flow Control -------------------------------------------------------------------------------------------------- 263
12.9 Registers --------------------------------------------------------------------------------------------------------------------- 263
12.10 Register Details ------------------------------------------------------------------------------------------------------------ 264
13. I2C Master/Slave Serial Communications Peripheral (I2C) -----------------------------------------------272
13.1 I2C Master/Slave Features----------------------------------------------------------------------------------------------- 274
13.2 Instances--------------------------------------------------------------------------------------------------------------------- 274
13.3 I2C Overview ---------------------------------------------------------------------------------------------------------------- 275
13.3.1 I2C Bus Terminology------------------------------------------------------------------------------------------------------------------- 275
13.3.2 I2C Transfer Protocol Operation --------------------------------------------------------------------------------------------------- 275
13.3.3 START and STOP Conditions -------------------------------------------------------------------------------------------------------- 275
13.3.4 Master Operation --------------------------------------------------------------------------------------------------------------------- 275
13.3.5 Acknowledge and Not Acknowledge --------------------------------------------------------------------------------------------- 275
13.3.6 Bit Transfer Process ------------------------------------------------------------------------------------------------------------------- 276
13.4 I2C Configuration and Usage-------------------------------------------------------------------------------------------- 277
13.4.1 SCL and SDA Bus Drivers ------------------------------------------------------------------------------------------------------------- 277
13.4.2 SCL Clock Configurations ------------------------------------------------------------------------------------------------------------ 277
13.4.3 SCL Clock Generation for Standard, Fast and Fast-Plus Modes ----------------------------------------------------------- 277
13.4.4 SCL Clock Generation for Hs-mode------------------------------------------------------------------------------------------------ 278
13.4.5 I2C Addressing -------------------------------------------------------------------------------------------------------------------------- 279
13.4.6 I2C Master Mode Operation -------------------------------------------------------------------------------------------------------- 280
13.4.7 I2C Slave Mode Operation ----------------------------------------------------------------------------------------------------------- 283
13.4.8 I2C Interrupt Sources ------------------------------------------------------------------------------------------------------------------ 288
13.4.9 TX FIFO and RX FIFO ------------------------------------------------------------------------------------------------------------------ 288
13.4.10 TX FIFO Preloading ---------------------------------------------------------------------------------------------------------------- 289
13.4.11 Interactive Receive Mode (IRXM) --------------------------------------------------------------------------------------------- 290
13.4.12 Clock Stretching -------------------------------------------------------------------------------------------------------------------- 291
13.4.13 I2C Bus Timeout -------------------------------------------------------------------------------------------------------------------- 291
13.4.14 I2C DMA Control-------------------------------------------------------------------------------------------------------------------- 292
13.5 Registers --------------------------------------------------------------------------------------------------------------------- 292

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13.6 Register Details ------------------------------------------------------------------------------------------------------------ 293
14. Quad Serial Peripheral Interface (SPI)-------------------------------------------------------------------------306
14.1 Instances--------------------------------------------------------------------------------------------------------------------- 307
14.2 SPI Formats ----------------------------------------------------------------------------------------------------------------- 308
14.2.1 Four-Wire SPI --------------------------------------------------------------------------------------------------------------------------- 308
14.2.2 Three-Wire SPI-------------------------------------------------------------------------------------------------------------------------- 309
14.3 Pin Configuration ---------------------------------------------------------------------------------------------------------- 310
14.3.1 QSPIn Alternate Function Mapping----------------------------------------------------------------------------------------------- 310
14.3.2 Four-wire Format Configuration--------------------------------------------------------------------------------------------------- 310
14.3.3 Three-Wire Format Configuration ------------------------------------------------------------------------------------------------ 310
14.3.4 Dual Mode Format Configuration------------------------------------------------------------------------------------------------- 311
14.3.5 Quad Mode Format Pin Configuration------------------------------------------------------------------------------------------- 311
14.4 QSPI Clock Configuration ------------------------------------------------------------------------------------------------ 311
14.4.1 Serial Clock ------------------------------------------------------------------------------------------------------------------------------ 311
14.4.2 SPI Peripheral Clock ------------------------------------------------------------------------------------------------------------------- 312
14.4.3 Master Mode Serial Clock Generation ------------------------------------------------------------------------------------------- 312
14.4.4 Clock Phase and Polarity Control-------------------------------------------------------------------------------------------------- 312
14.4.5 QSPIn FIFOs ----------------------------------------------------------------------------------------------------------------------------- 313
14.4.6 QSPI Interrupts and Wakeups ------------------------------------------------------------------------------------------------------ 313
14.5 Registers --------------------------------------------------------------------------------------------------------------------- 314
14.6 Register Details ------------------------------------------------------------------------------------------------------------ 315
15. HTimer (HT) ---------------------------------------------------------------------------------------------------------324
15.1 Overview--------------------------------------------------------------------------------------------------------------------- 324
15.2 Alarm Functions------------------------------------------------------------------------------------------------------------ 324
15.2.1 Long-Interval Alarm------------------------------------------------------------------------------------------------------------------- 324
15.2.2 Short-Interval Alarm ------------------------------------------------------------------------------------------------------------------ 324
15.3 Register Access Control -------------------------------------------------------------------------------------------------- 325
15.3.1 Register Write Protection ----------------------------------------------------------------------------------------------------------- 325
15.3.2 Register Read Protection ------------------------------------------------------------------------------------------------------------ 325
15.3.3 Count Register Access ---------------------------------------------------------------------------------------------------------------- 325
15.3.4 Alarm Register Access ---------------------------------------------------------------------------------------------------------------- 325
15.4 Registers --------------------------------------------------------------------------------------------------------------------- 326
15.5 Register Details ------------------------------------------------------------------------------------------------------------ 326
16. Timers ----------------------------------------------------------------------------------------------------------------329
16.1 Features---------------------------------------------------------------------------------------------------------------------- 329
16.2 Basic Operation ------------------------------------------------------------------------------------------------------------ 329

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16.3 Timer Pin Functionality--------------------------------------------------------------------------------------------------- 330
16.4 One-Shot Mode (000b)--------------------------------------------------------------------------------------------------- 330
16.4.1 One-Shot Mode Timer Period ------------------------------------------------------------------------------------------------------ 331
16.4.2 One-Shot Mode Configuration ----------------------------------------------------------------------------------------------------- 331
16.5 Continuous Mode (001b)------------------------------------------------------------------------------------------------ 331
16.5.1 Continuous Mode Timer Period---------------------------------------------------------------------------------------------------- 332
16.5.2 Continuous Mode Configuration -------------------------------------------------------------------------------------------------- 333
16.6 Counter Mode (010b) ---------------------------------------------------------------------------------------------------- 334
16.6.1 Counter Mode Timer Period -------------------------------------------------------------------------------------------------------- 335
16.6.2 Counter Mode Configuration ------------------------------------------------------------------------------------------------------- 335
16.7 PWM Mode (011b)-------------------------------------------------------------------------------------------------------- 336
16.7.1 PWM Mode Timer Period ----------------------------------------------------------------------------------------------------------- 336
16.7.2 PWM Mode Configuration ---------------------------------------------------------------------------------------------------------- 336
16.8 Capture Mode (100b) ---------------------------------------------------------------------------------------------------- 338
16.8.1 Capture Mode Timer Period -------------------------------------------------------------------------------------------------------- 339
16.8.2 Capture Mode Configuration ------------------------------------------------------------------------------------------------------- 339
16.9 Compare Mode (101b)--------------------------------------------------------------------------------------------------- 339
16.9.1 Compare Mode Timer Period------------------------------------------------------------------------------------------------------- 340
16.9.2 Compare Mode Configuration ----------------------------------------------------------------------------------------------------- 341
16.10 Gated Mode (110b) ------------------------------------------------------------------------------------------------------- 342
16.10.1 Gated Mode Timer Period------------------------------------------------------------------------------------------------------- 343
16.10.2 Gated Mode Configuration ----------------------------------------------------------------------------------------------------- 343
16.11 Capture/Compare Mode (111b) --------------------------------------------------------------------------------------- 344
16.11.1 Capture/Compare Timer Period ----------------------------------------------------------------------------------------------- 344
16.11.2 Capture/Compare Configuration ---------------------------------------------------------------------------------------------- 344
16.12 Timer Registers------------------------------------------------------------------------------------------------------------- 345
17. Pulse Train Engine (PT) -------------------------------------------------------------------------------------------349
17.1 Instances--------------------------------------------------------------------------------------------------------------------- 349
17.2 Pulse Train Engine Features--------------------------------------------------------------------------------------------- 349
17.3 Engine ------------------------------------------------------------------------------------------------------------------------ 349
17.3.1 Pulse Train Output Modes ---------------------------------------------------------------------------------------------------------- 350
17.4 Enabling and Disabling a Pulse Train Output ----------------------------------------------------------------------- 351
17.5 Atomic Pulse Train Output Enable and Disable -------------------------------------------------------------------- 351
17.5.1 Pulse Train Atomic Enable----------------------------------------------------------------------------------------------------------- 351
17.5.2 Pulse Train Atomic Disable---------------------------------------------------------------------------------------------------------- 352
17.6 Pulse Train Halt and Disable -------------------------------------------------------------------------------------------- 352

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17.7 Pulse Train Interrupts ---------------------------------------------------------------------------------------------------- 352
17.8 Registers --------------------------------------------------------------------------------------------------------------------- 352
17.9 Register Details ------------------------------------------------------------------------------------------------------------ 354
17.9.1 Pulse Train Engine Safe Enable Register----------------------------------------------------------------------------------------- 363
17.9.2 Pulse Train Engine Safe Disable Register---------------------------------------------------------------------------------------- 364
18. Real-Time Clock (RTC)---------------------------------------------------------------------------------------------369
18.1 Overview--------------------------------------------------------------------------------------------------------------------- 369
18.2 Instances--------------------------------------------------------------------------------------------------------------------- 370
18.3 Register Access Control -------------------------------------------------------------------------------------------------- 370
18.3.1 RTC_SEC and RTC_SSEC Read Access Control ---------------------------------------------------------------------------------- 370
18.3.2 RTC Write Access Control------------------------------------------------------------------------------------------------------------ 371
18.4 RTC Alarm Functions------------------------------------------------------------------------------------------------------ 371
18.4.1 Time-of-Day Alarm -------------------------------------------------------------------------------------------------------------------- 371
18.4.2 Sub-Second Alarm --------------------------------------------------------------------------------------------------------------------- 372
18.4.3 RTC Interrupt and Wakeup Configuration -------------------------------------------------------------------------------------- 373
18.4.4 Square Wave Output ----------------------------------------------------------------------------------------------------------------- 373
18.5 RTC Calibration------------------------------------------------------------------------------------------------------------- 374
18.6 Registers --------------------------------------------------------------------------------------------------------------------- 376
18.7 Register Details ------------------------------------------------------------------------------------------------------------ 376
19. Watchdog Timer (WDT) ------------------------------------------------------------------------------------------380
19.1 Features---------------------------------------------------------------------------------------------------------------------- 381
19.2 Usage ------------------------------------------------------------------------------------------------------------------------- 381
19.3 Interrupt and Reset Period Timeout Configuration--------------------------------------------------------------- 382
19.4 Timed Access Protection------------------------------------------------------------------------------------------------- 382
19.5 Enabling the Watchdog Timer------------------------------------------------------------------------------------------ 383
19.5.1 Enable sequence ----------------------------------------------------------------------------------------------------------------------- 383
19.6 Disabling the Watchdog Timer----------------------------------------------------------------------------------------- 383
19.6.1 Manual Disable ------------------------------------------------------------------------------------------------------------------------ 383
19.6.2 Automatic Disable--------------------------------------------------------------------------------------------------------------------- 383
19.7 Resetting the Watchdog Timer----------------------------------------------------------------------------------------- 383
19.7.1 Reset Sequence------------------------------------------------------------------------------------------------------------------------- 383
19.8 Detection of a Watchdog Reset Event-------------------------------------------------------------------------------- 383
19.9 Registers --------------------------------------------------------------------------------------------------------------------- 383
19.10 Register Details ------------------------------------------------------------------------------------------------------------ 384
20. 1-Wire Master (OWM)--------------------------------------------------------------------------------------------387

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20.1 Instances--------------------------------------------------------------------------------------------------------------------- 387
20.2 Pins and Configuration--------------------------------------------------------------------------------------------------- 388
20.2.1 Pin Configuration ---------------------------------------------------------------------------------------------------------------------- 388
20.2.2 1-Wire I/O (OWM_IO)---------------------------------------------------------------------------------------------------------------- 388
20.2.3 Pullup Enable (OWM_PE) ----------------------------------------------------------------------------------------------------------- 388
20.2.4 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 388
20.3 1-Wire Protocol ------------------------------------------------------------------------------------------------------------ 389
20.3.1 Networking Layers -------------------------------------------------------------------------------------------------------------------- 389
20.3.2 Read ROM Command ---------------------------------------------------------------------------------------------------------------- 393
20.3.3 Skip ROM and Overdrive Skip ROM Commands ------------------------------------------------------------------------------- 393
20.3.4 Match ROM and Overdrive Match ROM Commands ------------------------------------------------------------------------ 394
20.3.5 Search ROM Command -------------------------------------------------------------------------------------------------------------- 394
20.3.6 Search ROM Accelerator Operation ---------------------------------------------------------------------------------------------- 394
20.3.7 Resume Communication Command ---------------------------------------------------------------------------------------------- 395
20.4 1-Wire Operation---------------------------------------------------------------------------------------------------------- 396
20.4.1 Resetting the OWM ------------------------------------------------------------------------------------------------------------------- 396
20.5 1-Wire Data Reads -------------------------------------------------------------------------------------------------------- 396
20.5.1 Reading a Single Bit Value from the 1-Wire Bus ------------------------------------------------------------------------------ 396
20.5.2 Reading an 8-Bit Value from the 1-Wire Bus----------------------------------------------------------------------------------- 397
20.6 Registers --------------------------------------------------------------------------------------------------------------------- 397
20.7 Register Details ------------------------------------------------------------------------------------------------------------ 398
21. USB 2.0 High-Speed (USBHS) Host Interface with PHY----------------------------------------------------402
21.1 Instances--------------------------------------------------------------------------------------------------------------------- 402
21.2 USBHS Bus Signals--------------------------------------------------------------------------------------------------------- 403
21.3 USBHS Device Endpoints------------------------------------------------------------------------------------------------- 403
21.4 USBHS Reset and Clock -------------------------------------------------------------------------------------------------- 404
21.5 USBHS SUSPEND Mode and RESUME States------------------------------------------------------------------------ 404
21.6 Packet Size ------------------------------------------------------------------------------------------------------------------ 405
21.7 Endpoint 0 Control Transactions -------------------------------------------------------------------------------------- 405
21.7.1 Endpoint 0 Error Handling----------------------------------------------------------------------------------------------------------- 405
21.8 Bulk Endpoints Operation and Options ------------------------------------------------------------------------------ 405
21.8.1 Bulk IN Endpoints---------------------------------------------------------------------------------------------------------------------- 405
21.8.2 Bulk OUT Endpoints ------------------------------------------------------------------------------------------------------------------- 406
21.9 Interrupt Endpoints------------------------------------------------------------------------------------------------------- 407
21.9.1 Interrupt IN Endpoints---------------------------------------------------------------------------------------------------------------- 407
21.9.2 Interrupt OUT Endpoints------------------------------------------------------------------------------------------------------------- 407

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21.10 Isochronous Endpoints--------------------------------------------------------------------------------------------------- 407
21.10.1 Isochronous IN Endpoints ------------------------------------------------------------------------------------------------------- 407
21.10.2 Isochronous OUT Endpoints ---------------------------------------------------------------------------------------------------- 408
21.11 USBHS Device Registers-------------------------------------------------------------------------------------------------- 409
21.12 USBHS Device Register Details ----------------------------------------------------------------------------------------- 410
21.12.2 Endpoint Register Access Control --------------------------------------------------------------------------------------------- 416
21.12.3 USBHS IN Endpoint Maximum Packet Size Registers--------------------------------------------------------------------- 417
21.12.4 USBHS IN Endpoint Lower Control and Status Registers ---------------------------------------------------------------- 417
21.12.5 USBHS Endpoint 0 Control Status Register---------------------------------------------------------------------------------- 418
21.12.6 USBHS IN Endpoint Upper Control Registers ------------------------------------------------------------------------------- 419
22. Bluetooth 5 Low Energy (LE) Radio ----------------------------------------------------------------------------426
22.1 Power-Efficient Design--------------------------------------------------------------------------------------------------- 426
22.2 Bluetooth Hardware Accelerator-------------------------------------------------------------------------------------- 426
22.3 Arm Cordio®-B50 Software Stack-------------------------------------------------------------------------------------- 426
22.4 Pins---------------------------------------------------------------------------------------------------------------------------- 428
22.5 Configuration--------------------------------------------------------------------------------------------------------------- 428
22.6 Documentation ------------------------------------------------------------------------------------------------------------ 428
23. Trust Protection Unit (TPU)--------------------------------------------------------------------------------------429
23.1 Dedicated Cryptographic DMA Engine (CDMA)-------------------------------------------------------------------- 430
23.1.1 FIFOs -------------------------------------------------------------------------------------------------------------------------------------- 431
23.1.2 Direct FIFO Access --------------------------------------------------------------------------------------------------------------------- 432
23.1.3 Cache Security-------------------------------------------------------------------------------------------------------------------------- 432
23.2 Block Cipher Accelerator ------------------------------------------------------------------------------------------------ 432
23.2.1 Cipher Key Storage and Initialization--------------------------------------------------------------------------------------------- 434
23.2.2 Operation-------------------------------------------------------------------------------------------------------------------------------- 435
23.3 Hash Function Accelerator ---------------------------------------------------------------------------------------------- 435
23.3.1 Last Message Block Padding ------------------------------------------------------------------------------------------------------- 436
23.4 CRC Engine (Galois Field Accelerator) -------------------------------------------------------------------------------- 437
23.5 Hamming Code Accelerator--------------------------------------------------------------------------------------------- 437
23.6 Modular Arithmetic Accelerator--------------------------------------------------------------------------------------- 439
23.6.1 Operation-------------------------------------------------------------------------------------------------------------------------------- 440
23.6.2 MAA Memory--------------------------------------------------------------------------------------------------------------------------- 440
23.7 True Random Number Generation------------------------------------------------------------------------------------ 442
23.8 Registers --------------------------------------------------------------------------------------------------------------------- 442
23.8.1 Write Access ---------------------------------------------------------------------------------------------------------------------------- 443
23.8.2 Read Access ----------------------------------------------------------------------------------------------------------------------------- 443

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23.9 Register Details ------------------------------------------------------------------------------------------------------------ 444
24. Revision History ----------------------------------------------------------------------------------------------------457
List of Figures
Figure 1-1: MAX32665—MAX32668 Block Diagram..................................................................................................................25
Figure 3-1: Code Memory Mapping...........................................................................................................................................35
Figure 3-2: Data Memory Mapping ...........................................................................................................................................36
Figure 4-1: Clock Block Diagram ................................................................................................................................................51
Figure 4-2: Example 32MHz Crystal Capacitor Determination ..................................................................................................53
Figure 4-3: SLEEP Mode Clock Control.......................................................................................................................................55
Figure 4-4: DEEPSLEEP Clock Control.........................................................................................................................................57
Figure 4-5: BACKUP Mode Clock Control...................................................................................................................................59
Figure 4-6: MAX32665—MAX32668 Cache Controllers Control ...............................................................................................63
Figure 8-1. Simplified SPIXF Block Diagram .............................................................................................................................143
Figure 8-2. Simplified Block Diagram.......................................................................................................................................144
Figure 8-3. SPIXFC Transaction Delay ......................................................................................................................................149
Figure 8-4. Supported SPI configuration..................................................................................................................................159
Figure 8-5. SPIXFM Delay Configuration..................................................................................................................................160
Figure 8-6. Simplified SPIXR Block Diagram.............................................................................................................................168
Figure 8-7: SDHC Block Diagram ..............................................................................................................................................182
Figure 8-8: SD Bus Protocol - No Response and No Data Operations......................................................................................183
Figure 8-9: SD Bus Protocol - Multi-Block Read Operation......................................................................................................184
Figure 8-10: SD Bus Protocol - Multi Block Write Operation...................................................................................................184
Figure 9-1: DMA Block-Chaining Flowchart .............................................................................................................................229
Figure 10-1: Galois Field CRC and LFSR Architecture...............................................................................................................240
Figure 11-1: Analog to Digital Converter Block Diagram .........................................................................................................248
Figure 11-2: ADC Limit Engine .................................................................................................................................................253
Figure 12-1: UART Frame Diagram ..........................................................................................................................................260
Figure 13-1: I2C Block Diagram.................................................................................................................................................273
Figure 13-2: I2C Write Data Transfer........................................................................................................................................276
Figure 13-3: I2C SCL Timing for Standard, Fast, and Fast-Plus Modes .....................................................................................278
Figure 14-1: QSPI Block Diagram .............................................................................................................................................307
Figure 14-2: 4-Wire SPI Connection Diagram ..........................................................................................................................309
Figure 14-3: Generic 3-Wire SPI Master to Slave Connection .................................................................................................310
Figure 14-4: Dual Mode SPI Connection Diagram....................................................................................................................311
Figure 14-5: SCK Clock Rate Control ........................................................................................................................................312
Figure 14-6: SPI Clock Polarity .................................................................................................................................................313
Figure 16-1: One-Shot Mode Diagram.....................................................................................................................................330
Figure 16-2: Continuous Mode Diagram..................................................................................................................................332
Figure 16-3: Counter Mode Diagram .......................................................................................................................................334
Figure 16-4: Capture Mode Diagram .......................................................................................................................................338
Figure 16-5: Counter Mode Diagram .......................................................................................................................................340
Figure 16-6: Gated Mode Diagram ..........................................................................................................................................342
Figure 18-1. MAX32665―MAX32668 RTC Block Diagram (12-bit Sub-Second Counter) ........................................................369
Figure 18-2. RTC Busy/Ready Signal Timing.............................................................................................................................371
Figure 18-3. RTC Interrupt/Wakeup Diagram Wakeup Function.............................................................................................373
Figure 18-4. Internal Implementation of Digital Trim, 4kHz ....................................................................................................375
Figure 19-1: Watchdog Timer Block Diagram ..........................................................................................................................381
Figure 20-1: 1-Wire Signal Interface ........................................................................................................................................389

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Figure 20-2: 1-Wire Reset Pulse...............................................................................................................................................390
Figure 20-3: 1-Wire Write Time Slot........................................................................................................................................391
Figure 20-4: 1-Wire Read Time Slot.........................................................................................................................................391
Figure 20-5: 1-Wire ROM ID Fields ..........................................................................................................................................392
Figure 22-1: MAX32665—MAX32668 Bluetooth Stack Overview ...........................................................................................427
Figure 23-1. Cryptographic Accelerator Block Diagram...........................................................................................................430
Figure 23-2. DMA Block Diagram.............................................................................................................................................431
Figure 23-3. Block Cipher Block Diagram.................................................................................................................................433
Figure 23-4. Block Cipher Diagram ..........................................................................................................................................436
Figure 23-5. Hamming XOR Calculations .................................................................................................................................438

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List of Tables
Table 2-1: Dual Mapped APB Peripherals ..................................................................................................................................26
Table 2-2. MAX32665—MAX32668 Master Permission Bits .....................................................................................................26
Table 2-3: MAX32665—MAX32668 AHB Slaves ........................................................................................................................27
Table 2-4. MAX32665—MAX32668 AHB Master/Slave Interconnect Matrix............................................................................27
Table 2-5: RPU APB Register Offsets, Names, Access, and Descriptions ...................................................................................29
Table 2-6: RPU AHB Slave Register Addresses, Names, Access, and Descriptions ....................................................................30
Table 2-7: RPU APB Slave Permission Registers.........................................................................................................................31
Table 2-8: RPU AHB Slave Permission Register..........................................................................................................................33
Table 3-1: APB Peripheral Base Address Map............................................................................................................................41
Table 3-2: AHB Peripheral Base Address Map ...........................................................................................................................43
Table 3-3: Error Correction Coding (ECC) Enable Register.........................................................................................................44
Table 3-4: Error Correction Coding (ECC) Error Register ...........................................................................................................44
Table 3-5: Correctable Error Detected Register.........................................................................................................................46
Table 3-6: Error Correction Coding (ECC) Interrupt Enable Register .........................................................................................47
Table 3-7: Error Correction Coding (ECC) Address Register.......................................................................................................48
Table 4-1: Wakeup Sources .......................................................................................................................................................54
Table 4-2: Reset and Low Power Mode Effects .........................................................................................................................61
Table 4-3: Instruction Cache Controller Register Summary.......................................................................................................64
Table 4-4: SPIXF Cache Controller Register Summary ...............................................................................................................64
Table 4-5: ICCn Cache ID Register..............................................................................................................................................64
Table 4-6: ICCn Memory Size Register.......................................................................................................................................65
Table 4-7: ICCn Cache Control Register .....................................................................................................................................65
Table 4-8: ICCn Invalidate Register ............................................................................................................................................65
Table 4-9: SFCC Cache ID Register .............................................................................................................................................65
Table 4-10: SFCC Memory Size Register ....................................................................................................................................66
Table 4-11: SFCC Cache Control Register...................................................................................................................................66
Table 4-12: SFCC Invalidate Register .........................................................................................................................................66
Table 4-13 RAM Block Size and Base Address ...........................................................................................................................67
Table 4-14 Miscellaneous Control Register Summary ...............................................................................................................68
Table 4-15: Error Correction Coding (ECC) Enable Register.......................................................................................................68
Table 4-16: SQWOUT and PDOWN Output Enable Register......................................................................................................69
Table 4-17: Comparator Enable Register...................................................................................................................................69
Table 4-18: Control Register ......................................................................................................................................................70
Table 4-19: SIMO Power Supply Device Pin Connectivity..........................................................................................................71
Table 4-20: SIMO Controller Register Summary........................................................................................................................72
Table 4-21: Buck Voltage Regulator A Control Register ............................................................................................................73
Table 4-22: Buck Voltage Regulator B Control Register.............................................................................................................73
Table 4-23: Buck Voltage Regulator C Control Register.............................................................................................................74
Table 4-24: Buck Voltage Regulator D Control Register ............................................................................................................74
Table 4-25: High Side FET Peak Current VREGO_A VREGO_B Register......................................................................................74
Table 4-26: High Side FET Peak Current VREGO_C VREGO_D Register .....................................................................................75
Table 4-27: Maximum High Side FET Time On Register.............................................................................................................75
Table 4-28: Buck Cycle Count VREGO_A Register......................................................................................................................75
Table 4-29: Buck Cycle Count VREGO_B Register......................................................................................................................75
Table 4-30: Buck Cycle Count VREGO_C Register......................................................................................................................76
Table 4-31: Buck Cycle Count VREGO_D Register......................................................................................................................76
Table 4-32: Buck Cycle Count Alert VREGO_A Register .............................................................................................................76
Table 4-33: Buck Cycle Count Alert VREGO_B Register .............................................................................................................76
Table 4-34: Buck Cycle Count Alert VREGO_C Register .............................................................................................................76
Table 4-35: Buck Cycle Count Alert VREGO_D Register.............................................................................................................77

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Table 4-36: Buck Regulator Output Ready Register...................................................................................................................77
Table 4-37: Zero Cross Calibration VREGO_A Register ..............................................................................................................77
Table 4-38: Zero Cross Calibration VREGO_B Register ..............................................................................................................78
Table 4-39: Zero Cross Calibration VREGO_C Register ..............................................................................................................78
Table 4-40: Zero Cross Calibration VREGO_D Register..............................................................................................................78
Table 4-41: Power Sequencer and Always-On Domain Register Summary ...............................................................................78
Table 4-42: Low Power Control Register ...................................................................................................................................79
Table 4-43: GPIO0 Low Power Wakeup Status Flags .................................................................................................................80
Table 4-44: GPIO0 Low Power Wakeup Enable Registers..........................................................................................................80
Table 4-45: GPIO1 Low Power Wakeup Status Flags .................................................................................................................80
Table 4-46: GPIO1 Low Power Wakeup Enable Registers..........................................................................................................80
Table 4-47: Peripheral Low Power Wakeup Status Flags...........................................................................................................81
Table 4-48: Peripheral Low Power Wakeup Enable Register.....................................................................................................82
Table 4-49: RAM Shutdown Control Register ............................................................................................................................83
Table 4-50: Low Power VDD Power Down Register...................................................................................................................84
Table 4-51: BACKUP Return Vector Register .............................................................................................................................85
Table 4-52: BACKUP AoD Register .............................................................................................................................................85
Table 4-53: Global Control Register Summary...........................................................................................................................85
Table 4-54: System Control Register..........................................................................................................................................86
Table 4-55: Reset Register 0 ......................................................................................................................................................87
Table 4-56: System Clock Control Register ................................................................................................................................90
Table 4-57: Power Management Register .................................................................................................................................92
Table 4-58: Peripheral Clock Divisor Register ............................................................................................................................93
Table 4-59: Peripheral Clock Disable Register 0 ........................................................................................................................94
Table 4-60: Memory Clock Control Register..............................................................................................................................96
Table 4-61: Memory Zeroization Control Register ....................................................................................................................98
Table 4-62: System Status Flag Register ..................................................................................................................................100
Table 4-63: Reset Register 1 ....................................................................................................................................................100
Table 4-64: Peripheral Clock Disable Register 1 ......................................................................................................................102
Table 4-65: Event Enable Register ...........................................................................................................................................105
Table 4-66: Revision Register...................................................................................................................................................106
Table 4-67: System Status Interrupt Enable Register ..............................................................................................................106
Table 4-68: Error Correction Coding Error Register.................................................................................................................106
Table 4-69: Error Correction Not Double Error Detected Register ..........................................................................................107
Table 4-70: Error Correction Coding Interrupt Enable Register...............................................................................................109
Table 4-71: Error Correction Coding Address Register ............................................................................................................110
Table 4-72: Bluetooth LDO Control Register............................................................................................................................110
Table 4-73: Bluetooth LDO Delay Count Register....................................................................................................................112
Table 4-74: General Purpose 0 Register ..................................................................................................................................112
Table 4-75: Arm Peripheral Bus Asynchronous Bridge Select Register ...................................................................................112
Table 4-76: Function Control Register Summary.....................................................................................................................113
Table 4-77: Function Control Register 0 ..................................................................................................................................113
Table 4-78: AES Key Register Summary ...................................................................................................................................114
Table 4-79: AES Key 0 and 1 Registers .....................................................................................................................................114
Table 4-80: AES Key 2 and 3 Registers .....................................................................................................................................114
Table 5-1: MAX32665—MAX32668 Interrupt Vector Table ....................................................................................................115
Table 6-1: MAX32665—MAX32668 GPIO Pin Count ...............................................................................................................119
Table 6-2: MAX32665—MAX32668 GPIO and Alternate Function Matrix, 140 WLP ..............................................................120
Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration ...................................................................................................121
Table 6-4: MAX32665—MAX32668 Input Mode Configuration ..............................................................................................121
Table 6-5: MAX32665—MAX32668 Output Mode Configuration ...........................................................................................122
Table 6-6: MAX32665—MAX32668 GPIO Port Interrupt Vector Mapping..............................................................................122
Table 6-7: MAX32665―MAX32668 GPIO Wakeup Interrupt Vector ......................................................................................124

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Table 6-8: GPIO Register Summary..........................................................................................................................................125
Table 6-9: GPIO Port n Configuration Enable Bit 0 Register ....................................................................................................126
Table 6-10: GPIO Port n Configuration Enable Atomic Set Bit 0 Register................................................................................126
Table 6-11: GPIO Port n Configuration Enable Atomic Set Bit 0 Register................................................................................126
Table 6-12: GPIO Port n Output Enable Register.....................................................................................................................126
Table 6-13: GPIO Port n Output Enable Atomic Set Register...................................................................................................127
Table 6-14: GPIO Port n Output Enable Atomic Clear Register ...............................................................................................127
Table 6-15: GPIO Port n Output Register.................................................................................................................................127
Table 6-16: GPIO Port n Output Atomic Set Register ..............................................................................................................127
Table 6-17: GPIO Port n Output Atomic Clear Register ...........................................................................................................127
Table 6-18: GPIO Port n Input Register....................................................................................................................................128
Table 6-19: GPIO Port n Interrupt Mode Register ...................................................................................................................128
Table 6-20: GPIO Port n Interrupt Polarity Register ................................................................................................................128
Table 6-21: GPIO Port n Input Enable Register ........................................................................................................................128
Table 6-22: GPIO Port n Interrupt Enable Register..................................................................................................................129
Table 6-23: GPIO Port n Interrupt Enable Atomic Set Register................................................................................................129
Table 6-24: GPIO Port n Interrupt Enable Atomic Clear Register ............................................................................................129
Table 6-25: GPIO Port n Interrupt Status Register...................................................................................................................129
Table 6-26: GPIO Port n Interrupt Clear Register.....................................................................................................................129
Table 6-27: GPIO Port n Wakeup Enable Register ...................................................................................................................130
Table 6-28: GPIO Port n Wakeup Enable Atomic Set Register.................................................................................................130
Table 6-29: GPIO Port n Wakeup Enable Clear Register..........................................................................................................130
Table 6-30: GPIO Port n Interrupt Dual Edge Mode Register ..................................................................................................130
Table 6-31: GPIO Port n Pullup Pulldown Selection 0 Register................................................................................................130
Table 6-32: GPIO Port n Pullup Pulldown Selection 1 Register................................................................................................131
Table 6-33: GPIO Port n Configuration Enable Bit 1 Register ..................................................................................................131
Table 6-34: GPIO Port n Configuration Enable Atomic Set, Bit 1 Register...............................................................................131
Table 6-35: GPIO Port n Configuration Enable Atomic Clear, Bit 1 Register............................................................................131
Table 6-36: GPIO Port n Configuration Enable Bit 2 Register ..................................................................................................132
Table 6-37: GPIO Port n Configuration Enable Atomic Set Bit 2 Register................................................................................132
Table 6-38: GPIO Port n Configuration Enable Atomic Clear Bit 2 Register.............................................................................132
Table 6-39: GPIO Port n Output Drive Strength Bit 0 Register ................................................................................................132
Table 6-40: GPIO Port n Output Drive Strength Bit 0 Register ................................................................................................132
Table 6-41: GPIOn Pulldown/Pullup Strength Select Register.................................................................................................133
Table 6-42: GPIOn Supply Voltage Select Register ..................................................................................................................133
Table 7-1: MAX32665—MAX32668 Internal Flash Memory Organization ..............................................................................134
Table 7-2: Valid Addresses Flash Writes ..................................................................................................................................135
Table 7-3: Flash Controller Registers .......................................................................................................................................137
Table 7-4: Flash Controller Address Pointer Register ..............................................................................................................138
Table 7-5: Flash Controller Clock Divisor Register ...................................................................................................................138
Table 7-6: Flash Controller Control Register............................................................................................................................138
Table 7-7: Flash Controller Interrupt Register .........................................................................................................................139
Table 7-8: Flash Controller ECC Data Register .........................................................................................................................140
Table 7-9: Flash Controller Data Register 0 .............................................................................................................................140
Table 7-10: Flash Controller Data Register 1 ...........................................................................................................................140
Table 7-11: Flash Controller Data Register 2 ...........................................................................................................................140
Table 7-12: Flash Controller Data Register 3 ...........................................................................................................................141
Table 8-1: SPI Header Format ..................................................................................................................................................145
Table 8-2: Clock Polarity and Phase Combinations..................................................................................................................147
Table 8-3: Encrypted Data Write Order to SPIX Flash Memory ...............................................................................................150
Table 8-4. SPIXF Master Controller Register Offsets, Names, Access and Description ...........................................................151
Table 8-5. SPIXF Controller Configuration Register .................................................................................................................151
Table 8-6. SPIXF Controller Slave Select Polarity Register .......................................................................................................152

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Table 8-7. SPIXF Controller General Control Register..............................................................................................................153
Table 8-8. SPIXF Controller FIFO Control and Status Register .................................................................................................154
Table 8-9. SPIXF Controller Special Control Register ...............................................................................................................155
Table 8-10. SPIXF Controller Interrupt Status Register............................................................................................................156
Table 8-11. SPIXF Controller Interrupt Enable Register...........................................................................................................157
Table 8-12. SPIXF Master Controller FIFO Register Offsets, Names, Access and Description .................................................158
Table 8-13. SPIXF Master Controller TX FIFO Register.............................................................................................................158
Table 8-14. SPIXF Master Controller TX FIFO Register.............................................................................................................158
Table 8-15. SPIXFM Master Register Offsets, Names, Access and Description .......................................................................162
Table 8-16. SPIXFM Configuration Register .............................................................................................................................162
Table 8-17. SPIXFM Fetch Control Register .............................................................................................................................163
Table 8-18. SPIXFM Mode Control Register.............................................................................................................................164
Table 8-19. SPIXFM Mode Data Register .................................................................................................................................165
Table 8-20. SPIXFM SCK Feedback Control Register ................................................................................................................165
Table 8-21. SPIXFM I/O Control Register .................................................................................................................................165
Table 8-22. SPIXFM Memory Security Control Register...........................................................................................................166
Table 8-23. SPIXFM Bus Idle Detection....................................................................................................................................166
Table 8-24. SPIXR Master Controller Register Offsets, Names, Access and Descriptions........................................................168
Table 8-25. SPIXR FIFO Data Register ......................................................................................................................................169
Table 8-26. SPIXR Master Signals Control Register..................................................................................................................169
Table 8-27. SPIXR Transmit Packet Size Register .....................................................................................................................170
Table 8-28. SPIXR Static Configuration Register ......................................................................................................................170
Table 8-29. SPIXR Slave Select Timing Register .......................................................................................................................171
Table 8-30. SPIXR Master Baud Rate Generator......................................................................................................................172
Table 8-31. SPIXR DMA Control Register .................................................................................................................................173
Table 8-32. SPIXR Interrupt Status Flag Register .....................................................................................................................174
Table 8-33. SPIXR Interrupt Enable Register............................................................................................................................175
Table 8-34. SPIXR Wakeup Flag Register .................................................................................................................................176
Table 8-35. SPIXR Wakeup Enable Register .............................................................................................................................177
Table 8-36. SPIXR Active Status Register .................................................................................................................................177
Table 8-37. SPIXR External Memory Control Register .............................................................................................................177
Table 8-38: External Memory Cache Controller Register Addresses and Descriptions ...........................................................179
Table 8-39: SRCC Cache ID Register.........................................................................................................................................179
Table 8-40: SRCC Memory Size Register ..................................................................................................................................179
Table 8-41: SRCC Cache Control Register ................................................................................................................................179
Table 8-42: SRCC Invalidate Register .......................................................................................................................................180
Table 8-43: MAX32665—MAX32668 SDHC Alternate Function Mapping to SDHC Specification Pin Names .........................182
Table 8-44: Registers Used to Generate SD Commands..........................................................................................................184
Table 8-45: SDHC Register Offsets, Names and Descriptions..................................................................................................185
Table 8-46: SDHC SDMA System Address / Argument Register...............................................................................................186
Table 8-47: SDHC SDMA Block Size Register............................................................................................................................187
Table 8-48: SDHC SDMA Block Count Register ........................................................................................................................188
Table 8-49: SDHC SDMA Argument 1 Register ........................................................................................................................188
Table 8-50: SDHC SDMA Transfer Mode Register....................................................................................................................188
Table 8-51: Summary of how register settings determine type of data transfer ....................................................................190
Table 8-52: SDHC Command Register......................................................................................................................................190
Table 8-53: Relationship between Parameters and the Name of Response Type ..................................................................191
Table 8-54: SDHC Response 0 Register....................................................................................................................................191
Table 8-55: SDHC Response 1 Register....................................................................................................................................191
Table 8-56: SDHC Response 2 Register....................................................................................................................................191
Table 8-57: SDHC Response 3 Register....................................................................................................................................192
Table 8-58: SDHC Response 4 Register....................................................................................................................................192
Table 8-59: SDHC Response 5 Register....................................................................................................................................192

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Table 8-60: SDHC Response 6 Register....................................................................................................................................192
Table 8-61: SDHC Response 7 Register....................................................................................................................................193
Table 8-62: SDHC Response Register Mapping to SD Host Controller Response Register Convention...................................193
Table 8-63: Kind of SD Card Response Mapping to SDHC Response Registers........................................................................193
Table 8-64: SDHC Buffer Data Port Register ............................................................................................................................193
Table 8-65: SDHC Present State Register.................................................................................................................................193
Table 8-66: SDHC Host Control 1 Register ...............................................................................................................................196
Table 8-67: SDHC Power Control Register ...............................................................................................................................197
Table 8-68: SDHC Block Gap Control Register .........................................................................................................................197
Table 8-69: SDHC Wakeup Control Register ............................................................................................................................199
Table 8-70: SDHC Clock Control Register.................................................................................................................................199
Table 8-71: SDHC Timeout Control Register............................................................................................................................201
Table 8-72: SDHC Software Reset Register..............................................................................................................................202
Table 8-73: SDHC Normal Interrupt Status Register................................................................................................................203
Table 8-74: Transfer Complete and Data Timeout Error Priority and Status...........................................................................205
Table 8-75: Command Complete and Command Timeout Error Priority and Status ..............................................................205
Table 8-76: SDHC Error Interrupt Status Register....................................................................................................................205
Table 8-77: SDHC Normal Interrupt Status Register................................................................................................................207
Table 8-78: SDHC Error Interrupt Status Enable Register ........................................................................................................208
Table 8-79: SDHC Normal Interrupt Signal Enable Register.....................................................................................................209
Table 8-80: SDHC Error Interrupt Signal Enable Register ........................................................................................................210
Table 8-81: SDHC Auto CMD Error Status Register..................................................................................................................211
Table 8-82: SDHC Host Control 2 Register ...............................................................................................................................212
Table 8-83: SDHC Capabilities Register 0.................................................................................................................................213
Table 8-84: SDHC Capabilities Register 1.................................................................................................................................215
Table 8-85: SDHC Maximum Current Capabilities Register .....................................................................................................216
Table 8-86: SDHC Force Event Register for Auto CMD Error Status Register ..........................................................................216
Table 8-87: SDHC Force Event Register for Error Interrupt Status ..........................................................................................216
Table 8-88: SDHC ADMA Error Status Register........................................................................................................................217
Table 8-89: SDHC ADMA System Address Register 0...............................................................................................................218
Table 8-90: SDHC ADMA System Address Register 1...............................................................................................................219
Table 8-91: Preset Value Register Example .............................................................................................................................219
Table 8-92: Preset Value Register Selection Conditions ..........................................................................................................219
Table 8-93: SDHC Preset Value 0 to Preset Value 7 Registers .................................................................................................220
Table 8-94: SDHC Slot Interrupt Status Register......................................................................................................................220
Table 8-95: SDHC Host Controller Version Register.................................................................................................................221
Table 9-1: MAX32665—MAX32668 DMAC and Channel Instances.........................................................................................223
Table 9-2: MAX32665—MAX32668 DMAC Source and Destination by Peripheral .................................................................224
Table 9-3: Data Movement from Source to DMA FIFO............................................................................................................226
Table 9-4: Data Movement from the DMA FIFO to Destination..............................................................................................226
Table 9-5: DMA Channel Timeout Configuration.....................................................................................................................230
Table 9-6: DMAC Register Summary........................................................................................................................................231
Table 9-7: DMACn Control Register.........................................................................................................................................231
Table 9-8: DMACn Interrupt Register ......................................................................................................................................232
Table 9-9: Standard DMA Channel 0 to Channel 7 Register Summary ....................................................................................232
Table 9-10: DMACH Channel Registers Summary....................................................................................................................232
Table 9-11: DMACHn Configuration Register ..........................................................................................................................233
Table 9-12: DMA Status Register .............................................................................................................................................234
Table 9-13: DMACHn Source Register .....................................................................................................................................235
Table 9-14: DMA Channel n Destination Register ...................................................................................................................236
Table 9-15: DMA Channel n Count Register ............................................................................................................................236
Table 9-16: DMA Channel n Source Reload Register ...............................................................................................................236
Table 9-17: DMA Channel n Destination Reload Register .......................................................................................................236

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Table 9-18: DMA Channel n Count Reload Register ................................................................................................................237
Table 10-1: Common CRC Polynomials....................................................................................................................................239
Table 10-2: CRC Register Summary..........................................................................................................................................240
Table 10-3: CRC Control Register.............................................................................................................................................243
Table 10-4: CRC DMA Source Register.....................................................................................................................................243
Table 10-5: CRC DMA Destination Register .............................................................................................................................243
Table 10-6: CRC DMA Count Register ......................................................................................................................................243
Table 10-7: CRC Data Input Registers ......................................................................................................................................244
Table 10-8: CRC Data Output Registers ...................................................................................................................................244
Table 10-9: CRC Polynomial Register.......................................................................................................................................244
Table 10-10: CRC Value Register..............................................................................................................................................245
Table 10-11: CRC Pseudo-Random Number Generator Register.............................................................................................245
Table 11-1: MAX32665—MAX32668 ADC Peripheral Pins ......................................................................................................246
Table 11-2: ADC Clock Frequency and ADC Conversion Time (, ).............................249
Table 11-3: Input and Reference Scale Support by ADC Input Channel ..................................................................................251
Table 11-4: ADC Data Register Alignment Options..................................................................................................................252
Table 11-5. ADC Registers Summary........................................................................................................................................255
Table 11-6: ADC Control Register ............................................................................................................................................255
Table 11-7: ADC Status Register ..............................................................................................................................................257
Table 11-8: ADC Data Register.................................................................................................................................................257
Table 11-9: ADC Interrupt Control Register.............................................................................................................................257
Table 11-10: ADC Limit 0 to 3 Registers...................................................................................................................................258
Table 12-1: UART Interrupt Conditions....................................................................................................................................261
Table 12-2: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps ....................................................................262
Table 12-3: UART Register Summary.......................................................................................................................................264
Table 12-4: UART Control 0 Register .......................................................................................................................................264
Table 12-5: UART Control 1 Register .......................................................................................................................................266
Table 12-6: UART Status Register ............................................................................................................................................266
Table 12-7: UART Interrupt Enable Register............................................................................................................................267
Table 12-8: UART Interrupt Flags Register...............................................................................................................................268
Table 12-9: UART Rate Integer Register ..................................................................................................................................270
Table 12-10: UART Baud Rate Decimal Register......................................................................................................................270
Table 12-11: UART FIFO Register.............................................................................................................................................270
Table 12-12: UART DMA Configuration Register .....................................................................................................................270
Table 12-13: UART Transmit FIFO Data Output Register .........................................................................................................271
Table 13-1: MAX32665 –MAX32668 I2C Peripheral Pins ........................................................................................................274
Table 13-2: I2C Bus Terminology..............................................................................................................................................275
Table 13-3: Calculated I2C Bus Clock Frequencies ...................................................................................................................279
Table 13-4: I2C Slave Address Format ......................................................................................................................................279
Table 13-5: I2C Registers ..........................................................................................................................................................292
Table 13-6: I2C Control 0 Register............................................................................................................................................293
Table 13-7: I2C Status Register.................................................................................................................................................294
Table 13-8: I2C Interrupt Flag 0 Register..................................................................................................................................295
Table 13-9: I2C Interrupt Enable 0 Register .............................................................................................................................297
Table 13-10: I2C Interrupt Flag 1 Register................................................................................................................................299
Table 13-11: I2C Interrupt Enable 1 Register ...........................................................................................................................299
Table 13-12: I2C FIFO Length Register......................................................................................................................................299
Table 13-13: I2C Receive Control 0 Register.............................................................................................................................299
Table 13-14: I2C Receive Control 1 Register.............................................................................................................................300
Table 13-15: I2C Transmit Control 0 Register...........................................................................................................................301
Table 13-16: I2C Transmit Control 1 Register...........................................................................................................................302
Table 13-17: I2C Data Register .................................................................................................................................................302
Table 13-18: I2C Master Mode Control Register......................................................................................................................303