Maxim Integrated MAX32665 User manual

MAX32665–MAX32668 USER GUIDE
UG6971; Rev 0; 6/19
Abstract: This user guide provides application developers information on how to use the memory and peripherals of the
MAX32665–MAX32668 microcontroller. Detailed information for all registers and fields in the device are covered.
Guidance is given for managing all the peripherals, clocks, power and startup for the device family.

MAX32665-MAX32668 User Guide
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MAX32665—MAX32669 User Guide
Table of Contents
1. Overview----------------------------------------------------------------------------------------------------------------- 24
1.1 Block Diagram ---------------------------------------------------------------------------------------------------------------- 25
2. Resource Protection Unit (RPU) ------------------------------------------------------------------------------------ 26
2.1 Instances----------------------------------------------------------------------------------------------------------------------- 26
2.2 Usage --------------------------------------------------------------------------------------------------------------------------- 28
2.2.1 Reset State -------------------------------------------------------------------------------------------------------------------------------- 28
2.2.2 MPU Implementation ------------------------------------------------------------------------------------------------------------------ 28
2.2.3 MPU Protection Fault ------------------------------------------------------------------------------------------------------------------ 28
2.2.4 RPU Protection Fault-------------------------------------------------------------------------------------------------------------------- 28
2.2.5 RPU Fault Handler----------------------------------------------------------------------------------------------------------------------- 28
2.3 Registers----------------------------------------------------------------------------------------------------------------------- 29
2.4 Register Details -------------------------------------------------------------------------------------------------------------- 31
3. Memory, Register Mapping, and Access ------------------------------------------------------------------------- 34
3.1 Memory, Register Mapping, and Access Overview ----------------------------------------------------------------- 34
3.2 Standard Memory Regions------------------------------------------------------------------------------------------------ 37
3.2.1 Code Space -------------------------------------------------------------------------------------------------------------------------------- 37
3.2.2 SRAM Space------------------------------------------------------------------------------------------------------------------------------- 37
3.2.3 Peripheral Space ------------------------------------------------------------------------------------------------------------------------- 38
3.2.4 External RAM Space -------------------------------------------------------------------------------------------------------------------- 38
3.2.5 External Device Space ------------------------------------------------------------------------------------------------------------------ 39
3.2.6 System Area (Private Peripheral Bus) ---------------------------------------------------------------------------------------------- 39
3.2.7 System Area (Vendor Defined) ------------------------------------------------------------------------------------------------------- 39
3.3 Device Memory Instances------------------------------------------------------------------------------------------------- 39
3.3.1 Main Program Flash Memory -------------------------------------------------------------------------------------------------------- 39
3.3.2 Cache Memories ------------------------------------------------------------------------------------------------------------------------- 39
3.3.3 External Memory Cache Controller (EMCC) -------------------------------------------------------------------------------------- 40
3.3.4 Information Block Flash Memory---------------------------------------------------------------------------------------------------- 40
3.3.5 System SRAM ----------------------------------------------------------------------------------------------------------------------------- 40
3.3.6 AES Key and Working Space Memory---------------------------------------------------------------------------------------------- 40
3.3.7 MAA Key and Working Space Memory -------------------------------------------------------------------------------------------- 40
3.3.8 TPU Memory ------------------------------------------------------------------------------------------------------------------------------ 40
3.4 AHB Interfaces --------------------------------------------------------------------------------------------------------------- 40

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3.4.1 Core AHB Interfaces--------------------------------------------------------------------------------------------------------------------- 40
3.4.2 AHB Masters ------------------------------------------------------------------------------------------------------------------------------ 41
3.5 Peripheral Register Map--------------------------------------------------------------------------------------------------- 41
3.5.1 APB Peripheral Base Address Map-------------------------------------------------------------------------------------------------- 41
3.5.2 AHB Peripheral Base Address Map ------------------------------------------------------------------------------------------------- 42
3.6 Error Correction Coding (ECC) Module--------------------------------------------------------------------------------- 43
3.6.1 SRAM --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.2 FLASH --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.3 Cache --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.4 Limitations--------------------------------------------------------------------------------------------------------------------------------- 43
4. System, Power, Clocks, Reset --------------------------------------------------------------------------------------- 50
4.1 Oscillator Sources and Clock Switching -------------------------------------------------------------------------------- 50
4.1.1 Oscillator Inplementation ------------------------------------------------------------------------------------------------------------- 52
4.1.2 96MHz Internal Main High-Speed Oscillator ------------------------------------------------------------------------------------- 52
4.1.3 60MHz Low Power Internal Oscillator --------------------------------------------------------------------------------------------- 52
4.1.4 32MHz Bluetooth Radio Oscillator-------------------------------------------------------------------------------------------------- 52
4.1.5 7.3728MHz Internal Oscillator ------------------------------------------------------------------------------------------------------- 53
4.1.6 32.768kHz External Crystal Oscillator---------------------------------------------------------------------------------------------- 53
4.1.7 8kHz Ultra-Low Power Nano-Ring Internal Oscillator ------------------------------------------------------------------------- 53
4.2 Operating Modes------------------------------------------------------------------------------------------------------------ 54
4.2.1 ACTIVE Mode ----------------------------------------------------------------------------------------------------------------------------- 54
4.2.2 SLEEP Low Power Mode --------------------------------------------------------------------------------------------------------------- 54
4.2.3 DEEPSLEEP Low Power Mode -------------------------------------------------------------------------------------------------------- 56
4.2.4 BACKUP Low Power Mode ------------------------------------------------------------------------------------------------------------ 58
4.3 Device Resets----------------------------------------------------------------------------------------------------------------- 60
4.3.1 Peripheral Reset ------------------------------------------------------------------------------------------------------------------------- 61
4.3.2 Soft Reset ---------------------------------------------------------------------------------------------------------------------------------- 61
4.3.3 System Reset------------------------------------------------------------------------------------------------------------------------------ 62
4.3.4 Power-On Reset -------------------------------------------------------------------------------------------------------------------------- 62
4.4 Cache --------------------------------------------------------------------------------------------------------------------------- 62
4.5 Instruction Cache Controller---------------------------------------------------------------------------------------------- 63
4.5.1 Enabling ICC0/ICC1/SFCC -------------------------------------------------------------------------------------------------------------- 63
4.5.2 Flushing the ICC0/ICC1/SFCC Cache ------------------------------------------------------------------------------------------------ 64
4.5.3 Flushing SRCC Cache -------------------------------------------------------------------------------------------------------------------- 64
4.6 Instruction Cache Controller Registers--------------------------------------------------------------------------------- 64
4.7 External RAM SPIXR Cache Controller (SRCC) ------------------------------------------------------------------------ 66

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4.8 RAM Memory Management---------------------------------------------------------------------------------------------- 67
4.8.1 RAM Zeroization ------------------------------------------------------------------------------------------------------------------------- 67
4.8.2 RAM Low Power Modes --------------------------------------------------------------------------------------------------------------- 67
4.9 Miscellaneous Control Registers----------------------------------------------------------------------------------------- 68
4.10 Miscellaneous Control Registers Details------------------------------------------------------------------------------- 68
4.11 Single Inductor Multiple Output (SIMO) Power Supply ------------------------------------------------------------ 71
4.11.1 Power Supply Monitor------------------------------------------------------------------------------------------------------------------ 71
4.12 Single Inductor Multiple Output (SIMO) Registers ------------------------------------------------------------------ 72
4.13 Single Inductor Multiple Output (SIMO) Registers Details -------------------------------------------------------- 73
4.14 Power Sequencer and Always-On Domain Registers --------------------------------------------------------------- 78
4.15 Power Sequencer and Always-On Domain Register Details------------------------------------------------------- 79
4.16 Global Control Registers (GCR)------------------------------------------------------------------------------------------- 85
4.17 Global Control Register Details (GCR) ---------------------------------------------------------------------------------- 86
4.18 Function Control Registers ---------------------------------------------------------------------------------------------- 113
4.19 Function Control Register Details ------------------------------------------------------------------------------------- 113
4.20 AES Key Registers---------------------------------------------------------------------------------------------------------- 114
4.21 AES Key Register Details ------------------------------------------------------------------------------------------------- 114
5. Interrupts and Exceptions ------------------------------------------------------------------------------------------115
5.1 Features---------------------------------------------------------------------------------------------------------------------- 115
5.2 Interrupt Vector Table --------------------------------------------------------------------------------------------------- 115
6. General-Purpose I/O and Alternate Function Pins (GPIO)---------------------------------------------------119
6.1 Instances--------------------------------------------------------------------------------------------------------------------- 119
6.2 Usage ------------------------------------------------------------------------------------------------------------------------- 123
6.2.1 Reset State ------------------------------------------------------------------------------------------------------------------------------ 123
6.2.2 Input Mode Configuration----------------------------------------------------------------------------------------------------------- 123
6.2.3 Output Mode Configuration -------------------------------------------------------------------------------------------------------- 123
6.2.4 Alternate Function Configuration ------------------------------------------------------------------------------------------------- 123
6.3 Configuring GPIO (External) Interrupts------------------------------------------------------------------------------- 123
6.3.1 GPIO Interrupt Handling ------------------------------------------------------------------------------------------------------------- 124
6.3.2 Using GPIO for Wakeup from Low Power Modes ----------------------------------------------------------------------------- 124
6.4 Registers--------------------------------------------------------------------------------------------------------------------- 125
6.5 Register Details ------------------------------------------------------------------------------------------------------------ 126
7. Flash Controller (FLC) ------------------------------------------------------------------------------------------------134
7.1 Instances--------------------------------------------------------------------------------------------------------------------- 134
7.2 Usage ------------------------------------------------------------------------------------------------------------------------- 134

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7.2.1 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 135
7.2.2 Lock Protection------------------------------------------------------------------------------------------------------------------------- 135
7.2.3 Flash Write Width --------------------------------------------------------------------------------------------------------------------- 135
7.2.4 Flash Write ------------------------------------------------------------------------------------------------------------------------------ 136
7.2.5 Page Erase------------------------------------------------------------------------------------------------------------------------------- 136
7.2.6 Mass Erase ------------------------------------------------------------------------------------------------------------------------------ 137
7.3 Flash Error Correction Coding ------------------------------------------------------------------------------------------ 137
7.4 Flash Controller Registers ----------------------------------------------------------------------------------------------- 137
7.5 Flash Controller Register Details--------------------------------------------------------------------------------------- 138
8. External Memory -----------------------------------------------------------------------------------------------------142
8.1 Overview--------------------------------------------------------------------------------------------------------------------- 142
8.2 SPI Execute-in-Place Flash (SPIXF)------------------------------------------------------------------------------------- 142
8.2.1 SPIXF Master Controller-------------------------------------------------------------------------------------------------------------- 143
8.2.2 SPIXF Master---------------------------------------------------------------------------------------------------------------------------- 158
8.3 SPI Execute-in-Place RAM (SPIXR)------------------------------------------------------------------------------------- 167
8.3.1 SPIXR Master Controller Registers ------------------------------------------------------------------------------------------------ 168
8.3.2 SPIXR Register Details ---------------------------------------------------------------------------------------------------------------- 169
8.4 SPIXR Cache Controller (SRCC) ----------------------------------------------------------------------------------------- 178
8.4.1 Features---------------------------------------------------------------------------------------------------------------------------------- 178
8.4.2 Enabling the SRCC --------------------------------------------------------------------------------------------------------------------- 178
8.4.3 Disabling the SRCC -------------------------------------------------------------------------------------------------------------------- 178
8.4.4 SRCC Registers-------------------------------------------------------------------------------------------------------------------------- 179
8.4.5 SRCC Register Details ----------------------------------------------------------------------------------------------------------------- 179
8.5 Secure Digital Host Controller------------------------------------------------------------------------------------------ 181
8.5.1 Instances--------------------------------------------------------------------------------------------------------------------------------- 182
8.5.2 SDHC Peripheral Clock Selection--------------------------------------------------------------------------------------------------- 183
8.5.3 Usage ------------------------------------------------------------------------------------------------------------------------------------- 183
8.5.4 SD Command Generation ----------------------------------------------------------------------------------------------------------- 184
8.5.5 SDHC Registers ------------------------------------------------------------------------------------------------------------------------- 185
8.5.6 SDHC Register Details ---------------------------------------------------------------------------------------------------------------- 186
9. Standard DMA (DMAC)----------------------------------------------------------------------------------------------222
9.1 Instances--------------------------------------------------------------------------------------------------------------------- 222
9.2 DMA Channel Operation (DMACH) ----------------------------------------------------------------------------------- 223
9.2.1 DMA Channel Arbitration and DMA Bursts ------------------------------------------------------------------------------------- 223
9.2.2 DMA Source and Destination Addressing --------------------------------------------------------------------------------------- 224
Data Movement From Source to DMA------------------------------------------------------------------------------------------------------- 226

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9.2.3 Data Movement From the DMA to Destination ------------------------------------------------------------------------------- 226
9.3 Usage ------------------------------------------------------------------------------------------------------------------------- 227
9.4 Count-To-Zero (CTZ) Condition ---------------------------------------------------------------------------------------- 227
9.5 Chaining Buffers ----------------------------------------------------------------------------------------------------------- 228
9.6 DMA Interrupts ------------------------------------------------------------------------------------------------------------ 230
9.7 Channel Timeout Detect------------------------------------------------------------------------------------------------- 230
9.8 Memory-to-Memory DMA ---------------------------------------------------------------------------------------------- 231
9.9 DMAC Registers------------------------------------------------------------------------------------------------------------ 231
9.10 DMAC Register Details --------------------------------------------------------------------------------------------------- 231
9.11 DMA Channel Registers-------------------------------------------------------------------------------------------------- 232
9.12 DMAC Channel Registers ------------------------------------------------------------------------------------------------ 232
9.13 DMA Channel Register Details ----------------------------------------------------------------------------------------- 233
10. Cyclic Redundancy Check Engine (CRC)-----------------------------------------------------------------------238
10.1 Instances--------------------------------------------------------------------------------------------------------------------- 239
10.2 Linear Feedback Shift Register (LFSR) -------------------------------------------------------------------------------- 239
10.3 Registers --------------------------------------------------------------------------------------------------------------------- 240
10.4 Register Details ------------------------------------------------------------------------------------------------------------ 241
11. Analog to Digital Converter and Comparators (ADC)------------------------------------------------------246
11.1 Features---------------------------------------------------------------------------------------------------------------------- 246
11.2 Instances--------------------------------------------------------------------------------------------------------------------- 246
11.3 Architecture----------------------------------------------------------------------------------------------------------------- 247
11.4 Clock Configuration ------------------------------------------------------------------------------------------------------- 249
11.5 Power-Up Sequence ------------------------------------------------------------------------------------------------------ 250
11.6 Conversion ------------------------------------------------------------------------------------------------------------------ 250
11.7 Reference Scaling and Input Scaling ---------------------------------------------------------------------------------- 250
11.7.1 AIN0 –AIN7 Scale Limitations------------------------------------------------------------------------------------------------------ 251
11.7.2 Scale Limitations for All Other Input Channels--------------------------------------------------------------------------------- 251
11.7.3 Data Conversion Output Alignment ---------------------------------------------------------------------------------------------- 251
11.7.4 Data Conversion Value Equations------------------------------------------------------------------------------------------------- 252
11.7.5 Data Limits and Out of Range Interrupts---------------------------------------------------------------------------------------- 253
11.7.6 Power-Down Sequence--------------------------------------------------------------------------------------------------------------- 254
11.8 Comparator Operation--------------------------------------------------------------------------------------------------- 254
11.9 Registers --------------------------------------------------------------------------------------------------------------------- 255
11.10 Register Details ------------------------------------------------------------------------------------------------------------ 255
12. UART------------------------------------------------------------------------------------------------------------------260

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12.1 Instances--------------------------------------------------------------------------------------------------------------------- 260
12.2 UART Frame----------------------------------------------------------------------------------------------------------------- 260
12.3 UART Interrupts------------------------------------------------------------------------------------------------------------ 261
12.4 UART Baud Rate Clock Source------------------------------------------------------------------------------------------ 261
12.5 UART Baud Rate Calculation-------------------------------------------------------------------------------------------- 261
12.6 UART Configuration and Operation----------------------------------------------------------------------------------- 263
12.7 Wakeup Time--------------------------------------------------------------------------------------------------------------- 263
12.8 Hardware Flow Control -------------------------------------------------------------------------------------------------- 263
12.9 Registers --------------------------------------------------------------------------------------------------------------------- 263
12.10 Register Details ------------------------------------------------------------------------------------------------------------ 264
13. I2C Master/Slave Serial Communications Peripheral (I2C) -----------------------------------------------272
13.1 I2C Master/Slave Features----------------------------------------------------------------------------------------------- 274
13.2 Instances--------------------------------------------------------------------------------------------------------------------- 274
13.3 I2C Overview ---------------------------------------------------------------------------------------------------------------- 275
13.3.1 I2C Bus Terminology------------------------------------------------------------------------------------------------------------------- 275
13.3.2 I2C Transfer Protocol Operation --------------------------------------------------------------------------------------------------- 275
13.3.3 START and STOP Conditions -------------------------------------------------------------------------------------------------------- 275
13.3.4 Master Operation --------------------------------------------------------------------------------------------------------------------- 275
13.3.5 Acknowledge and Not Acknowledge --------------------------------------------------------------------------------------------- 275
13.3.6 Bit Transfer Process ------------------------------------------------------------------------------------------------------------------- 276
13.4 I2C Configuration and Usage-------------------------------------------------------------------------------------------- 277
13.4.1 SCL and SDA Bus Drivers ------------------------------------------------------------------------------------------------------------- 277
13.4.2 SCL Clock Configurations ------------------------------------------------------------------------------------------------------------ 277
13.4.3 SCL Clock Generation for Standard, Fast and Fast-Plus Modes ----------------------------------------------------------- 277
13.4.4 SCL Clock Generation for Hs-mode------------------------------------------------------------------------------------------------ 278
13.4.5 I2C Addressing -------------------------------------------------------------------------------------------------------------------------- 279
13.4.6 I2C Master Mode Operation -------------------------------------------------------------------------------------------------------- 280
13.4.7 I2C Slave Mode Operation ----------------------------------------------------------------------------------------------------------- 283
13.4.8 I2C Interrupt Sources ------------------------------------------------------------------------------------------------------------------ 288
13.4.9 TX FIFO and RX FIFO ------------------------------------------------------------------------------------------------------------------ 288
13.4.10 TX FIFO Preloading ---------------------------------------------------------------------------------------------------------------- 289
13.4.11 Interactive Receive Mode (IRXM) --------------------------------------------------------------------------------------------- 290
13.4.12 Clock Stretching -------------------------------------------------------------------------------------------------------------------- 291
13.4.13 I2C Bus Timeout -------------------------------------------------------------------------------------------------------------------- 291
13.4.14 I2C DMA Control-------------------------------------------------------------------------------------------------------------------- 292
13.5 Registers --------------------------------------------------------------------------------------------------------------------- 292

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13.6 Register Details ------------------------------------------------------------------------------------------------------------ 293
14. Quad Serial Peripheral Interface (SPI)-------------------------------------------------------------------------306
14.1 Instances--------------------------------------------------------------------------------------------------------------------- 307
14.2 SPI Formats ----------------------------------------------------------------------------------------------------------------- 308
14.2.1 Four-Wire SPI --------------------------------------------------------------------------------------------------------------------------- 308
14.2.2 Three-Wire SPI-------------------------------------------------------------------------------------------------------------------------- 309
14.3 Pin Configuration ---------------------------------------------------------------------------------------------------------- 310
14.3.1 QSPIn Alternate Function Mapping----------------------------------------------------------------------------------------------- 310
14.3.2 Four-wire Format Configuration--------------------------------------------------------------------------------------------------- 310
14.3.3 Three-Wire Format Configuration ------------------------------------------------------------------------------------------------ 310
14.3.4 Dual Mode Format Configuration------------------------------------------------------------------------------------------------- 311
14.3.5 Quad Mode Format Pin Configuration------------------------------------------------------------------------------------------- 311
14.4 QSPI Clock Configuration ------------------------------------------------------------------------------------------------ 311
14.4.1 Serial Clock ------------------------------------------------------------------------------------------------------------------------------ 311
14.4.2 SPI Peripheral Clock ------------------------------------------------------------------------------------------------------------------- 312
14.4.3 Master Mode Serial Clock Generation ------------------------------------------------------------------------------------------- 312
14.4.4 Clock Phase and Polarity Control-------------------------------------------------------------------------------------------------- 312
14.4.5 QSPIn FIFOs ----------------------------------------------------------------------------------------------------------------------------- 313
14.4.6 QSPI Interrupts and Wakeups ------------------------------------------------------------------------------------------------------ 313
14.5 Registers --------------------------------------------------------------------------------------------------------------------- 314
14.6 Register Details ------------------------------------------------------------------------------------------------------------ 315
15. HTimer (HT) ---------------------------------------------------------------------------------------------------------324
15.1 Overview--------------------------------------------------------------------------------------------------------------------- 324
15.2 Alarm Functions------------------------------------------------------------------------------------------------------------ 324
15.2.1 Long-Interval Alarm------------------------------------------------------------------------------------------------------------------- 324
15.2.2 Short-Interval Alarm ------------------------------------------------------------------------------------------------------------------ 324
15.3 Register Access Control -------------------------------------------------------------------------------------------------- 325
15.3.1 Register Write Protection ----------------------------------------------------------------------------------------------------------- 325
15.3.2 Register Read Protection ------------------------------------------------------------------------------------------------------------ 325
15.3.3 Count Register Access ---------------------------------------------------------------------------------------------------------------- 325
15.3.4 Alarm Register Access ---------------------------------------------------------------------------------------------------------------- 325
15.4 Registers --------------------------------------------------------------------------------------------------------------------- 326
15.5 Register Details ------------------------------------------------------------------------------------------------------------ 326
16. Timers ----------------------------------------------------------------------------------------------------------------329
16.1 Features---------------------------------------------------------------------------------------------------------------------- 329
16.2 Basic Operation ------------------------------------------------------------------------------------------------------------ 329

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16.3 Timer Pin Functionality--------------------------------------------------------------------------------------------------- 330
16.4 One-Shot Mode (000b)--------------------------------------------------------------------------------------------------- 330
16.4.1 One-Shot Mode Timer Period ------------------------------------------------------------------------------------------------------ 331
16.4.2 One-Shot Mode Configuration ----------------------------------------------------------------------------------------------------- 331
16.5 Continuous Mode (001b)------------------------------------------------------------------------------------------------ 331
16.5.1 Continuous Mode Timer Period---------------------------------------------------------------------------------------------------- 332
16.5.2 Continuous Mode Configuration -------------------------------------------------------------------------------------------------- 333
16.6 Counter Mode (010b) ---------------------------------------------------------------------------------------------------- 334
16.6.1 Counter Mode Timer Period -------------------------------------------------------------------------------------------------------- 335
16.6.2 Counter Mode Configuration ------------------------------------------------------------------------------------------------------- 335
16.7 PWM Mode (011b)-------------------------------------------------------------------------------------------------------- 336
16.7.1 PWM Mode Timer Period ----------------------------------------------------------------------------------------------------------- 336
16.7.2 PWM Mode Configuration ---------------------------------------------------------------------------------------------------------- 336
16.8 Capture Mode (100b) ---------------------------------------------------------------------------------------------------- 338
16.8.1 Capture Mode Timer Period -------------------------------------------------------------------------------------------------------- 339
16.8.2 Capture Mode Configuration ------------------------------------------------------------------------------------------------------- 339
16.9 Compare Mode (101b)--------------------------------------------------------------------------------------------------- 339
16.9.1 Compare Mode Timer Period------------------------------------------------------------------------------------------------------- 340
16.9.2 Compare Mode Configuration ----------------------------------------------------------------------------------------------------- 341
16.10 Gated Mode (110b) ------------------------------------------------------------------------------------------------------- 342
16.10.1 Gated Mode Timer Period------------------------------------------------------------------------------------------------------- 343
16.10.2 Gated Mode Configuration ----------------------------------------------------------------------------------------------------- 343
16.11 Capture/Compare Mode (111b) --------------------------------------------------------------------------------------- 344
16.11.1 Capture/Compare Timer Period ----------------------------------------------------------------------------------------------- 344
16.11.2 Capture/Compare Configuration ---------------------------------------------------------------------------------------------- 344
16.12 Timer Registers------------------------------------------------------------------------------------------------------------- 345
17. Pulse Train Engine (PT) -------------------------------------------------------------------------------------------349
17.1 Instances--------------------------------------------------------------------------------------------------------------------- 349
17.2 Pulse Train Engine Features--------------------------------------------------------------------------------------------- 349
17.3 Engine ------------------------------------------------------------------------------------------------------------------------ 349
17.3.1 Pulse Train Output Modes ---------------------------------------------------------------------------------------------------------- 350
17.4 Enabling and Disabling a Pulse Train Output ----------------------------------------------------------------------- 351
17.5 Atomic Pulse Train Output Enable and Disable -------------------------------------------------------------------- 351
17.5.1 Pulse Train Atomic Enable----------------------------------------------------------------------------------------------------------- 351
17.5.2 Pulse Train Atomic Disable---------------------------------------------------------------------------------------------------------- 352
17.6 Pulse Train Halt and Disable -------------------------------------------------------------------------------------------- 352

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17.7 Pulse Train Interrupts ---------------------------------------------------------------------------------------------------- 352
17.8 Registers --------------------------------------------------------------------------------------------------------------------- 352
17.9 Register Details ------------------------------------------------------------------------------------------------------------ 354
17.9.1 Pulse Train Engine Safe Enable Register----------------------------------------------------------------------------------------- 363
17.9.2 Pulse Train Engine Safe Disable Register---------------------------------------------------------------------------------------- 364
18. Real-Time Clock (RTC)---------------------------------------------------------------------------------------------369
18.1 Overview--------------------------------------------------------------------------------------------------------------------- 369
18.2 Instances--------------------------------------------------------------------------------------------------------------------- 370
18.3 Register Access Control -------------------------------------------------------------------------------------------------- 370
18.3.1 RTC_SEC and RTC_SSEC Read Access Control ---------------------------------------------------------------------------------- 370
18.3.2 RTC Write Access Control------------------------------------------------------------------------------------------------------------ 371
18.4 RTC Alarm Functions------------------------------------------------------------------------------------------------------ 371
18.4.1 Time-of-Day Alarm -------------------------------------------------------------------------------------------------------------------- 371
18.4.2 Sub-Second Alarm --------------------------------------------------------------------------------------------------------------------- 372
18.4.3 RTC Interrupt and Wakeup Configuration -------------------------------------------------------------------------------------- 373
18.4.4 Square Wave Output ----------------------------------------------------------------------------------------------------------------- 373
18.5 RTC Calibration------------------------------------------------------------------------------------------------------------- 374
18.6 Registers --------------------------------------------------------------------------------------------------------------------- 376
18.7 Register Details ------------------------------------------------------------------------------------------------------------ 376
19. Watchdog Timer (WDT) ------------------------------------------------------------------------------------------380
19.1 Features---------------------------------------------------------------------------------------------------------------------- 381
19.2 Usage ------------------------------------------------------------------------------------------------------------------------- 381
19.3 Interrupt and Reset Period Timeout Configuration--------------------------------------------------------------- 382
19.4 Timed Access Protection------------------------------------------------------------------------------------------------- 382
19.5 Enabling the Watchdog Timer------------------------------------------------------------------------------------------ 383
19.5.1 Enable sequence ----------------------------------------------------------------------------------------------------------------------- 383
19.6 Disabling the Watchdog Timer----------------------------------------------------------------------------------------- 383
19.6.1 Manual Disable ------------------------------------------------------------------------------------------------------------------------ 383
19.6.2 Automatic Disable--------------------------------------------------------------------------------------------------------------------- 383
19.7 Resetting the Watchdog Timer----------------------------------------------------------------------------------------- 383
19.7.1 Reset Sequence------------------------------------------------------------------------------------------------------------------------- 383
19.8 Detection of a Watchdog Reset Event-------------------------------------------------------------------------------- 383
19.9 Registers --------------------------------------------------------------------------------------------------------------------- 383
19.10 Register Details ------------------------------------------------------------------------------------------------------------ 384
20. 1-Wire Master (OWM)--------------------------------------------------------------------------------------------387