Megawin MPC82x54A User manual

MPC82x54A
8-bit micro-controller
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
©Megawin Technology Co., Ltd. 2005 All right reserved. 2007/12 version A7
MEGAWIN
Features .............................................................................................................................3
General Description ..........................................................................................................5
Order Information: ............................................................................................................5
Pin Description..................................................................................................................6
Pin Definition ...................................................................................................................6
Pin Configuration ...........................................................................................................10
Block Diagram ................................................................................................................ 11
Special Function Register ...............................................................................................12
Address Map ..................................................................................................................12
Bits Description..............................................................................................................13
Memory...........................................................................................................................15
Organization ...................................................................................................................15
RAM...............................................................................................................................16
Nonvolatile Registers:....................................................................................................16
Embedded Flash .............................................................................................................19
Functional Description....................................................................................................20
I/O Port Configuration ...................................................................................................20
Timer/Counter ................................................................................................................24
Interrupt..........................................................................................................................29
Watch Dog Timer ...........................................................................................................33
Universal Asynchronous Serial Port (UART) ................................................................35
Programmable Counter Array (PCA).............................................................................38
Serial Peripheral Interface (SPI) ....................................................................................47
Analog to Digital Converter...........................................................................................54
Built-In Oscillator ..........................................................................................................56
Power-Up and Low Voltage Detector and Reset............................................................56
Power Management........................................................................................................57
Reset and Boot Entrance ................................................................................................59
In System Programming and In Application Programming............................................60
In System Programming (ISP) .......................................................................................60
In-Application Program (IAP) .......................................................................................63
Avoid Inadvertent Data Lost from IAP/ISP ...................................................................64

2 MPC82x54A Data Sheet MEGAWIN
Instructions Set................................................................................................................65
Absolute Maximum Rating (MPC82E54A) ...................................................................68
DC Characteristics (MPC82E54A).................................................................................68
Absolute Maximum Rating (MPC82L54A) ...................................................................69
DC Characteristics (MPC82L54A).................................................................................69
Package Dimension.........................................................................................................70
Revision History .............................................................................................................74

MEGAWIN MPC82x54A Data Sheet 3
Features
zEnhanced 80C51 Central Processing Unit
z15.5K bytes on-chip flash memory with ISP/IAP capability
z256 bytes scratch-pad RAM and 256 bytes auxiliary RAM
zTwo-level code protection for flash memory access
zTwo 16-bits timer/counter
z7 sources, 4-level-priority interrupt capability
zOne enhanced UART with automatic address recognition and frame error detection
z15 bits Watch-Dog-Timer with 8-bit pre-scalar, one-time enabled
zSPI Master/Slave mode
zProgrammable Counter Array (PCA)
z10-bit Analog-to-Digital Converter (ADC)
zPower control: Idle mode and Power-Down mode, Power-down can be woken-up through
INT0 and INT1
z27 programmable I/O ports
zAlternative built-in 6MHz oscillator
zFully static operation
zExcellent noise immunity
zOn-Chip flash program/data memory:
- The data endurance of the embedded flash gets over 20,000 times.
- Greater than 100 years data rentention under room temperature
zVery low power consumption
zOperating Voltage:
- 4.5V~5.5V for MPC82E54A
- 2.4V~3.6V for MPC82L54A, minimum 2.7V requirement in flash write operation
(ISP/ICP/…...)
- Built-in Low-Voltage Detector and Reset circuit.
zOperating Temperature
- Industrial (-40°C to +85°C)*
zMaximum Operating Frequency:
- Up to 24MHz, Industrial range

4 MPC82x54A Data Sheet MEGAWIN
zMore package type:
PDIP-20/28:MPC82x54AE/AE2
PLCC-32: MPC82x54AP
SOP-20/28:MPC82x54AS/AS2
SSOP-28: MPC82x54AS3
TSSOP-20/28:MPC82x54AT/AT2
*: Tested by sampling

MEGAWIN MPC82x54A Data Sheet 5
General Description
MPC82x54A is a single-chip 8-bit micro-controller with instruction sets fully compatible with
industrial-standard 80C51 series microcontroller.
There is an excellent MCU kernel built in this device compared to general 80C51 MCUs those
take twelve oscillating cycles to finish an instruction, and this unique device could take only
one oscillating cycle to finish one instruction.
There is 15.5 Kbytes flash memory embedded which could be used as program or data. Also
the In-System Programming and In-Application Programming mechanisms are supported.
The data endurance of the embedded flash gets over 20,000 times, and 21 years data
retention is guaranteed.
The operation frequency reaches at 24 MHz. An user can apply a crystal oscillator for the
oscillating source, or alternatively uses the built in 6 MHz RC oscillator to save system cost.
The built in high performance 10-bit Analog-to-Digital Converter make it easy to sensing the
environment or implement a set of scan keys in low cost.
The UART and SPI interfaces make the device convenient to communicate with the peripheral
component: talking to a personal computer via RS-232 port, or communicating with a serial
memory.
The Pulse-Width-Modulator (PWM) mode in Programmable Counter Array (PCA) makes the
device to drive the peripheral step motor or LED in least cost.
The MPC82x54A is really the most efficient MCU adapted for simple control, such as:
electronic scales, remote controller, security encoder/decoder, and user interface controller.
Order Information:
Part Number Temperature
Range
Package Packing Operation Voltage
MPC82x54AE Industrial PDIP-20 Tube L: 3V / E: 5V
MPC82x54AE2 Industrial PDIP-28 Tube L: 3V / E: 5V
MPC82x54AP Industrial PLCC-32 Tube L: 3V / E: 5V
MPC82x54AS Industrial SOP-20 Tube L: 3V / E: 5V
MPC82x54AS2 Industrial SOP-28 Tube L: 3V / E: 5V
MPC82x54AS3 Industrial SSOP-28 Tube L: 3V / E: 5V
MPC82x54AT Industrial TSSOP-20 Tube L: 3V / E: 5V
MPC82x54AT2 Industrial TSSOP-28 Tube L: 3V / E: 5V

6 MPC82x54A Data Sheet MEGAWIN
Pin Description
Pin Definition
PIN NUMBER
Pin Name
PLCC-32 PDIP-28 PDIP-20
TYPE DESCRIPTION
P2.2 1 1 BU P2.2: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
P2.3 2 2 BU P2.3: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
RST 3 3 1 ID RST: =
A
high duty on this pin keeps for at
least 10us plus 36 oscillation cycles
will reset the device.
P3.0(RXD) 4 4 2 BU P3.0: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
RXD: =
Data Receiving pin for built-in UART
functionality.
P3.1(TXD) 5 5 3 BU P3.1: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
TXD: =
Data Transmitting pin for built-in
UART functionality.
P0.0 6 BU P0.0: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
XTALO 7 6 4 O XTALO: =
Output from the inverting oscillator
amplifier.
XTALI 8 7 5 I XTALI: =
Input to the inverting oscillator
amplifier.
P3.2(INT0) 9 8 6 BU P3.2: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
INT0: =
External interrupt source

MEGAWIN MPC82x54A Data Sheet 7
P0.1 10 BU P0.1: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
P3.3(INT1) 11 9 7 BU P3.3: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
INT1: =
External interrupt source
P3.4(ECI/T0) 12 10 8 BU P3.4: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
ECI: =
External Clock Input to
Programmable Counter Array (PCA)
T0: =
Alternative clock input to timer-0
P3.5 (CEX1/T1) 13 11 9 BU P3.5: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
CEX1: =
Capture Event trigger to
Programmable Counter Array (PCA)
module-1 or PWM output
T1: =
Alternative clock input to timer-1
P2.4(CEX3) 14 12 BU P2.4: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
CEX3: =
Capture Event trigger to
Programmable Counter Array (PCA)
module-3 or PWM output
P2.5 15 13 BU P2.5: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
VSS 16 14 10 G Groun d
P2.6 17 15 BU P2.6: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.

8 MPC82x54A Data Sheet MEGAWIN
P2.7 18 16 BU P2.7: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
P3.7(CEX0) 19 17 11 BU P3.7: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
CEX0: =
Capture Event trigger to
Programmable Counter Array (PCA)
module-0 or PWM output
P1.0(AIN0) 20 18 12 BU P1.0: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
AIN0: =
Alternative ADC input
P1.1(AIN1) 21 19 13 BU P1.1: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
AIN1: =
Alternative ADC input
P1.2(AIN2) 22 20 14 BU P1.2: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
AIN2: =
Alternative ADC input
P0.2 23 BU P0.2: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
P1.3(AIN3) 24 21 15 BU P1.3: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
AIN3: =
Alternative ADC input
P1.4(SS/AIN4) 25 22 16 BU P1.4: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
SS: =
Serial mode Selector or
Chip-Enabling pin for Serial
Peripheral Interface (SPI)
AIN4: =

MEGAWIN MPC82x54A Data Sheet 9
Alternative ADC input
P0.3 26 BU P0.3: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
P1.5(MOSI/AIN5) 27 23 17 BU P1.5: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
MOSI: =
Master data Output or Slave data
Input for Serial Peripheral Interface
(SPI)
AIN5: =
Alternative ADC input
P1.6(MISO/AIN6) 28 24 18 BU P1.6: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
MISO: =
Master data Input or Slave data
Output for Serial Peripheral Interface
(SPI)
AIN6: =
Alternative ADC input
P1.7
(SPICLK/AIN7)
29 25 19 BU P1.7: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
SPICLK: =
Serial Clock for Serial Peripheral
Interface (SPI)
AIN7: =
Alternative ADC input
P2.0(CEX2) 30 26 BU P2.0: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
CEX2: =
Capture Event trigger to
Programmable Counter Array (PCA)
module-2 or PWM output
P2.1 31 27 BU P2.1: =
General purpose 4-state I/O port with
internal pull-up mechanism; can be
configured as open-drain output.
VCC 32 28 20 P Power supply

10 MPC82x54A Data Sheet MEGAWIN
P2.2
1
4
5
13
14 20
21
29
30
P2.3
RST
P3.0
P3.1
P0.0
XTAL2
XTAL1
P3.2
P0.1
P3.3
P3.5
PLCC-32
P2.4
P2.5
VSS
P2.6 P2.7 P3.7
P1.1
P1.2
P0.2
P1.3
P1.4
P0.3
P1.5
P1.6
P1.7
P2.0
P2.1
VDD
P3.4
P1.0
Pin Configuration
RST
1
RXD/P3.0
2
TXD/P3.1
3
X
TAL2
4
X
TAL1
5
INT0/P3.2
6
INT1/P3.3
7
ECI/T0/P3.4
8
CEX1/T1/P3.5
9
V
SS
10
V
CC
P1.7/SPICLK/AIN7
P1.6/MISO/AIN6
P1.5/MOSI/AIN5
P1.4/SS/AIN4
P1.3/AIN3
P1.2/AIN2
P1.1/AIN1
P1.0/AIN0
P3.7/CEX0
SkinnyDIP-20/SOP-20/TSSOP-20
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2.0/CEX2
P2.1
P2.2
P2.3
P2.4/CEX3
P2.5 P2.7
P2.6
RST
RXD/P3.0
TXD/P3.1
1
XTAL2
2
XTAL1
3
INT0/P3.2
4
INT1/P3.3
5
ECI/T0/P3.4
6
CEX1/T1/P3.5
7
V
SS
8
V
CC
P1.7/SPICLK/AIN7
P1.6/MISO/AIN6
P1.5/MOSI/AIN5
P1.4/SS/AIN4
P1.3/AIN3
P1.2/AIN2
P1.1/AIN1
P1.0/AIN0
P3.7/CEX0
9
10 11
12
13
14
15
16
17
18
19
20
SkinnyDIP-28/SOP-28/SSOP-28/TSSOP-28

MEGAWIN MPC82x54A Data Sheet 11
Block Diagram
RAM ADDR
Register RAM256
Flash ROM
ISP
Address
Generator
Program
Counter
B Register ACC
TMP2 TMP1
ALU
Stack Pointer
Timer0
Timer1
UART
PSW WDT
Port0/2/3
Latch
Port1 Latch
Port0/2/3
Driver
Port1 Driver
Control
Unit
P1.0 ~ P1.7
P3.0~P3.5,P3.7
RESET
MPC82x54 Block Diagram
XTAL1 XTAL2 P1.0 ~ P1.7
ADC
8
PCA &
SPI
LVD/LVR
P0.0 ~ P0.3
P2.0 ~ P2.7
AUX-RAM256

12 MPC82x54A Data Sheet MEGAWIN
Special Function Register
Address Map
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
0F8H CH CCAP0H CCAP1H CCAP2H CCAP3H
00000000 00000000 00000000 00000000 00000000
0F0H B PCAPWM0 PCAPWM1 PCAPWM2 PCAPWM3
000000 xxxxxx00 xxxxxx00 xxxxxx00 xxxxxx00
0E8H CL CCAP0L CCAP1L CCAP2L CCAP3L
00000000 00000000 00000000 00000000 00000000
0E0H ACC WDTCR IFD IFADRH IFADRL IFMT SCMD ISPCR
00000000 0x000000 11111111 00000000 00000000 xxxxxx00 xxxxxxxx 00000000
0D8H CCON CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3
00xx0000 0xxxx000 x0000000 x0000000 x0000000 x0000000
0D0H PSW
00000000
0C8H
0C0H ADCTL ADCV PCON2
000000000 00000000 xxxxx000
0B8H IP SADEN ADCVL
x0000000 00000000 00000000
0B0H P3 P3M0 P3M1 IPH
1x111111 00000000 00000000 x0000000
0A8H IE SADDR
00000000 00000000
0A0H P2 TSTWD
11111111
098H SCON SBUF
00000000 xxxxxxxx
090H P1 P1M0 P1M1 P0M0 P0M1 P2M0 P2M1
11111111 00000000 0000 0000 xxxx0000 xxxx0000 00000000 00000000
088H TCON TMOD TL0 TL1 TH0 TH1 AUXR
00000000 00000000 00000000 00000000 00000000 00000000 000000xx
080H P0 SP DPL DPH SPISTAT SPICTL SPIDAT PCON
xxxx1111 00000111 00000000 00000000 00xxxxxx 00000100 00000000 00110000

MEGAWIN MPC82x54A Data Sheet 13
Bits Description
SYMBOL DESCRIPTION ADDR BIT ADDRESS AND SYMBOL
MSB LSB
INITIAL
VALUE
P0 Port 0 80H xxxx1111B
SP Stack Pointer 81H 00000111B
DPL Data Pointer Low 82H 00000000B
DPH Data Pointer High 83H 00000000B
SPISTAT SPI Status register 84H SPIF WCOL - - - - - - 00xxxxxxB
SPICTL SPI control register 85H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 00000100B
SPIDAT SPI data register 86H 00000000B
PCON Power Control 87H SMOD SMOD0 LVF POF GF1 GF0 PD IDL 00110000B
TCON Timer/Counter Control
Register
88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000B
TMOD Timer/Counter Mode
Register
89H GATE C/T M1 M0 GATE C/T M1 M0 00000000B
TL0 Timer Low 0 8AH 00000000B
TL1 Timer Low 1 8BH 00000000B
TH0 Timer High 0 8CH 00000000B
TH1 Timer High 1 8DH 00000000B
AUXR Auxiliary register 8EH T0x12 T1x12 URM0x6 EADCI ESPI ENLVFI - - 000000xxB
P1 Port 1 90H P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 11111111B
P1M0 P1 configuration 0 91H 00000000B
P1M1 P1 configuration 1 92H 00000000B
P0M0 P0 configuration 0 93H - - - - xxxx0000B
P0M1 P0 configuration 1 94H - - - - xxxx0000B
P2M0 P2 configuration 0 95H 00000000B
P2M1 P2 configuration 1 96H 00000000B
SCON Serial Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00000000B
SBUF Serial Buffer 99H xxxxxxxxB
P2 Port 2 A0H 11111111B
TSTWD For WDT test A7H Reserved for testing WDT 0x000000B
IE Interrupt Enable A8H EA EPCA_
LVD
ESPI_
ADC
ES ET1 EX1 ET0 EX0 00000000B
SADDR Slave Address A9H 00000000B
P3 Port 3 B0H P3.7 - P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 1x111111B
P3M0 P3 Configuration 0 B1H - 0x000000B
P3M1 P3 Configuration 0 B2H - 0x000000B
IPH Interrupt Priority High B7H - PPCAH
_LVD
PSPIH
_ADC
PSH PT1H PX1H PT0H PX0H x0000000B
IP Interrupt Priority Low B8H - PPCA
_LVD
PSPI
_ADC
PS PT1 PX1 PT0 PX0 x0000000B
SADEN Slave Address Mask B9H 00000000B
ADCVL ADC Result Low BEH - - - - - - ADCV.1 ADCV.0 00000000B
ADCTL ADC Control Register C5H ADCON SPEED1 SPEED0 ADCI ADCS CHS2 CHS1 CHS0 00000000B
ADCV ADC Result Register C6H ADCV.9 ADCV.8 ADCV.7 ADCV.6 ADCV.5 ADCV.4 ADCV.3 ADCV.2 00000000B
PCON2 Power Control 2 C7H - - - - - CKS2 CKS1 CKS0 xxxxx000B

14 MPC82x54A Data Sheet MEGAWIN
PSW Program Status Word D0H CY AC F0 RS1 RS0 OV - P 00000000B
CCON PCA counter control
register
D8H CF CR CCF3 CCF2 CCF1 CCF0 00xx0000B
CMOD PCA counter mode register D9H CIDL - - - - CPS1 CPS0 ECF 0xxxx000B
CCAPM0 PCA module0 mode
register.
DAH - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x0000000B
CCAPM1 PCA module1 mode
register.
DBH - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x0000000B
CCAP2M PCA module2 mode
register
DCH ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x0000000B
CCAP3M PCA module3 mode
register
DDH ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x0000000B
ACC Accumulator E0H 00000000B
WDTCR WDT control register E1H WRF - ENW CLW WIDL PS2 PS1 PS0 0x000000B
IFD ISP Flash data register E2H 11111111B
IFADRH ISP Flash Address High
Byte
E3H 00000000B
IFADRL ISP Flash Address Low
Byte
E4H 00000000B
IFMT ISP Mode Table E5H - - - - - - MS1 MS0 xxxxxx00B
SCMD ISP Sequential Command E6H xxxxxxxxB
ISPCR ISP Control Register E7H ISPEN SWBS SWRST CFAIL - WAIT.2 WAIT.1 WAIT.0 00000000B
CL PCA Counter Low Byte E9H 00000000B
CCAP0L Low byte of PCA
module-0 Compare/Capture
register
EAH 00000000B
CCAP1L Low byte of PCA
module-1 Compare/Capture
register
EBH 00000000B
CCAP2L Low byte of PCA
module-2 Compare/Capture
register
ECH 00000000B
CCAP3L Low byte of PCA
module-3 Compare/Capture
register
EDH 00000000B
B B Register F0H 00000000B
PCAPWM0 PCA PWM mode
auxiliary register 0
F2H - - - - - - EPC0H EPC0L xxxxxx00B
PCAPWM1 PCA PWM mode
auxiliary register 1
F3H - - - - - - EPC1H EPC1L xxxxxx00B
PCAPWM2 PCA PWM mode
auxiliary register 2
F4H - - - - - - EPC2H EPC2L xxxxxx00B
PCAPWM3 PCA PWM mode
auxiliary register 3
F5H - - - - - - EPC3H EPC3L xxxxxx00B
CH PCA Counter High Byte F9H 00000000B
CCAP0H High byte of PCA
module-0 Compare/Capture
register
FAH 00000000B
CCAP1H High byte of PCA
module-1 Compare/Capture
register
FBH 00000000B
CCAP2H High byte of PCA
module-2 Compare/Capture
register
FCH 00000000B
CCAP3H High byte of PCA
module-3 Compare/Capture
register
FDH 00000000B

MEGAWIN MPC82x54A Data Sheet 15
Memory
Organization
0000
3DFF
Address Space for MPC82x54A embedded Flash memory
AP
Memory
IAP
Memory
ISP
Memor
y
yyyy – 3DFF :=
Memory for In-System-
Programming code
yyyy is determined by OR0[5:4]
yyyy
xxxx
xxxx – yyyy :=
Memory for In-Application-
Programming data
xxxx is determined by OR1[7:0]
0000 – xxxx :=
User’s Application
xxxx is determined by OR1[7:0]
00-7F RAM, Access it via direct addressing
80-FF SFR, Access it via direct addressing
80-FF indirect on-chip RAM,
Access it via indirect addressing
00
80
FF
Address Space for MPC82x54A RAM
7F
0000-00FF On-Chip External auxiliary RAM.

16 MPC82x54A Data Sheet MEGAWIN
RAM
There are 512 bytes RAM built in MPC82x54A.
The user can visit the leading 128-byte RAM via direct addressing instructions, and we name
those RAM as direct RAM that occupies address space 00h to 7Fh.
Followed 128-byte RAM can be visited via indirect addressing instructions, and we name
those RAM as indirect RAM that occupied address space 80h to FFh.
There are extra 256 bytes RAM can be visited via MOVX @Ri or @DPTR instructions which
are named external RAM. When using MOVX @DPTR, the content in DPH is ignored. None
of P0 status and P2 status is affected during MOVX instruction.
Nonvolatile Registers:
There are four Nonvolatile Registers named OR0, OR1,OR2, and OR3 individually. They are
designed to configure the MPC82x54A, i.e.,: to decide to use internal RC oscillator or use
crystal oscillator as oscillating source, or to allocate the built-in flash for application program,
application data and In-System-Program code.
Generally, the only way to program those four nonvolatile registers is making use of a popular
NVM writer, such as: Hi-Lo System All-11, Leaper-48 and Megawin-Provided MCU writer. The
user’s program and the ISP program never can change those option registers.
NVM register: OR0 (Option Register 0):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
LVFWP ENLVR ISPAS1 ISPAS0 HWBS reserved1SB LOCK
LVFWP: = Low-Voltage-Flag-Write-Protecting bit.
0:=
inhibit the flash read/write action via ISP/IAP mechanism while the power supply drops
under a specific voltage level. Typically, the voltage threshold is around 3.7V/2.3V (Operate
in the 5V / 3V) for Fosc =12MHz.
1:= (default)
No inhibition on the flash-writing action.
ENLVR: =Enable-Low-Voltage-Reset
0:=
Clearing the bit will reset the device while the power supply drops under a specific voltage
level. Typically, the voltage threshold is around 3.7V/2.3V (Operate in the 5V / 3V) for
Fosc = 12MHz.
1:= (default)
Setting the bit implies never reset the device in spite of voltage dropping.

MEGAWIN MPC82x54A Data Sheet 17
{ISPAS1, ISPAS0}:= ISP-Address-Start
{0,0}:=
Set the ISP start address 3000H. (ISP code could take 3.5K bytes)
{0,1}:=
Set the ISP start address 3400H. (ISP code could take 2.5K bytes)
{1,0}:=
Set the ISP start address 3800H. (ISP code could take 1.5K bytes)
{1,1}:= (default)
Express no ISP code.
HWBS: = Hardware-Boot-Selector
0:= (default)
Clearing the bit is to configure the device to boot from ISP program after power-up.
1:=
Setting the bit is to configure the device to boot normally from user’s application program
after power-up.
In fact, the boot entrance is determined by register SWBS from SFR ISPCR ignoring the boot
comes from RST-pin press, software-trigger, or power-up. However, if a boot happens and that
boot comes from power-up action, the device will first load the complement of the HWBS to SWBS,
and decides the boot entrance according to the state of bit SWBS. So the HWBS is named
Hardware Boot Selector. It influence on power-up boot, but does not influence on the boot from
RST-pin or software-trigger.
reserved1:= The bit is reserved for afterward user, and should be left at set.
The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the
device.
SB: = Used to decide if the program code will be Scrambled while it is dumped.
0:=
Code dump from Writer is scrambled.
1:= (default)
Code dump from Writer is transparent.
LOCK: = Used to decide if the program code will be Locked against the popular writer.
0:=
Code dumping from Writer is locked.
1:= (default)
Permit code dumping from general Writers.
NVM register: OR1 (Option Register 1):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
-
OR1 [7:1]:= Used to set the boundary of IAP memory
The user’s application program can change only the IAP flash memory, not of AP flash memory
itself nor the ISP flash memory. The IAP memory is defined between address scope
OR1 [7:1]*512 and ISP-Address-Start. Setting the OR1 [7:1] 1111111Bmeans no IAP memory.
NVM register: OR2 (Option Register 2):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
reserved1OSCDN HWBS2 reserved1- reserved1ENROSC reserved1
reserved1:= The bit is reserved for afterward user, and should be left at set.

18 MPC82x54A Data Sheet MEGAWIN
The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the
device.
OSCDN: = Used to adjust the behavior of crystal oscillator.
0:=
The current gain of crystal oscillator amplifier is reduced. It will bring
help to EMI reducing and improve the power consumption. Dealing with application does
not need high frequency clock (under 12MHz). It is recommended to do so.
1:= (default)
The current gain of crystal oscillator is enough for oscillator to start oscillating up to 24MHz.
HWBS2:= Used to adjust the behavior of crystal oscillator.
0:=
Force the boot entrance as ISP code for both of power-up boot and RST-pin boot.
1:= (default)
Transfer the determination of boot entrance to HWBS.
By using HWBS2, ISP program may be triggered to run by RESET pin. (See Boot and
Reset section)
ENROSC: = Used to determined if to enable the built-in RC oscillator.
0:=
Clearing the bit will enable the built-in RC oscillator, and set that oscillator as the oscillating
source
1:= (default)
Setting the bit means to disable the built-in RC oscillator.
NVM register: OR3 (Option Register 3):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
reserved1reserved1HWENW - HWWIDL HWPS2 HWPS1 HWPS0
reserved1:= The bit is reserved for afterward user, and should be left at set.
The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the
device.
HWENW: = Hardware Enable Watch-dog-timer
0:=
Clearing the bit will automatically enable the watch-dog-timer after power-up immediately.
HWWIDL, HWPS2, HWPS1 and HWPS0 will be loaded Into SFR WDTCR after power-up if
and only if HWENW =0.
1:= (default)
No Hardware enable for Watch-dog-timer.
HWWIDL: = Hardware enables reset from Watch-dog-timer in spite of the MCU lies idle.
0:=
Watch-dog-timer is also suspended while the MCU lies idle.
1:= (default)
Enable watch-dog-timer to keep working in spite of the MCU has been put into idle mode.
If the bit HWENW is left 1, the bits HWWIDL, HWPS2, HWPS1 and HWPS0 make no sense.
{HWPS2, HWPS1, HWPS0}:= Hardware Watch-dog-timer Pre-Scalar
If the bit HWENW is cleared to 0, those bits will be loaded into SFR WDTCR after power-up.
Those three bits set the pre-scalar of the watch-dog-timer.
If the bit HWENW is left 1, those three bits makes no sense.
{0,0,0}:=
The frequency of the clock source for the watch-dog-timer is divided by 2.
{0,0,1}:=
The frequency of the clock source for the watch-dog-timer is divided by 4.

MEGAWIN MPC82x54A Data Sheet 19
{0,1,0}:=
The frequency of the clock source for the watch-dog-timer is divided by 8.
{0,1,1}:=
The frequency of the clock source for the watch-dog-timer is divided by 16
{1,0,0}:=
The frequency of the clock source for the watch-dog-timer is divided by 32
{1,0,1}:=
The frequency of the clock source for the watch-dog-timer is divided by 64
{1,1,0}:=
The frequency of the clock source for the watch-dog-timer is divided by 128
{1,1,1}:=
The frequency of the clock source for the watch-dog-timer is divided by 256
Embedded Flash
There is totally 15.5 Kbyte flash embedded in the MPC82x54A.
The user can configure the whole flash to store the application program, can configure the
flash for both storage of application (AP) program and In-System-Program (ISP) code, or
even can configure the flash for storage of AP, ISP, and In-Application-Program (IAP) memory.
While the program counter of MPC82x54A is spanning over 3DFFH, the device will do nothing.
The user can develop own ISP program, and put it into the embedded flash that addressed
from 3000H, 3400H, or 3800H, meanwhile configure OR0[5:4], and set OR0[3] to 0, and to
direct the device to boot from own ISP code.
If there is requirement from the user’s application program to store nonvolatile parameters,
the user can allocate part of the embedded flash as IAP memory by configure OR1 [7:1].

20 MPC82x54A Data Sheet MEGAWIN
Functional Description
I/O Port Configuration
All 27 port pins on MPC82x54A may be independently configured to one of four modes:
quasi-bidirectional (standard 8051 port output), push-pull output, open-drain output or
input-only. All port pins default to quasi-bidirectional after reset. Each port pin has a
Schmitt-triggered input for improved input noise rejection. During power-down, all the
Schmitt-triggered inputs are disabled with the exception of P3.2 and P3.3, which may be used
to wake-up the device. Therefore P3.2 and P3.3 should not be left floating during
power-down.
There are several special function registers designed to configure those I/O ports.
SFR: P0M0 (P0 Configuration 0)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
- - - - P0M03 P0M02 P0M01 P0M00
SFR: P0M1 (P0 Configuration 1)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
- - - - P0M13 P0M12 P0M11 P0M10
SFR: P1M0 (P1 Configuration 0)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
P1M07 P1M06 P1M05 P1M04 P1M03 P1M02 P1M01 P1M00
SFR: P1M1 (P1 Configuration 1)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
P1M17 P1M16 P1M15 P1M14 P1M13 P1M12 P1M11 P1M10
SFR: P2M0 (P2 Configuration 0)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
P2M07 P2M06 P2M05 P2M04 P2M03 P2M02 P2M01 P2M00
SFR: P2M1 (P2 Configuration 1)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
P2M17 P2M16 P2M15 P2M14 P2M13 P2M12 P2M11 P2M10
SFR: P3M0 (P3 Configuration 0)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
P3M07 P3M06 P3M05 P3M04 P3M03 P3M02 P3M01 P3M00