MiTAC 8081 User manual

BY: Sissel Diao Sissel Diao
Repair Technology Research Department /EDVD
Repair Technology Research Department /EDVD
Jul. 2003
SERVICE MANUAL FOR
8081
80818081
8081
SERVICE MANUAL FOR
SERVICE MANUAL FOR
8081
80818081
8081
8081
80818081
8081

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Contents
1. Hardware Engineering Specification …………………………………………………………………
1.1 Introduction …………………………………………………………………………………………………………
1.2 Hardware System ……………………………………………………………………………………………………
1.3 Other Functions ……………………………………………………………………………………………………..
1.4 Peripheral Components …………………………………………………………………………………………….
1.5 Power Management …………………………………………………………………………………………………
1.6 Appendix 1 : Intel 82801DBM ICH4-M GPIO Definitions ………………………………………………………
1.7 Appendix 2 : MiTAC 8081 Product Specification ………………………………………………………………..
2. System View and Disassembly ………………………………………………………………………...
2.1 System View …………………………………………………………………………………………………………
2.2 System Disassembly …………………………………………………………………………………………………
3. Definition & Location of Connectors / Switches ……………………………………………………..
3.1 Mother Board ……………………………………………………………………………………………………….
3.2 DC to DC Board …………………………………………………………………………………………………….
4. Definition & Location of Major Components ………………………………………………………..
4.1 Mother Board ……………………………………………………………………………………………………….
5. Pin Description of Major Component …….………………………………………………………….
5.1 Intel Banias Pentium M Processor …………………………………………………………………………………
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Contents
5.2 Intel 82855GM Memory Controller Hub (GMCH) ………………………………………………………………
5.3 Intel 82801DBM I/O Controller Hub Mobile (ICH4-M) …………………………………………………………
6. System Block Diagram ………………………………………………………………………………...
7. Maintenance Diagnostics ………………………………………………………………………………
7.1 Introduction …………………………………………………………………………………………………………
7.2 Error Codes ………………………………………………………………………………………………………….
7.3 Maintenance Diagnostics ……………………………………………………………………………………………
8. Trouble Shooting ………………………………………………………………………………………
8.1 No Power …………………………………………………………………………………………………………….
8.2 No Display ……………………………………………………………………………………………………………
8.3 VGA Controller Failure LCD No Display …………………………………………………………………………
8.4 External Monitor No Display ………………………………………………………………………………………
8.5 Memory Test Error …………………………………………………………………………………………………
8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………….
8.7 Hard Driver Test Error …………………………………………………………………………………………….
8.8 CD-ROM Driver Test Error ……………………………………………………………………………………….
8.9 USB Port Test Error ………………………………………………………………………………………………..
8.10 Audio Failure ………………………………………………………………………………………………………
8.11 LAN Test Error ……………………………………………………………………………………………………
8.12 PC Card & 1394 Socket Failure …………………………………………………………………………………
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Contents
9. Spare Parts List ………………………………………………………………………………………..
10. System Exploded Views ………………………………………………………………………………
11. Circuit Diagram ………………………………………………………………………………………
12. Reference Material …………………………………………………………………………………...
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1.1 Introduction
1. Hardware Engineering Specification
This document describes the brief introduction for MiTAC 8081 portable notebook computer system.
1.1.1 General Description
The MiTAC 8081 model is designed for Intel Banias/Dothan processor with 400MHz FSB with Micro-FCPGA
package. It can support Banias 1.3GHz~1.7GHz CPU/Dothan CPU with 1.8GHz or above.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface
(ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can
be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as AC Power indicator, Wireless on/off indicator, Battery status indicator, CD-ROM, HDD, NUM LOCK,
CAP LOCK, SCROLL LOCK. It also equipped with LAN, 56K Fax MODEM, 4 USB port, 3D stereo audio functions,
and audio line out, external microphone in function.
The memory subsystem supports one expansion DDR SDRAM slot with unbuffered PC1600/PC2100 DDR-SDRAM,
and 16Mx16 DDR RAM on board 256MB.
1.1.2 System Overview

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The Montara-GM GMCH Host Memory Controller integrates a high performance host interface for Intel Banias
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, Digital Video port
(DVOB & DVOC) interface, and Intel Hub interface Technology connecting with Intel 82801DBM ICH4-M.
The Intel ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller
with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Intel Hub
interface technology.
The VIA VT6105LOM “Rhine III” Ethernet controller is a cutting edge, feature-rich, and cost-competitive single
ASIC chip solution for PC “LAN On Motherboard” applications or Low Cost NIC applications. The 6105LOM eases
server processor utilization by optimizing throughput between NIC and PCI bus allowing data transfers of up to at
200Mbps in full duplex mode, without using the system CPU. The VT6105LOM contains advanced power
management feature for low power consumption including Wake On LAN (WOL) and is implemented using a low
power 0.22-micron design.
The R5C551 is the single chip solution offering single PCI bus-PC Card Bridge. The R5C551 is compliant with the
latest specification in both PC card and IEEE 1394. The R5C551 has two PCI functions compliant, the PC Card
interface and the IEEE 1394 interface. The PC Card controller of the R5C551 is compliant with PC Card Standard
Release 7.0. The R5C551 provides features that make it the best choice for bridging between the PCI bus and PC
Cards, and supports any combination of 16-bit (Card-16), and CardBus (Card-32) PC Cards in one socket, powered at
5V or 3.3V, as required. The R5C551 provides the IEEE1394 OHCI-Link and two ports the IEEE1394 PHY that are
compliant with the IEEE1394-1995, IEEE1394a-2000 and the latest 1394 OHCI specifications. The R5C551 data rate
is capable of 100, 200, and 400Mbits per second.The R5C551 is compliant with the latest PCI Bus Power
Management Specification, and provides several low-power modes that enable the host power system to further reduce
power consumption.

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The NS PC87393 LPC Super I/O device is targeted for a wide range of portable applications. PC99 and ACPI
compliant, it also incorporates: a Floppy Disk Controller (FDC), two enhanced Serial Ports (UARTs), one with Fast
Infrared (FIR, IrDA 1.1 compliant), General-Purpose Input/Output (GPIO) support for a total of 32 ports, Interrupt
Serialize for Parallel IRQs and an enhanced WATCHDOG timer.
The NS PC87393 Super I/O controller integrates the standard PC I/O functions: LPC bus interface, X-Bus Extension
for read and write operations, floppy disk interface and one EPP/ECP capable parallel port. Like all LPC Super I/O
devices, the PC87393 offers a single-chip solution to the most commonly used PC I/O peripherals to provide for the
increasing number of multimedia application.
CMI9738-S is a 4CH AC97 CODEC, applicable for major MB chipsets of Intel, VIA, Ali, and SIS. CMI9738-S is
ideal for PC2001-compliant desktops, notebooks, and home entertainment PCs where high-quality audio is a must.
The specially-designed 4CH hardware architecture of CMI9738-S allows multi-channel south bridge to playback 4CH
audio. As to the cost concern, CMI9738-S integrates the earphone buffer, analog CD differential interface, and analog
switch for rear channel audio to Line-in for traditional 3 jacks audio port to output 4 channels audio. CMI9738-S also
has built-in PLL to save additional crystal. Last but not least, CMI9738-S provides HRTF 3D audio which interface
compatible with EAX/ A3D/DirectSound3D. In addition, it provides Sensaura3D audio option. In that regard,
the audio quality of CMI9738-S is fabulous beyond general expectation.
The H8/F3437 is a high performance micro controller with a fast H8/300 CPU core and a set of on-chip supporting
functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication
interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions
needed in control system configurations, so that compact, high performance systems can be implemented easily.

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A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
CPU : Intel Banias/Dothan processors in Micro-FCPGA package
Synthesizer : ICS950810
North Bridge : Montara-GM GMCH
South Bridge : ICH4-M
Super I/O controller : NS PC87393
Keyboard System : Hitachi H8/F3437 Universal Controller
FAX/MODEM : Billonton MDC56S-I 56Kbps Fax Modem
LAN single chip : VT6105LOM
PCMCIA controller : R5C551
AC’97 Codec : CMI9738-S
Thermal sensor : ADM1021A
System Flash Memory (BIOS)
1.1.3 System Parts

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Intel Banias/Dothan Processors with 478 pins Micro-FCPGA package .
The first Intel mobile processor with the Intel NetBurst micro-architecture which features include hyper-
pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic
execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD
Extensions 2 (SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia
applications including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four
times per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and
frequency between two performance modes.
1.2 Hardware System
1.2.1 CPU Module

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System frequency synthesizer: ICS950810
Programmable output frequency, divider ratios, output rise/fall time, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions.
Programmable watchdog safe frequency.
Support I2C Index read/write and block read/write operations.
Use external 14.318MHz crystal.
1.2.3 Montara-GM GMCH IGUI 3D Graphic DDR/SDR Chipset
Montara-GM GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel Banias
processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface,
and Intel®’ I/O Hub architecture INTEL 82801DBM ICH4-M.
Montara-GM GMCH Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated
on-die termination to support Intel Banias processors. Montara-GM GMCH provides a 12-deep In-Order-Queue to
support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video
Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Banias series based
PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth
demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition
1.2.2 Synthesizer

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to integrated GUI, Montara-GM GMCH also can support external AGP slot with AGP 1X/2X/4X capability and
Fast Write Transactions. A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect
Montara-GM GMCH and INTEL 82801DBM ICH4-Mtogether. Intel®’ I/O Hub architecture is developed into
three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master
devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link
Encoder/Decoder in INTEL 82801DBM ICH4-M to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded
I/O Link layer to/from Montara-GM GMCH, and the Multi-threaded I/O Link Encoder/Decoder in Montara-GM
GMCH to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from Intel 82801DBM ICH4-M.
An Unified Memory Controller supporting DDR266 DRAM is incorporated, delivering a high performance data
transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP
master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the
CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The Montara-GM GMCH adopts
the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing
the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB.
Processor/Host Bus Support
- Intel®Banias processor
- 2X Address, 4X data
- Support host bus Dynamic Bus Inversion (DBI)
- Supports system bus at 400MT/s (100 MHz)
- Supports 64-bit host bus addressing
- 8-deep In-Order-Queue
Features :

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- AGTL+ bus driver technology with integrated GTL termination resistors and low voltage operation (1.05V)
- Supports Enhanced Intel®SpeedStepTM Technology (EIST) and Geyserville III
- Support for DPWR# signal to Banias processor for PSB power management
Memory System
- Directly supports one DDR channel, 64-bts wide (72-b with ECC).
- Supports 200-MHz and 266-MHz DDR devices with max of 2 Double-Sided SO-DIMMs(4 rows populated)
with unbuffered PC1600/PC2100 DDR(with ECC).
- Supports 128-Mb, 256-Mb and 512-Mbit technologies providing maximum capacity of 1-GB with only x 16 devices.
- All supported devices have 4 banks.
- Supports up to 16 simultaneous open pages.
- Supports page sizes of 2KB, 4KB, 8KB, and 16KB. Page size is individually selected for every row.
- UMA support only.
System interrupt
- Supports 8259 and Processor System Bus interrupt delivery mechanism
- Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface
- MSI sent to the CPU through the system Bus
- From IOxAPIC in ICH4-M
- Provides redirection for upstream interrupts to the System Bus
- Video Stream Decoder
- Improved HW Motion Compensation for MPEG2
- All format decoder (18 ATSC formats) supported
- Dynamic Bob and Weave support for Video Streams

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- Software DVD at 60 fields/second and 30 frames/second full screen
- Support for 720x480 pixel resolution DVD quality encoding at low CPU utilization
- Video Overlay
- Single high quality scalable overlay and second Sprite to support second overlay
- Multiple overlay functionality provided via Arithmetic Stretch Blt
- Direct YUV from Overlay to TV-out
- Independent Gamma Correction
- Independent Brightness / Contrast / Saturation
- Independent Tint / Hue support
- Destination Color keying
- Source Chromakeying
- Maximum source resolution of 1920x1080 pixels
- Maximum overlay clock of 133 MHz/200 MHz provides a pixel resolution up to 1600x1200@ 60Hz or 1280x
1024@ 85 Hz
Display
- Analog Display Support
- 350 MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor up to 1800
x1350@ 85 Hz.
- Accompanying I2C and DDC channels provided through multiplexed interface Hot-plug and display support
- Dual independent pipe with single display support Simultaneous: Same images and native display timings on
each display device
- DVO (DVOB) support
- Digital video out port DVOB with 165-MHz dot clock on 12-bit interface

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-- Variety of DVO devices channel
-- Compliant with DVI Specification 1.0, thereby providing support for a flat panel up to 2048x1536 pixel
resolution, or digital CRT up to 1920x1080 pixel resolution
- Dedicated LFP (local flat panel) interface
-- Single or dual channel LVDS panel support up to SXGA+ panel resolution with frequency range from
25MHz to 112MHz per channel
-- SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock
-- Supports data format of 18bpp
-- Direct YUV from Overlay to TV-out
-- LCD panel power sequencing compliant with SPWG timing specification
-- Compliant with ANSI/TIA/EIA –644-1995 spec
-- Integrated PWM interface for LCD backlight inverter control
-- Bi-linear Panel fitting
- Tri-view support through LFP interface, DVO ports and CRT
- Internal Graphics Features
- Core Frequency
-- Display Core frequency of 133MHz
-- Render Core frequency of 133MHz
- 2D Graphics Engine
- Optimized 128 bit BLT engine
- Ten programmable and predefined monochrome patterns
- Alpha Stretch Blt (via 3D pipeline)
- Anti-aliased lines
- Hardware-based BLT Clipping & Scissoring
- 32-bit Alpha Blended cursor

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- Programmable 64*64 3-color Transparent cursor
- Color Space Conversion
- 3 Operand Raster BLTs
- 8-bit, 16-bit, and 32-bit color
- ROP support
- DIB translation and Linear/Title addressing
- 3D Graphics Engine
- 3D Setup and Render Engine
- Viewpoint Transform and Perspective Divide
- Triangle Lists, Strips and Fans support
- Indexed Vertex and Flexible Vertex formats
- Pixel accurate Fast Scissoring and Clipping operation
- Back-face Culling support
- DirectXTM and OGL Pixelization rules
- Anti-Aliased Lines support
- Sprite Points support
- Zone Rendering
- Provides the highest sustained fill rate performance in 32-bit color and 24-bit W mode
- High quality performance Texture Engine
- 266 MegaTexel/speak performance
- Per Pixel Perspective corrected Texture Mapping
- Single Pass Texture Composting (Multi-Texture) at rate
- Enhanced Texture Blending functions

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- Twelve Level of Detail MIP Map Sizes from 1x1 to 2Kx2K
- Numerous Texture formats including 32-bit RGBA
- Alpha and Luminance Maps
- Texture Chromakeying
- Bilinear, Trilinear, Anisotropic MIP-Mapped Filtering
- Cubic Environment Reflection Mapping
- Embossed Bump-mapping
- DXTn Texture Decompression
- 3D Graphics Rasterrization enhancements
- One Pixel per Clock
- Flat and Gouraud Shading
- Color Alpha Blending for Transparency
- Vertex and Programmable Pixel Fog and Atmospheric effects
- Color Specular Lighting
- Vertex and Programmable Pixel Fog and Atmospheric effects
- Z Bais support
-Dithering
- Line and Full-Scence Anti-Aliasing
- 16 and 24-bit Z Buffering
- 16 and 24-bit W Buffering
- 8-bit Stencil Buffering
- Double and Triple Render Buffer support
- 16 and 32 –bit color

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- Destination Alpha
- Vertex Cache
- Maximum 3D resolution of 1600x1200 x32 bpp at 85 Hz
- Optimal 3D resolution supported
- Fast Clear support
- ROP support
HUB Interface for ICH4
- 266 MB/s point to point hub interface to ICH4-M
- 66-M Hz base clock
- Supports the following traffic types to the ICH4-M
- Hub interface-to DRAM
- CPU-to-Hub interface
- Messaging
- MSI interrupt messages
- Power Management state change
- SMI, SCI, and SERR error indication
- Power Management
-- SMRAM space remapping to A0000h (128-KB)
-- Supports extended SMRAM space above 256- MB ,additional 1 MB TSEG from top of Memory, cacheable
(cacheability controlled by CPU)
-- APM rev 1.2 compliant power management
-- Supports Suspend to System Memory(S3),Suspend to Disk(S4) and Hard Off/Total Reboot(S5)
-- ACPI 1.0b,2.0 Support

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1.2.4 I/O Controller Hub : Intel 82801DBM
The Intel 82801DBM ICH4-M integrates three Universal Serial Bus 2.0 Host Controllers, the Audio Controller with
AC 97 Interface, the IDE Master/Slave controllers, and Intel®’ I/O Hub architecture. The PCI to LPC Bridge, I/O
Advanced Programmable Interrupt Controller, legacy system I/O and legacy power management functionalities are
integrated as well.
The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers
with six USB ports delivering 480 Mb/s bandwidth and rich connectivity. Besides, Legacy USB devices as well as
over current detection are also implemented.
The Integrated AC97 v2.3 compliance Audio Controller that features a 7-channels of audio speaker out and HSP v.90
modem support. Additionally, the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting
multiple audio codecs with one separate modem codec.
The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode transfers
up to 16 Mbytes/sec and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that
sustain the high data transfer rate in the multitasking environment.
Intel 82801DBM ICH4-M supports 6 PCI masters and complies with PCI 2.2 specification. It also incorporates the
legacy system I/O like: two 82C37 compatible DMA controllers, Channels 0-3 are hardwired to 8 bit, three 8254
compatible programmable 16-bit counters channels 5-7, hardwired keyboard controller and PS2 mouse interface (not
use in MiTAC 8080 model), Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt
controllers. Besides, the I/O APIC managing up to 14 interrupts with both Serial and FSB interrupt delivery modes is
supported.

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The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2
compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and
power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for
specific application. In addition, the Intel 82801DBM ICH4-M supports Deeper Sleep power state for Intel Mobile
processor.
A high bandwidth and mature Intel®’ I/O Hub architecture is incorporated to connect Montara and Intel 82801DBM
ICH4-M Hub interface together. Intel®’ I/O Hub architecture is developed.
PCI Bus Interface
Supports PCI Revision 2.2 Specification at 33 MHz
133 MB/sec maximum throughput
Supports up to six master devices on PCI
One PCI REQ/GNT pair can be given higher arbitration priority (intended for external 1394 host controller)
Support for 44-bit addressing on PCI using DAC protocol Integrated LAN Controller
WfM 2.0 and IEEE 802.3 compliant
LAN Connect Interface (LCI)
10/100 Mbit/sec Ethernet support_ Integrated IDE Controller
Supports “Native Mode” register and interrupts
Independent timing of up to 4 drives, with separate primary and secondary IDE cable connections
Features :

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Ultra ATA/100/66/33, BMIDE and PIO modes
Tri-state modes to enable swap bay
USB
Includes three UHCI host controllers that support six external ports
New: Includes one EHCI high-speed USB 2.0 Host Controller that supports all six ports
New: Supports a USB 2.0 high-speed debug port
Supports wake-up from sleeping states S1–S5
Supports legacy keyboard/mouse software AC-Link for Audio and Telephony CODECs
Supports AC ’97 2.3
New: Third AC_SDATA_IN line for three codec support
New: Independent bus master logic for seven channels (PCM In/Out, Mic 1 input, Mic 2 input, modem in/out,
S/PDIF out)
Separate independent PCI functions for audio and modem
Support for up to six channels of PCM audio output (full AC3 decode)
Supports wake-up events Interrupt Controller
Support up to eight PCI interrupt pins
Supports PCI 2.2 message signaled interrupts
Two cascaded 82C59 with 15 interrupts
Integrated I/O APIC capability with 24 interrupts