MiTAC 8666 User manual

BY: Star Meng
Repair Technology Research Department /EDVD
Repair Technology Research Department /EDVD
Apr.2005 / R01
SERVICE MANUAL FOR
8666
86668666
8666
SERVICE MANUAL FOR
SERVICE MANUAL FOR
8666
86668666
8666
8666
86668666
8666

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1. Hardware Engineering Specification ………………………………………………………………………
1.1 Introduction ………………………………………………………………………………………………………………..
1.2 System Hardware Parts …………………………………………………………………………………………………...
1.3 Other Functions ……………………………………………………………………………………………………………
1.4 Power Management ……………………………………………………………………………………………………….
1.5 Appendix 1 : VIA VT8235CE GPIO Definitions ………………………………………………………………………..
1.6 Appendix 2 : W83L950D KBC Pins Definitions …………………………………………………………………………
1.7 Appendix 3 : 8666 External Specification ………………………………………………………………………………..
2. System View and Disassembly ……………………………………………………………………………..
2.1 System View ……………………………………………………………………………………………………………….
2.2 Tools Introduction …………………………………………………………………………………………………………
2.3 System Disassembly ……………………………………………………………………………………………………….
3. Definition & Location of Connectors / Switches …………………………………………………………..
3.1 Mother Board ……………………………………………………………………………………………………………...
3.2 Daughter Board ……………………………………………………………………………………………………………
4. Definition & Location of Major Components ……………………………………………………………..
4.1 Mother Board ……………………………………………………………………………………………………………...
5. Pin Description of Major Components ….…………………………………………………………………
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5.1 Intel Pentium M Processor CPU …………………………………………………………………………………………
5.2 PN800 North Bridge ………………………………………………………………………………………………………
5.3 VT8235CE South Bridge ….……………………………………………………………………………………………...
6. System Block Diagram ……………………………………………………………………………………..
7. Maintenance Diagnostics …………………………………………………………………………………..
7.1 Introduction ……………………………………………………………………………………………………………….
7.2 Error Codes ……………………………………………………………………………………………………………….
7.3 Debug Tool …………………………………………………………………………………………………………………
8. Trouble Shooting ……………………………………………………………………………………………
8.1 No Power …………………………………………………………………………………………………………………..
8.2 No Display …………………………………………………………………………………………………………………
8.3 LCD No Display or Picture Abnormal …………………………………………………………………………………..
8.4 External Monitor No Display or Color Abnormal ………………………………………………………………………
8.5 TV Test Error ……………………………………………………………………………………………………………..
8.6 Memory Test Error ……………………………………………………………………………………………………….
8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………………..
8.8 Hard Drive Test Error ……………………………………………………………………………………………………
8.9 CD-ROM Drive Test Error ………………………………………………………………………………………………
8.10 USB Port Test Error …………………………………………………………………………………………………….
8.11 PC Card Socket Test Error ……………………………………………………………………………………………..
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Contents
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8.12 Mini-PCI Socket Test Error …………………………………………………………………………………………...
8.13 Audio Test Error …………………………………………………………………………………………………………
8.14 LAN Test Error ………….……………………………………………………………………………………………….
9. Spare Parts List ……………………………………………………………………………………………..
10. System Exploded Views ……………………………………………………………………………………
11. Circuit Diagram ……………………………………………………………………………………………
12. Reference Material ………………………………………………………………………………………..
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1.1 Introduction
1. Hardware Engineering Specification
This document describes the brief introduction for MiTAC 8666 portable notebook computer system
1.1.1 General Description
1.1.2 System Overview
The MiTAC 8666 model is designed for Intel Mobile Pentium-M Processor Banias 1.3G ~ 1.5GHz or Dothan 1.3G ~
2.1GHz with 400MHz, and Dothan 1.6G ~ 2.1GHz with 533MHz FSB with Micro-FCPGA package.
This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard
hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface
(ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can
be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system
status, such as Wireless Lan indicator, Power indicator, Battery status indicator, ODD, HDD, Num Lock, Caps Lock,
Scroll Lock, It also equipped with LAN, 56K Fax MODEM, 4 USB ports, S-Video and audio line out, external
microphone function.
The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC3200 DDR400 SDRAM.
The VIA PN800 Mobile North Bridge integrates a high performance CPU interface for Intel Pentium 4 / Pentium-M
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processor, a full featured AGP port controller, Integrated Graphics with 2D/ 3D/ Video Controllers, a advanced high-
performance DDR400 SDRAM controller, and high bandwidth Ultra V-Link host controller connecting with VIA
VT8235CE South Bridge.
The VIA VT8235CE integrates Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with
AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Inter-operable
with VIA Host-to-V-Link Host Controller.
The VIA VT6103L is a Fast Ethernet 10 / 100 1-port PHY / Transceiver with MII interface, and meet all applicable
IEEE 802.3, 10Base-T and 100Base-Tx standards.
The ENE CB1410 CardBus controller functions as a single slot PCI to Cardbus bridge. The CB1410 compliant with
PCI Local Bus Specification Rev2.2, PC99 System Design Guide, and PC Card Standard 8.0.
The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded control.
These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus interface, host
interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so
that compact, high performance systems can be implemented easily.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME,
Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering
IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power
shutdown.
Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Hardware Parts
CPU Mobile Pentium-M Processor 1.3G ~ 1.9GHz
Core logic VIA PN800 + VIA VT8235CE chipset
VGA Control North Bridge Integrated
System BIOS SST49LF040
Memory DDR RAM :
DDR333 Nanya NT512D64S8HBAFM-6K
DDR400 Micron, MT8VDDT3264HD
Video Memory Share memory
Clock Generator ICS 950902
LVDS VIA VT1634AL
TV VIA VT1623M
LAN PHY VIA VT6103L
PCMCIA ENE CB1410
Audio System AC97 CODEC: Advance Logic, Inc, ALC655
Power Amplifier: TI TPA0212
Modem AC97 Link: MDC (Mobile Daughter Card)!
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1.2.1 Intel Banias Processors in Micro-FCPGA Package
Intel Banias Processors with 593 pins Micro-FCBGA package.
It has the Intel NetBurst micro-architecture which features include hyper-pipelined technology, a rapid execution
engine, a 400MHz system, an execution trace cache, advanced dynamic execution, advanced transfer cache, enhanced
floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications
including 3-D graphics, video decoding/encoding, and speech recognition.
Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times
per bus clock.
Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and
frequency between two performance modes.
1.2.2 Clock Generator
The ICS950902 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style
chipsets with PC133 or DDR memory. The ICS950902 is part of a whole new line of ICS clock generators and buffers
called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust
features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the
output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the
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output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure
output frequency with resolution up to 0.1MHz increment.
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
•1 - Pair of differential CPU clocks @ 3.3V (CK408)/ 1 - Pair of differential open drain CPU clocks (K7)
•1 - Pair of differential push pull CPU_CS clocks @ 2.5V
•3 - AGP @ 3.3V
•7 - PCI @ 3.3V (1 - Free running)
•1 - 48MHz @ 3.3V fixed
•1 - 24_48MHz @ 3.3V (Default 48MHz I2C select only)
•2 - REF @ 3.3V, 14.318MHz
•12 - SDRAM (6 pair - DDR) selectable
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•Programmable output frequency.
•Programmable output divider ratios.
•Programmable output rise/fall time.
•Programmable output skew.
•Programmable spread percentage for EMI control.
•DDR output buffer supports up to 200MHz.
•Watchdog timer technology to reset system if system malfunctions.
•Programmable watch dog safe frequency.
•Support I2C Index read/write and block read/write operations.
•Uses external 14.318MHz crystal.
Features/Benefits:
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1.2.3 PN800 Mobile North Bridge
Defines Highly Integrated Solutions for Full Featured Value PC Mobile Designs
•High Performance UMA North Bridge: Integrated Pentium 4 North Bridge with 800 MHz FSB support and
UniChrome Pro 3D / 2D Graphics & Video Controllers in a single chip
•Advanced 64-bit memory controller supporting DDR400 / 333 / 266 SDRAM
•Combines with VIA VT8235-CE / VT8237 South Bridge for integrated 10/100 LAN, Audio, ATA133 IDE,
LPC, USB 2.0 and Serial ATA (VT8237)
•1.5V Core and Pentium 4 AGTL+ I/O
•37.5 x 37.5mm HSBGA (Ball Grid Array with Heat Spreader) package with 829 balls and 1mm ball pitch
•Pin compatible with PM800, PM880, PN880, PT800A and PT880 Pentium 4 North Bridges
High Performance CPU Interface
•Supports Intel 800 / 533 / 400 MHz FSB Pentium 4 and Pentium M processors
•Supports Intel Hyper-Threading Technology
•Supports DBI (Dynamic Bus Inversion) and Data, Address, Response Parity
•Twelve outstanding transactions (twelve level In-Order Queue (IOQ) )
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•AGP v3.0 compliant 8x / 4x transfer modes with Fast Write support
•1.5V AGP I/O interface
•Pipelined split-transaction long-burst transfers up to 2.1 GB/sec
•Supports Side Band Addressing (SBA) mode
•Supports Flush / Fence commands
•Supports DBI (Dynamic Bus Inversion)
•Asynchronous AGP and CPU interface
•Thirty-two level request queue for read and write
•One-hundred-twenty-eight level (quadwords) of read data FIFO
•Sixty-four level (quadwords) of write data FIFO
•Graphics Address Relocation Table (GART)
•One level TLB structure
•Built-in Phase Lock Loop circuitry for optimal skew control within and between clocking regions
Full Featured Accelerated Graphics Port (AGP) Controller
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•Sixteen entry fully associative page table
•LRU replacement scheme
•Supports DDR400 / 333 / 266 memory types with 2.5V SSTL-2 DRAM interface
•Supports mixed 64 / 128 / 256 / 512 / 1024Mb DDR SDRAMs in x8 and x16 configurations
•Supports CL 2 / 2.5 for DDR266 / 333 and CL 2.5 / 3 for DDR400
•Supports 4 unbuffered double-sided DIMMs and up to 8 GBytes of physical memory
•Two sets of memory data, address and control signals each of which drives up to 2 DIMMs
•Programmable timing / drive for memory address, data and control signals independently for each signal set
•DRAM interface pseudo-synchronous with host CPU for optimal memory performance
•Concurrent CPU, AGP / integrated graphics controller and V-Link access for minimum memory access
latency
•Bank interleave and up to 16-bank page interleave (i.e., 16 pages open simultaneously) based on LRU to
effectively reduce memory access latency
•Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks
Advanced High-Performance DDR400 SDRAM Controller
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while accessing the current bank)
•CPU Read-Around-Write capability for non-stalled operation
•Speculative DRAM read before snoop result to reduce PCI master memory read latency
•Supports Burst Read and Write operations with burst length of 4 or 8
•Twelve cache lines (96 quadwords) of integrated CPU-to-DRAM write buffers and twelve separate cache
lines of CPU-to-DRAM read prefetch buffers
•Optional dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0)
•Supports self-refresh and CAS-before-RAS DRAM refresh with staggered RAS timing
•Supports 66 MHz, 4x and 8x transfer modes, Ultra V-Link Host interface with 1 GB/sec total bandwidth
•Full duplex transfers with separate command / strobe for 4x and 8x modes
•Request / Data split transaction
•Transaction assurance for V-Link Host-to-Client access eliminates V-Link Host-Client Retry cycles
•Intelligent V-Link transaction protocol to eliminate data wait-states and throttle transfer latency to avoid data
overflow
High Bandwidth 1 GB / Sec 16-Bit “Ultra V-Link” Host Controller
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•Highly efficient V-Link arbitration with minimum overhead
•ACPI 2.0 and PCI Bus Power Management 1.1 compliant
•Supports Suspend-to-DRAM (STR) and DRAM self-refresh
•Supports dynamic Clock Enable (CKE) control for DRAM power reduction during normal system state (S0)
•Supports SMI, SMM, and STPCLK mechanisms
•Supports Enhanced Intel Speedstep™ Technology
•Low-leakage I/O pads
Advanced System Power Management Support
•Optimized Unified Memory Architecture (UMA)
•Supports 16 / 32 / 64 MB Frame Buffer sizes
•200 MHz Graphics Engine Clock
•Two independent 128-bit data paths between North Bridge and graphics core to improve video performance,
one for frame buffer access and one for texture / command access
Integrated Graphics with 2D / 3D / Video Controllers
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•PCI v2.2 compliant (for control and configuration)
•AGP v3.0 compliant (for control and data transfer)
•128-bit 2D graphics engine
•Hardware 2D rotation
•Supports ROP3, 256 operations
•Supports 8bpp, 15/16bpp and 32bpp color depth modes
•BitBLT (Bit BLock Transfer) functions including alpha BLTs
•True-color hardware cursor (64x64x32bpp) with 256-level blending effect
•Color expansion, source Color Key and destination Color Key
•Bresenham line drawing / style line function
•Transparency mode
•Window clipping
•Text function
2D Acceleration
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•3D Graphics Processor
– 128-bit 3D graphics engine
– Dual pixel rendering pipes
– Dual texture units
– Floating-point setup engine
– Internal full 32-bit ARGB format for high rendering quality
– 8K Texture Cache
•Capability
– Supports ROP2
– Supports various texture formats including 16/32bpp ARGB, 8bpp Palletized (ARGB), YUV 422/420 and
compressed texture (DXTC)
– Texture sizes up to 2048x2048
– Microsoft DirectX texture compression
– High quality texture filter for Nearest, Linear, Bi-linear, Tri-linear, and Anisotropic modes
– Flat and Gouraud shading
– Vertex Fog and Fog Table
– Z-Bias, LOD-Bias, Polygon offset, Edge Anti-aliasing and Alpha Blending
– Bump mapping and cubic mapping
3D Acceleration
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– Hardware back-face culling
– Specular lighting
•Performance
– Two textures per pass
– Triangle rate up to 4.5 million triangles per second
– Pixel rate up to 200 million pixels per second for 2 textures each
– Texel bilinear fill rate up to 400 million texels per second
– High quality dithering
•High Quality Video Processor
– RGB555, RGB565, RGB8888 and YUV422 video playback formats
– High quality 5-tap horizontal and 5-tap vertical scaler (up or down) for both horizontal and vertical scaling
(linear interpolation for horizontal and vertical p-scaling and filtering for horizontal and vertical down-
scaling)
– Independent graphics and video gamma tables
– 2 sets of Color and Chroma Key support
– Color enhancement for contrast, hue, saturation and brightness
– YUV-to-RGB color space conversion
– Display rotation in clockwise and counter-clockwise directions
Video Acceleration
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– Bob, Weave, Median-filter and Adaptive de-interlacing modes
– 3:2 / 2:2 pull-down detection
– De-blocking mode support
– Combining of many special effects such as filter, scaling up or down, sub-picture blending, de-interlacing
and deblocking to one pass process
– Tear-free double / triple buffer flipping
– Input video vertical blanking or line interrupt
– Video gamma correction
•Video Overlay
– Simultaneous graphics and TV video playback overlay
– Supports video window overlays
– Supports both YUV and RGB format Chroma Key
– Supports 16 operations for Color and Chroma Key
– Hardware sub-picture blending
•MPEG Video Playback
– MPEG-2 hardware VLD (Various Length Decode), iDCT, and motion compensation for full speed DVD
and MPEG-2 playback at full D1 resolution
– MPEG-4 ASP (Advanced Simple Profile) Level 5 with GMC (Global Motion Compensation) L0/L1 and ¼
pixel MC support for high video quality and performance
– High quality DVD and streaming video playback
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– DVD playback auto-flipping
– DVD sub-picture playback overlay
•Video Capture Capability
– 8-bit capture port following ITU-R BT656, VIP 1.1 and VIP 2.0 standards supporting 16 / 32-bit RGB and
YUV422 video capture formats
– Video capture and playback tear free auto flipping
– Multiplexed on Digital Video Port 0 (DVP0 selectable as Capture-In or TV-Out)
– External Hsync / Vsync support
•Built-in reference voltage generator and monitor sense circuits
•Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-
down
•External I/O signal controls enabling of graphics accelerator into standby / suspend-off state
•Dynamic clock gating for inactive functions to achieve maximum power savings
•I2C Serial Bus and DDC / E-DDC Monitor Communications for Plug-and-Play configuration
Advanced Graphics Power Management Support
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