
x
BFL (DS1)...................................................................................................2-4
CPU (DS2) ..................................................................................................2-4
PMC2 (DS3)................................................................................................2-4
PMC1 (DS4)................................................................................................2-4
10/100 BASET Port............................................................................................2-4
DEBUG Port.......................................................................................................2-5
PMC Slots...........................................................................................................2-7
PCI MEZZANINE CARD (PMC Slot 1)....................................................2-7
PCI MEZZANINE CARD (PMC Slot 2)....................................................2-7
PMCspan ...................................................................................................................2-8
CHAPTER 3 Functional Description
Introduction ...............................................................................................................3-1
Features......................................................................................................................3-1
General Description...................................................................................................3-4
Block Diagram...........................................................................................................3-4
MPC750 Processor.............................................................................................3-4
L2 Cache .....................................................................................................3-6
Hawk System Memory Controller (SMC)/PCI Host Bridge (PHB) ASIC........3-7
PCI Bus Latency .........................................................................................3-8
PPC Bus Latency.......................................................................................3-10
Assumptions..............................................................................................3-12
Clock Ratios and Operating Frequencies..................................................3-13
PPC60x Originated....................................................................................3-13
PCI Originated ..........................................................................................3-14
SDRAM Memory.............................................................................................3-14
SDRAM Latency.......................................................................................3-15
Flash Memory...................................................................................................3-19
ROM/Flash Performance ..........................................................................3-19
Ethernet Interface .............................................................................................3-22
PCI Mezzanine Card (PMC) Interface.............................................................3-23
PMC Slot 1 (Single-Width PMC) .............................................................3-23
PMC Slot 2 (Single-Width PMC) .............................................................3-24
PMC Slots 1 and 2 (Double-Width PMC) ................................................3-24
PCI Expansion...........................................................................................3-24
VMEbus Interface ............................................................................................3-25
Asynchronous Debug Port................................................................................3-25
PCI-ISA Bridge (PIB) Controller.....................................................................3-26
Real-Time Clock/NVRAM/Timer Function.....................................................3-27
PCI Host Bridge (PHB)....................................................................................3-27