Motorola 56F827 Instructions for use

© Motorola, Inc., 2003. All rights reserved.
56F827 Evaluation Module
Hardware User’s Manual
Order this document by
DSP56F827EVMUM/D
Re . 1, 07/22/2003
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MOTOROLA Table of Contents i
Pre ace
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
Notation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
efinitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Chapter 1
Introduction
1.1 56F827EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 56F827EVM Configuration Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 56F827EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1 56F827 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Program and ata Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 SPI EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 RS-232 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.7 ebug LE s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8 ebug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8.1 JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.9 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.12.1 Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.12.2 igital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Table o Contents
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ii 56F827 E aluation Module Hardware User’s Manual MOTOROLA
2.13 aughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.13.1 Memory aughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-15
2.13.2 Peripheral aughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-17
2.14 SCI Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.15 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Appendix A
56F827EVM Schematics
Appendix B
56F827EVM Bill o Material
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MOTOROLA List of Figures iii
1-1 Block iagram of the 56F827EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 56F827EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 Connecting the 56F827EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic iagram of the External Memory Interface . . . . . . . . . . . . . . 2-3
2-2 SPI EEPROM Memory Block iagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-3 Schematic iagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4 Schematic iagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5 Schematic iagram of the ebug LE Interface . . . . . . . . . . . . . . . . . . . 2-7
2-6 Block iagram of the Parallel JTAG Interface. . . . . . . . . . . . . . . . . . . . . 2-9
2-7 Schematic iagram of the User Interrupt Interface . . . . . . . . . . . . . . . . 2-11
2-8 Schematic iagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . 2-11
2-9 Schematic iagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-10 Codec Analog Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-11 CS4218 Stereo Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
List o Figures
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MOTOROLA List of Tables
1-1 56F827EVM efault Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 SPI Port Connector escription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2 RS-232 Serial Connector escription. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4 JTAG Connector escription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 Parallel JTAG Interface isable Jumper Selection. . . . . . . . . . . . . . . . . . 2-8
2-6 Parallel JTAG Interface Connector escription . . . . . . . . . . . . . . . . . . . . 2-9
2-7 Codec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-8 Memory aughter Card Connector escription. . . . . . . . . . . . . . . . . . . 2-16
2-9 Peripheral aughter Card Connector escription . . . . . . . . . . . . . . . . . 2-18
2-10 SCI Port #2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
List o Tables
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MOTOROLA Preface ii
Pre ace
This reference manual describes in detail the hardware on the 56F827 Evaluation Module.
Audience
This document is intended for application developers who are creating software for
devices using the Motorola 56F827 part.
Organization
This manual is organized into two chapters and two appendixes.
•Chapter 1, Introduction - provides an overview of the EVM and its features.
•Chapter 2, Technical Summary - describes in detail the 56F827 hardware.
•Appendix A, 56F827EVM Schematics contains the schematics of the
56F827EVM.
•Appendix B, 56F827EVM Bill of Material - provides a list of the materials used on the
56F827EVM board.
Suggested Reading
More documentation on the 56F827 and the 56F827EVM kit may be found at URL:
http://www.motorola.com/semiconductors
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iii 56F827 E aluation Module Hardware User’s Manual MOTOROLA
Notation Conventions
This manual uses the following notational conventions:
De initions, Acronyms, and Abbreviations
efinitions, acronyms and abbreviations for terms used in this document are defined
below for reference.
Term or Value Symbol Examples Exceptions
Acti e High Signals
(Logic One)
No special symbol
attached to the
signal name
A0
CLKO
Acti e Low Signals
(Logic Zero)
Noted with an
o erbar in text and
in most figures
WE
OE
In schematic drawings,
Acti e Low Signals may be
noted by a backslash:
/WE
Hexadecimal
Values
Begin with a “$”
symbol
$0FF0
$80
Decimal Values No special symbol
attached to the
number
10
34
Binary Values Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers Considered positi e
unless specifically
noted as a negati e
alue
5
-10
Voltage is often shown as
positi e: +3.3V
Blue Text Linkable on-line ...refer to
Figure 1-1
Bold Reference sources,
paths, emphasis
...see:
http://www.motorola.com/...
Codec COder/ ECoder; a part used to convert analog signals to digital (Coder)
and digital signals to analog ( ecoder)
EEPROM Electrically Erasable Programmable Read Only Memory
EVM Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop their application
GPIO General Purpose Input and Output Port; does not share pin functionality
with any other peripheral on the chip and can only be set as an input,
output or level-sensitive interrupt input
IC Integrated Circuit
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MOTOROLA Preface ix
Re erences
The following sources were referenced to produce this manual:
[1] DSP56800 Family Manual, SP56800FM/
[2] DSP56F826/827 Digital Signal Processor User’s Manual,
SP56F826_827UM/
[3] DSP56F827 Technical Data, SP56F827/
JTAG Joint Test Action Group; a bus protocol/interface used for test and debug
QFP Low-profile Quad Flat Pack
MPIO Multi-Purpose Input/Output Port; shares package pins with other
peripherals on the chip and can function as a GPIO
OnCETM On-Chip Emulation, a debug bus and port created by Motorola to enable
designers to create a low-cost hardware interface for a professional
quality debug environment
PCB Printed Circuit Board
P Phase Locked Loop
RAM Random Access Memory
ROM Read-Only Memory
SCI Serial Communications Interface Port
SPI Serial Peripheral Interface Port
SRAM Static Random Access Memory
SSI Synchronous Serial Interface Port
WS Wait State
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MOTOROLA Introduction 1-1
Chapter 1
Introduction
The 56F827EVM is used to demonstrate the abilities of the 56F827 and to provide a
hardware tool allowing the development of applications that use the 56F827.
The 56F827EVM is an evaluation module board that includes a 56F827 part, 16-bit stereo
codec, external memory and a daughter card expansion interface. The daughter card
expansion connectors are for signal monitoring and user feature expandability.
The 56F827EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800 architecture.
The tools and examples provided with the 56F827EVM facilitate evaluation of the
feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables
the user to develop and simulate routines, download the software to on-chip or
on-board RAM, run it, and debug it using a debugger via the JTAG/OnCETM port.
The breakpoint features of the OnCE port enable the user to easily specify complex
break conditions and to execute user-developed software at full-speed, until the
break conditions are satisfied. The ability to examine and modify all user
accessible registers, memory and peripherals through the OnCE port greatly
facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables
the user to connect external hardware peripherals. The on-board peripherals can be
disabled, providing the user with the ability to reassign any and all of the hybrid
controller's peripherals. The OnCE port's unobtrusive design means that all of the
memory on the board and on the hybrid controller chip are available to the user.
1.1 56F827EVM Architecture
The 56F827EVM facilitates the evaluation of various features present in the 56F827 part.
The 56F827EVM can be used to develop real-time software and hardware products based
on the 56F827. The 56F827EVM provides the features necessary for a user to write and
debug software, demonstrate the functionality of that software and interface with the
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1-2 56F827 E aluation Module Hardware User’s Manual MOTOROLA
customer's application-specific device(s). The 56F827EVM is flexible enough to allow a
user to fully exploit the 56F827's features to optimize the performance of his product, as
shown in Figure 1-1.
Figure 1-1. Block Diagram o the 56F827EVM
1.2 56F827EVM Con iguration Jumpers
Seven jumper groups, (JG1-JG7), shown in Figure 1-2, are used to configure various
features on the 56F827EVM board. Table 1-1 describes the default jumper group settings.
56F827
RESET
MODE
Address,
Data &
Control
JTAG/OnCE
XTAL/EXTAL
SPI
SCI
SSI
GPIO
& GND
Peripheral
Daughter Card
Connector
RESET
LOGIC
MODE
LOGIC
Program Memory
64Kx16-bit
SRAM
Memory
Daughter Card
Connector
JTAG
Connector
Parallel
JTAG
Interface
4.00MHz
Crystal
DSub
25-Pin
Data Memory
64Kx16-bit
SRAM
DSub
9-Pin
Debug LEDs
Stereo 16-bit
Codec
RS-232
Interface
SPI EEPROM
1M-bit
Power Supply
+2.5V, +3.3V & +5.0V
IRQ Interface
IRQ
Amp
Stereo Line Out
Headphone Jack
Stereo Line In
+2.5V, +3.3V
A/D
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56F827EVM Configuration Jumpers
MOTOROLA Introduction 1-3
Figure 1-2. 56F827EVM Jumper Re erence
Table 1-1. 56F827EVM De ault Jumper Options
Jumper
Group Comment Jumpers
Connections
JG1 Enable on-board Parallel JTAG Host/Target Interface NC
JG2 Enable RS-232 output NC
JG3 Enable on-board SRAM 1–2
JG4 Use on-board EXTAL crystal input for hybrid controller oscillator 2–3
JG5 Use on-board XTAL crystal input for hybrid controller oscillator 1–2
JG6 Selects hybrid controller’s Mode 0 operation upon exit from reset 1-2
JG7 Enable SPI EEPROM 1–2, 3–4, 5–6 & 7–8
JG6
DSP56F827EVM
J3
JTAG
U7
S/N
P1
Y1
U1
U2
S2
S3
S1
S4
P2
EDS
JG5
JG2
U5
RESET
IRQB
IRQA
1
2
7
8
JG3
J2
P6
1
JG5
3
JG2
JG3
JG1
JG6
TB1
P3
P4 P5
JG4
J1
JG7
HEADPHONE
INE
INE
IN OUT
JG1
JG4
3
1
JG7
J3
JTAG
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1-4 56F827 E aluation Module Hardware User’s Manual MOTOROLA
1.3 56F827EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V C power supply or external +5.0V C lab power supply to the 56F827EVM
board.
Perform the following steps to connect the 56F827EVM cables:
1. Connect the parallel extension cable to the parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P2, shown in Figure 1-3,
on the 56F827EVM board. This provides the connection which allows the host
computer to control the board.
3. Make sure that the external +12.0V C 1.2A switching power supply or the
external +5.0V C 1.0A lab power supply is not plugged into a 120V AC power
source.
4. Connect the 2.1mm output power plug from the external switching power supply
into P1, shown in Figure 1-3, on the 56F827EVM board. Optionally, attach an
external +5.0V C lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LE , LE 7, will
illuminate when power is correctly applied.
Figure 1-3. Connecting the 56F827EVM Cables
PC-compatible
Cable
Computer
Parallel Extension
56F827EVM
External
+12.0V
Power
P2
P1
Connect cable
to Parallel/Printer port
with 2.1mm,
receptacle
connector
+5.0V
Lab
Supply
TB1
or
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MOTOROLA Technical Summary 2-1
Chapter 2
Technical Summary
The 56F827EVM is designed as a versatile hybrid controller development card for
developing real-time software and hardware products to support a new generation of
applications in digital and wireless messaging, digital answering machines, feature
phones, modems, and digital cameras. The power of the 16-bit 56F827 hybrid controller,
combined with the on-board 64K ×16-bit external program static RAM (SRAM),
64K ×16-bit external data SRAM, RS-232 interface, stereo 16-bit codec interface,
aughter Card Expansion interface and parallel JTAG interface, makes the 56F827EVM
ideal for developing and implementing many audio and voice algorithms, as well as for
learning the architecture and instruction set of the 56F827 processor.
The main features of the 56F827EVM, with board and schematic reference designators
include:
• 56F827 16-bit +2.5V/+3.3V hybrid controller operating at 80MHz [U1]
• External fast static RAM (FSRAM) memory [U2], configured as:
—64K×16 bits of program memory with 0 wait states at 70MHz
—64K×16 bits of data memory with 0 wait states at 70MHz
• 1M-bit Serial EEPROM [U4]
• 4.00MHz crystal oscillator for hybrid controller frequency generation [Y1]
• Optional external oscillator frequency input connector [JG4 and JG5]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P2]
• RS-232 interface for easy connection to a host processor [U3 and P3]
• 16-bit stereo codec interface [U5, P4 and P5]
• Stereo headphone interface [U6 and P6]
• Codec sample rate selector [S4]
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2-2 56F827 E aluation Module Hardware User’s Manual MOTOROLA
• Peripheral aughter Card Expansion Connector, to allow the user to connect his
own SCI, SSI, SPI or GPIO-compatible peripheral to the hybrid controller[J2]
• Memory aughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the hybrid controller[J1]
• On-board power regulation from an external +12V C-supplied power input [P1]
• On-board power regulation from an optional +5V C-supplied power input [TB1]
• Light Emitting iode (LE ) power indicator [LE 7]
• Six on-board real-time user debugging LE s [LE 1-6]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3]
2.1 56F827
The 56F827EVM uses a Motorola SP56F827FG80 part, designated as U1 on the board
and in the schematics. This part will operate at a maximum speed of 80MHz. A full
description of the 56F827, including functionality and user information, is provided in
these documents:
•56F827 Technical Data, (56F827/ ): Provides features list and specifications
including signal descriptions, C power requirements, AC timing requirements
and available packaging.
•DSP56F826/827 6-Bit Digital Signal Processor User’s Manual,
( SP56F826_827UM/ ): Provides an overview description of the hybrid
controller and detailed information about the on-chip components including the
memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem.
• DSP56800 Family Manual, ( SP56800FM/ ): Provides a detailed description of
the core processor, including internal status and control registers and a detailed
description of the family instruction set.
Refer to these documents for detailed information about chip functionality and operation.
They can be found on this URL:
http://www.motorola.com/semiconductors
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Program and Data Memory
MOTOROLA Technical Summary 2-3
2.2 Program and Data Memory
The 56F827EVM uses one bank of 128K×16-bit Fast Static RAM (GSI GS72116, labelled
U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1.
This physical memory bank is split into two logical memory banks of 64Kx16-bits: one
for program memory and the other for data memory. By using the hybrid controller’s
program strobe, PS, signal line along with the memory chip’s A0 signal line, half of the
memory chip is selected when program memory accesses are requested and the other half
of the memory chip is selected when data memory access are requested. This memory
bank will operate with zero wait-state accesses while the 56F827 is running at 70MHz.
However, when running at 80MHz, the memory bank operates with four wait-state
accesses. This memory bank can be disabled by removing the jumper at JG3.
Figure 2-1. Schematic Diagram o the External Memory Inter ace
56F827 GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
DQ0-DQ15
OE
WE
CE
1 2
JG3
+3.3V
Jumper Pin 1-2:
Enable SRAM
Jumper Remo ed:
Disable SRAM
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2-4 56F827 E aluation Module Hardware User’s Manual MOTOROLA
2.3 SPI EEPROM Memory
A 1M-bit +3.3V SPI serial EEPROM Memory, Atmel AT45 B011-SC, is provided on
the 56F827EVM, reference Figure 2-2. This memory connects directly to the SPI Port
through a header on the 56F827. It can be used to load program code and data into the
56F827’s internal or external memory spaces. A jumper block is provided, JG7, to allow
the user to disconnect the on-board SPI EEPROM from the SPI port and allow him to
connect his own SPI port peripheral. The header details are shown in Table 2-1.
Figure 2-2. SPI EEPROM Memory Block Diagram
.Table 2-1. SPI Port Connector Description
JG7
Pin # Signal Pin # Signal
1 SS/GPIO7 2 CS
3MISO4 SDO
5MOSI6 SDI
7SCLK8 SCK
56F827
MOSI
MISO
SCLK
GPIOF7
Serial EEPROM
SDI
SDO
SCK
CS
EEPROM Enable
(SPI Port Connector)
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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