Motorola DSP56F826EVM Instructions for use

© Motorola, Inc., 2003. All rights reserved.
56F826 Evaluation Module
Hardware User’s Manual
Order this document by
DSP56F826EVMUM/D
Rev 1, 06/06/2003
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MOTOROLA Table of Contents iii
Prefa e
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Notation onventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Chapter 1
Introdu tion
1.1 56F826EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 56F826EVM onfiguration Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 56F826EVM onnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Te hni al Summary
2.1 56F826 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 SPI EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 RS-232 Serial ommunications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 lock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.7 Debug LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8.1 JTAG onnector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8.2 Parallel JTAG Interface onnector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.9 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.12 Stereo odec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.12.1 Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.12.2 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Table of Contents
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iv 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
2.13 Daughter ard onnectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.13.1 Memory Daughter ard Expansion onnector . . . . . . . . . . . . . . . . . . . . . . 2-16
2.13.2 Peripheral Daughter ard Expansion onnector . . . . . . . . . . . . . . . . . . . . . 2-17
2.14 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Appendix A
56F826EVM S hemati s
Appendix B
56F826EVM Bill of Material
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MOTOROLA List of Figures v
1-1 Block Diagram of the 56F826EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 56F826EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 onnecting the 56F826EVM ables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic Diagram of the External Memory Interface . . . . . . . . . . . . . . 2-3
2-2 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-3 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4 Schematic Diagram of the lock Interface . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . 2-7
2-6 Block Diagram of the Parallel JTAG Interface. . . . . . . . . . . . . . . . . . . . . 2-9
2-7 Schematic Diagram of the User Interrupt Interface . . . . . . . . . . . . . . . . 2-10
2-8 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . 2-11
2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-10 odec Analog onnections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11 S4218 Stereo Audio odec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
A-1 56F826 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A-2 RESET, MODE, LO K & IRQS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A-3 PROGRAM & DATA SRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . A-4
A-4 SPI Serial 1M-bit Serial EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . A-5
A-5 S I PORT, RS-232 and onnector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A-6 SSI 16-bit Stereo odec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
A-7 Parallel JTAG Host Target Interface and JTAG onnector . . . . . . . . . . . A-8
A-8 Daughter ard Expansion onnectors . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A-9 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A-10 Bypass aps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
List of Figures
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MOTOROLA List of Tables vii
1-1 56F826EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 SPI Port onnector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2 RS-232 Serial onnector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4 JTAG onnector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 Parallel JTAG Interface Disable Jumper Selection. . . . . . . . . . . . . . . . . . 2-8
2-6 Parallel JTAG Interface onnector Description . . . . . . . . . . . . . . . . . . . . 2-9
2-7 odec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-8 Memory Daughter ard onnector Description. . . . . . . . . . . . . . . . . . . 2-16
2-9 Peripheral Daughter ard onnector Description . . . . . . . . . . . . . . . . . 2-17
List of Tables
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MOTOROLA Preface ix
Prefa e
This reference manual describes in detail the hardware on the 56F826 Evaluation Module.
Audien e
This document is intended for application developers who are creating software for
devices using the Motorola 56F826 part.
Organization
This manual is organized into two chapters and two appendixes.
•Chapter 1, Introduction - provides an overview of the 56F826EVM and its features.
•Chapter 2, Technical Summary - describes the 56F826EVM hardware in detail.
•Appendix A, 56F826E M Schematics - contains the schematics of the
56F826EVM.
•Appendix B, 56F826E M Bill of Material - provides a list of the materials used on the
56F826EVM board.
Suggested Reading
More documentation on the 56F826 and the 56F826EVM kit may be found at URL:
http://www.motorola.com/semiconductors
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x 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
Notation Conventions
This manual uses the following notational conventions:
Definitions, A ronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference
Term or Value Symbol Examples Ex eptions
Active High Signals
(Logic One)
No special symbol
attached to the
signal name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and
in most figures
WE
OE
In schematic drawings,
Active Low Signals may be
noted by a backslash:
/WE
Hexadecimal
Values
Begin with a “$”
symbol
$0FF0
$80
Decimal Values No special symbol
attached to the
number
10
34
Binary Values Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers Considered positive
unless specifically
noted as a negative
value
5
-10
Voltage is often shown as
positive: +3 3V
Blue Text Linkable on-line refer to
Figure 1-1
Bold Reference sources,
paths, emphasis
see:
http://www.motorola. om/
codec Oder/DE oder, a part used to convert analog signals to digital ( oder)
and digital signals to analog (Decoder)
EEPROM Electrically Erasable Programmable Read-Only Memory
E M Evaluation Module, a hardware platform which allows a customer to
evaluate the silicon and develop their application
GPIO General Purpose Input and Output Port; does not share pin functionality
with any other peripheral on the chip and can only be set as an input,
output or level-sensitive interrupt input
IC Integrated ircuit
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