Motorola DSP56F826EVM Instructions for use

© Motorola, Inc., 2003. All rights reserved.
56F826 Evaluation Module
Hardware User’s Manual
Order this document by
DSP56F826EVMUM/D
Rev 1, 06/06/2003
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MOTOROLA Table of Contents iii
Prefa e
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Notation onventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Chapter 1
Introdu tion
1.1 56F826EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 56F826EVM onfiguration Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 56F826EVM onnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Te hni al Summary
2.1 56F826 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 SPI EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4 RS-232 Serial ommunications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.5 lock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.6 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.7 Debug LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.8.1 JTAG onnector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.8.2 Parallel JTAG Interface onnector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.9 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.12 Stereo odec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.12.1 Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.12.2 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Table of Contents
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iv 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
2.13 Daughter ard onnectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.13.1 Memory Daughter ard Expansion onnector . . . . . . . . . . . . . . . . . . . . . . 2-16
2.13.2 Peripheral Daughter ard Expansion onnector . . . . . . . . . . . . . . . . . . . . . 2-17
2.14 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Appendix A
56F826EVM S hemati s
Appendix B
56F826EVM Bill of Material
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MOTOROLA List of Figures v
1-1 Block Diagram of the 56F826EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-2 56F826EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-3 onnecting the 56F826EVM ables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2-1 Schematic Diagram of the External Memory Interface . . . . . . . . . . . . . . 2-3
2-2 SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-3 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . 2-5
2-4 Schematic Diagram of the lock Interface . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-5 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . 2-7
2-6 Block Diagram of the Parallel JTAG Interface. . . . . . . . . . . . . . . . . . . . . 2-9
2-7 Schematic Diagram of the User Interrupt Interface . . . . . . . . . . . . . . . . 2-10
2-8 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . 2-11
2-9 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2-10 odec Analog onnections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2-11 S4218 Stereo Audio odec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
A-1 56F826 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A-2 RESET, MODE, LO K & IRQS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A-3 PROGRAM & DATA SRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . A-4
A-4 SPI Serial 1M-bit Serial EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . A-5
A-5 S I PORT, RS-232 and onnector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A-6 SSI 16-bit Stereo odec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
A-7 Parallel JTAG Host Target Interface and JTAG onnector . . . . . . . . . . . A-8
A-8 Daughter ard Expansion onnectors . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A-9 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10
A-10 Bypass aps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
List of Figures
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MOTOROLA List of Tables vii
1-1 56F826EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
2-1 SPI Port onnector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2 RS-232 Serial onnector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-3 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2-4 JTAG onnector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2-5 Parallel JTAG Interface Disable Jumper Selection. . . . . . . . . . . . . . . . . . 2-8
2-6 Parallel JTAG Interface onnector Description . . . . . . . . . . . . . . . . . . . . 2-9
2-7 odec Sample Rate Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2-8 Memory Daughter ard onnector Description. . . . . . . . . . . . . . . . . . . 2-16
2-9 Peripheral Daughter ard onnector Description . . . . . . . . . . . . . . . . . 2-17
List of Tables
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viii 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
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MOTOROLA Preface ix
Prefa e
This reference manual describes in detail the hardware on the 56F826 Evaluation Module.
Audien e
This document is intended for application developers who are creating software for
devices using the Motorola 56F826 part.
Organization
This manual is organized into two chapters and two appendixes.
•Chapter 1, Introduction - provides an overview of the 56F826EVM and its features.
•Chapter 2, Technical Summary - describes the 56F826EVM hardware in detail.
•Appendix A, 56F826E M Schematics - contains the schematics of the
56F826EVM.
•Appendix B, 56F826E M Bill of Material - provides a list of the materials used on the
56F826EVM board.
Suggested Reading
More documentation on the 56F826 and the 56F826EVM kit may be found at URL:
http://www.motorola.com/semiconductors
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x 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
Notation Conventions
This manual uses the following notational conventions:
Definitions, A ronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference
Term or Value Symbol Examples Ex eptions
Active High Signals
(Logic One)
No special symbol
attached to the
signal name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and
in most figures
WE
OE
In schematic drawings,
Active Low Signals may be
noted by a backslash:
/WE
Hexadecimal
Values
Begin with a “$”
symbol
$0FF0
$80
Decimal Values No special symbol
attached to the
number
10
34
Binary Values Begin with the letter
“b” attached to the
number
b1010
b0011
Numbers Considered positive
unless specifically
noted as a negative
value
5
-10
Voltage is often shown as
positive: +3 3V
Blue Text Linkable on-line refer to
Figure 1-1
Bold Reference sources,
paths, emphasis
see:
http://www.motorola. om/
codec Oder/DE oder, a part used to convert analog signals to digital ( oder)
and digital signals to analog (Decoder)
EEPROM Electrically Erasable Programmable Read-Only Memory
E M Evaluation Module, a hardware platform which allows a customer to
evaluate the silicon and develop their application
GPIO General Purpose Input and Output Port; does not share pin functionality
with any other peripheral on the chip and can only be set as an input,
output or level-sensitive interrupt input
IC Integrated ircuit
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MOTOROLA Preface xi
Referen es
The following sources were used to produce this manual:
[1] DSP56800 Family Manual, Motorola, DSP56800FM/D
[2] 56F826/827 User’s Manual, Motorola, DSP56F826-827UM/D
[3] 56F826 Technical Data, Motorola, DSP56F826/D
JTAG Joint Test Action Group, a bus protocol/interface used for test and debug
LQFP Low-profile Quad Flat Pack
MPIO Multi-Purpose Input and Output Port; shares package pins with other
peripherals on the chip and can function as a GPIO
OnCETM On- hip Emulation, a debug bus and port created by Motorola to enable
designers to create a low-cost hardware interface for a
professional-quality debug environment
PCB Printed ircuit Board
PLL Phase Locked Loop
RAM Random Access Memory
ROM Read-Only Memory
SCI Serial ommunications Interface Port
SPI Serial Peripheral Interface Port
SRAM Static Random Access Memory
SSI Synchronous Serial Interface Port
WS Wait State
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xii 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
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MOTOROLA Introduction 1-1
Chapter 1
Introdu tion
The 56F826EVM is used to demonstrate the abilities of the 56F826 and to provide a
hardware tool allowing the development of applications that use the 56F826.
The 56F826EVM is an evaluation module board that includes a 56F826 part, 16-bit stereo
codec, external memory and a daughter card expansion interface. The daughter card
expansion connectors are for signal monitoring and user feature expandability.
The 56F826EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800 architecture.
The tools and examples provided with the 56F826EVM facilitate evaluation of the
feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables
the user to develop and simulate routines, download the software to on-chip or
on-board RAM, run it, and debug it using a debugger via the JTAG/On ETM port.
The breakpoint features of the On E port enable the user to easily specify complex
break conditions and to execute user-developed software at full-speed, until the
break conditions are satisfied. The ability to examine and modify all user
accessible registers, memory and peripherals through the On E port greatly
facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables
the user to connect external hardware peripherals. The on-board peripherals can be
disabled, allowing the user to reassign any and all of the hybrid controller's
peripherals. The On E port's unobtrusive design means that all of the memory on
the board and on the chip are available to the user.
1.1 56F826EVM Ar hite ture
The 56F826EVM facilitates the evaluation of various features present in the 56F826 part.
The 56F826EVM can be used to develop real-time software and hardware products based
on the 56F826. The 56F826EVM provides the features necessary for a user to write and
debug software, demonstrate the functionality of that software and interface with the
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1-2 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
customer's application-specific device(s). The 56F826EVM is flexible enough to allow a
user to fully exploit the 56F826's features to optimize the performance of his product, as
shown in Figure 1-1.
Figure 1-1. Blo k Diagram of the 56F826EVM
1.2 56F826EVM Configuration Jumpers
Seven jumper groups, (JG1-JG7), shown in Figure 1-2, are used to configure various
features on the 56F826EVM board. Table 1-1 describes the default jumper group settings.
56F826
RESET
MODE
Address,
Data &
Control
JTAG/OnCE
XTAL/EXTAL
SPI
SCI
SSI
GPIO
+2 5V, +3 3V
& GND
Peripheral
Daughter Card
Connector
RESET
LOGIC
MODE
LOGIC
Program Memory
64Kx16-bit
SRAM
Memory
Daughter Card
Connector
JTAG
Connector
Parallel
JTAG
Interface
4 00MHz
Crystal
DSub
25-Pin
Data Memory
64Kx16-bit
SRAM
DSub
9-Pin
Debug LEDs
Stereo 16-bit
Codec
RS-232
Interface
SPI EEPROM
1M-bit
Power Supply
+2 5V, +3 3V & +5 0V
IRQ Interface
IRQ
Amp
Stereo Line Out
Headphone Jack
Stereo Line In
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56F826EVM Configuration Jumpers
MOTOROLA Introduction 1-3
Figure 1-2. 56F826EVM Jumper Referen e
Table 1-1. 56F826EVM Default Jumper Options
Jumper
Group Comment Jumpers
Conne tions
JG1 Enable on-board Parallel JTAG Host/Target Interface NC
JG2 Enable RS-232 output NC
JG3 Enable on-board SRAM 1–2
JG4 Use on-board EXTAL crystal input for oscillator 2–3
JG5 Use on-board XTAL crystal input for oscillator 1–2
JG6 Selects device’s Mode 0 operation upon exit from reset 1-2
JG7 Enable SPI EEPROM 1–2, 3–4, 5–6 & 7–8
JG6
DSP56F826E M
J3
JTAG
U7
S/N
P1
Y1
U1
U2
S2
S3
S1
S4
P2
LEDS
JG5
JG2
U5
RESET
IRQB
IRQA
1
2
7
8
JG3
J2
P6
1
JG5
3
JG2
JG3
JG1
JG6
TB1
P3
P4 P5
JG4
J1
JG7
HEADPHONE
LINE
LINE
IN OUT
JG1
JG4
31
JG7
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1-4 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
1.3 56F826EVM Conne tions
An interconnection diagram is shown in Figure 1-3 for connecting the P and the external
+12.0V D power supply or external +5.0V D lab power supply to the 56F826EVM
board.
Perform the following steps to connect the 56F826EVM cables:
1. onnect the parallel extension cable to the parallel port of the host computer
2. onnect the other end of the parallel extension cable to P1 on the 56F826EVM
board as shown in Figure 1-3. This provides the connection which allows the host
computer to control the board.
3. Make sure that the external +12.0V D , 2.1A switching power supply or the
external +5.0V D , 1A lab power supply is not plugged into a +120V A power
source
4. onnect the 2.1mm output power plug from the external switching power supply
into P2 on the 56F826EVM board, as shown in Figure 1-3. Optionally, attach an
external +5.0V D lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is applied correctly.
Figure 1-3. Conne ting the 56F826EVM Cables
PC-compatible
Cable
Computer
Parallel Extension
56F826EVM
External
+12 0V
Power
P1
P2
Connect cable
to Parallel/Printer port
with 2 1mm,
receptacle
connector
+5 0V
Lab
Supply
TB1
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MOTOROLA Technical Summary 2-1
Chapter 2
Te hni al Summary
The 56F826EVM is designed as a versatile hybrid controller development card for
developing real-time software and hardware products to support a new generation of
applications in digital and wireless messaging, digital answering machines, feature
phones, modems, and digital cameras. The power of the 16-bit 56F826 device, combined
with the on-board 64K ×16-bit external program static RAM (SRAM), 64K ×16-bit
external data SRAM, RS-232 interface, stereo 16-bit codec interface, Daughter ard
Expansion interface and parallel JTAG interface, makes the 56F826EVM ideal for
developing and implementing many audio and voice algorithms, as well as for learning the
architecture and instruction set of the 56F826 processor.
The main features of the 56F826EVM, with board and schematic reference designators,
include:
• 56F826EVM 16-bit +2.5V/+3.3V hybrid controller operating at 80MHz [U1]
• External fast static RAM (FSRAM) memory [U2], configured as:
—64K×16 bits of Program memory with 0 wait states at 70MHz
—64K×16 bits of Data memory with 0 wait states at 70MHz
• 1Mbit Serial EEPROM [U4]
• 4.00MHz crystal oscillator for device frequency generation [Y1]
• Optional external oscillator frequency input connector [JG4 and JG5]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a P printer
port cable [P2]
• RS-232 interface for easy connection to a host processor [U3 and P3]
• 16-bit stereo codec interface [U5, P4 and P5]
• Stereo headphone interface [U6 and P6]
• odec sample rate selector [S4]
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2-2 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
• Peripheral Daughter ard Expansion onnector, to allow the user to connect his
own S I, SSI, SPI or GPIO-compatible peripheral to the hybrid controller[J2]
• Memory Daughter ard Expansion onnector, to allow the user to connect his own
memory or memory device to the hybrid controller[J1]
• On-board power regulation from an external +12V D -supplied power input [P1]
• On-board power regulation from an optional +5V D -supplied power input [TB1]
• Light Emitting Diode (LED) power indicator [LED7]
• Six on-board real-time user debugging LEDs [LED1-6]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3]
2.1 56F826
The 56F826EVM uses a Motorola DSP56F826BU80 part, designated as U1 on the board
and in the schematics. This part will operate at a maximum speed of 80MHz. A full
description of the 56F826, including functionality and user information, is provided in
these documents:
•56F826 Preliminary Technical Data Sheet, (DSP56F826-827 UM/D): Provides
features list and specifications including signal descriptions, D power
requirements, A timing requirements and available packaging.
•56F826/827 16- it Digital Signal Processor User’s Manual, (56F826UM/AD):
Provides an overview description of the and detailed information about the on-chip
components including the memory and I/O maps, peripheral functionality, and
control/status register descriptions for each subsystem.
• DSP56F800Family Manual, (DSP56F800FM/D): Provides a detailed description
of the core processor, including internal status and control registers and a detailed
description of the family instruction set.
Refer to these documents for detailed information about chip functionality and operation.
They can be found on this URL:
http://www.motorola.com/semiconductors
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Program and Data Memory
MOTOROLA Technical Summary 2-3
2.2 Program and Data Memory
The 56F826EVM uses one bank of 128K×16-bit Fast Static RAM (GSI GS72116, labeled
U2) for external memory expansion; see the FSRAM schematic diagram in Figure 2-1.
This physical memory bank is split into two logical memory banks of 64Kx16-bits: one
for program memory and the other for data memory. By using the hybrid controller’s
program strobe, PS, signal line along with the memory chip’s A0 signal line, half of the
memory chip is selected when program memory accesses are requested and the other half
of the memory chip is selected when data memory access are requested. This memory
bank will operate with zero wait state accesses while the 56F826 is running at 70MHz.
However, when running at 80MHz, the memory bank operates with four wait state
accesses. This memory bank can be disabled by removing the jumper at JG3.
Figure 2-1. S hemati Diagram of the External Memory Interfa e
56F826 GS72116
A0-A15
PS
D0-D15
RD
WR
A1-A16
A0
DQ0-DQ15
OE
WE
CE
1 2
JG3
+3 3V
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
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2-4 56F826 Evaluation Module Hardware User’s Manual MOTOROLA
2.3 SPI EEPROM Memory
A 1Mbit, +3.3V, SPI, serial EEPROM Memory, Atmel AT45DB011-S , is provided on
the 56F826EVM; reference Figure 2-2. This memory connects directly to the SPI Port
through a header on the 56F826. It can be used to load program code and data into the
56F826’s internal or external memory spaces. A jumper block, JG7, is provided, which
allows the user to disconnect the on-board SPI EEPROM from the SPI port and to connect
his own SPI port peripheral. The header details are shown in Table 2-1.
Figure 2-2. SPI EEPROM Memory Blo k Diagram
.Table 2-1. SPI Port Conne tor Des ription
JG7
Pin # Signal Pin # Signal
1 SS/GPIO7 2 CS
3MISO4 SDO
5MOSI6 SDI
7SCLK8 SCK
56F826
MOSI
MISO
SCLK
GPIOF7
Serial EEPROM
SDI
SDO
SCK
CS
EEPROM Enable
(SPI Port Connector)
JG7
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