MYiR MYC-YT507H User manual

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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MYC-YT507H
Product Manual
File State：
[ ] Draft
[ √ ] Release
FILE ID：
MYIR-MYC-YT507H-HW-PM-EN
Version：
V1.0
Author：
Dana
Created：
2022-04-13
Updated：
2022-04-13
Copyright © MYIR Electronics Limited 2020-2030 all rights reserved.

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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History
Version
Author
Participants
Date
Description
V1.0
Dana
20220413
Initial Version

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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Contents
History.......................................................................................................................................- 2 -
Contents...................................................................................................................................- 3 -
1. Overview ............................................................................................................................................................ - 5 -
2. Product Presentation.....................................................................................................................................- 8 -
2.1. Chip Resources..............................................................................................................- 8 -
2.2. Core Board Features................................................................................................. - 11 -
2.3. Block Diagram............................................................................................................. - 12 -
2.4. Core Board Ordering Information....................................................................... - 13 -
3. Pin Description .............................................................................................................................................. - 15 -
3.1. Pin Out........................................................................................................................... - 15 -
3.2. Pin List............................................................................................................................ - 17 -
4. Electrical Characteristics .............................................................................................................................- 23 -
4.1. System Power.............................................................................................................. - 23 -
4.2. Power Consumption................................................................................................. - 24 -
4.3. GPIO DC Parameters .................................................................................................- 24 -
5. System Start-up Configuration ............................................................................................................... - 25 -
5.1. Boot Mode....................................................................................................................- 25 -
5.2. Special Function Pin..................................................................................................- 25 -
6. Interfaces .........................................................................................................................................................- 26 -
6.1. SMHC..............................................................................................................................- 26 -
6.1.1. Pin Description.................................................................................................- 26 -
6.2. UART............................................................................................................................... - 27 -
6.2.1. Pin Description.................................................................................................- 27 -
6.3. USB.................................................................................................................................. - 28 -
6.3.1. Pin Description.................................................................................................- 28 -
6.4. Ethernet......................................................................................................................... - 29 -
6.4.1. Pin Description.................................................................................................- 29 -
6.5. MIPI CSI..........................................................................................................................- 30 -
6.5.1. Pin Description.................................................................................................- 30 -

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6.6. Parallel CSI.................................................................................................................... - 31 -
6.6.1. Pin Description.................................................................................................- 31 -
6.7. LVDS................................................................................................................................- 32 -
6.7.1. Pin Description.................................................................................................- 32 -
6.8. HDMI...............................................................................................................................- 33 -
6.8.1. Pin Description.................................................................................................- 33 -
6.9. TV CVBS Output ..........................................................................................................- 33 -
6.9.1. Pin Description.................................................................................................- 33 -
6.10. SPDIF-OUT..................................................................................................................- 34 -
6.10.1. Pin Description...............................................................................................- 34 -
6.11. I2S..................................................................................................................................- 34 -
6.11.1. Pin Description...............................................................................................- 34 -
6.12. Line Out.......................................................................................................................- 34 -
6.12.1. Pin Description...............................................................................................- 34 -
6.13. GPIO ..............................................................................................................................- 35 -
6.13.1. Pin Description...............................................................................................- 35 -
6.14. ADC...............................................................................................................................- 36 -
6.14.1. Pin Description...............................................................................................- 36 -
7. Package Information ...................................................................................................................................- 37 -
7.1. Package Dimensions.................................................................................................- 37 -
7.2. Carrier Board PCB Requirements......................................................................... - 38 -
7.3. carrier board PCB requirement.............................................................................- 39 -
Appendix A ..........................................................................................................................................................- 40 -
Warranty & Technical Support Services.................................................................... - 40 -

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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1. Overview
Allwinner T5 series is a high-performance quad-core CortexTM-A53 processor, suitable for the
new generation of automotive market. T5 series meet the test requirements of automobile AEC -
Q100. The chip integrates quad-core CortexTM-A53 CPU, G31 MP2 GPU, 32-bit DDR3 /
LPDDR3 / DDR4 / LRDDR4 dynamic random access memory. Multi-channel video output
interface (RGB / 2*LVDS / HDMI / CVBS OUT), multi-channel video input interface (MIPI CSI/
BT656/BT1120). The chip supports 4K@60fps H.265 decoding, 4K@60fps VP9 decoding,
4K@60fps AVS2 decoding, 4K@25fps H.264 encoding, 3D noise reduction as well as automatic
color matching system and trapezoidal correction module to provide a smooth user experience and
professional visual effects.
MYC-YT507H core board is based on T507-H processor, has a good software development
environment, kernel support open source operating system Linux. MYC-YT507H also has rich
interface resources. You may download the above materials at any time at the following address:
http://d.myirtech.com//MYD-YT507H/
MYC-YT507H core board is based on T507-H processor, has a good software development
environment, kernel support open source operating system Linux. MYC-YT507H also has rich
interface resources. You may download the above materials at any time at the following address:
http://www.myir-tech.com/product

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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Figure 1-1 MYC-YT507H Core board
Figure 1-2 MYD-YT507H Kit Top side

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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Figure 1-3 MYD-YT507H Kit Bottom side

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2. Product Presentation
MYC-YT507H core board adopts SMD encapsulation form patch (stamp hole + back pad). There
are 4 standard models. They have some differences in storage configuration, temperature and
other aspects, customers can choose the appropriate model according to their needs. For the
differences between product models, see 2.4.
2.1. Chip Resources
Figure 2-1 T507-H Resource diagram
Resource
Parameter Description
CPU
Quad-core ARM CortexTM[email protected]
GPU
G31 MP2
Supports OpenGL ES 3.2/2.0/1.0,Vulkan 1.1, OpenCL 2.0
External s
torage
32-bit DDR4/DDR3/DDR3L/LPDDR3/LPDDR4 interface, supporting
maximum capacity of 4GB
SD3.0/eMMC5.0 interface

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8-bit Nand flash interface with maximum 80-bit/1KB ECC
Video
engine
Video decoder
H.265 MP decoder up to 4K@60fps
H.264 BL/MP/HP decoder up to 4K@30fps
VP9 decoder up to 4K@60fps
AVS2 decoder up to 4K@60fps
Multi-format 1080p@60fps video playback, including VP8,
MPEG1/2 SP/MP,MPEG4 SP/ASP,
AVS+/AVS JIZHUN, VC1 SP/MP
Video encoder
H.264 encoder up to 4K@25fps
MJPEG encoder up to 4K@15fps
JPEG encoder up to 8K x 8K resolution
Video
input
Supports one 8-/10-/12-/16-bit digital camera(DC) interface
Maximum pixel clock of 148.5MHz for each DC interface
BT656,BT1120 video input for multichannel YUV
Four-lane MIPI CSI, up to l Gbps per lane in HS transmission,comp
liant with MIPI-CSI2 V1.00 and MIPI DPHY V1.00
Maximum video capture resolution of 8M@30fps or 4x 1080p@25fps
for MIPI CSI
Supports formats:YUV422,YUV420,RAW-8,RAW-10,RAW-12
Audio
Two DAC channels
Supports 1 audio output interface
(differential LINEOUTP/N or single-end LINEOUTL/LINEOUTR)
One Audio HUB, supporting internal mixing function
Embedded 3 I2S/PCM for connecting the external devices
(I2S0 for extended audio codec, I2S2 for BT, I2S3 for digital power
amplifier)
Supports Left-justified, Right-justified, Standard I2S mode,
PCM mode, and TDM mode
I2S mode supports 8 channels, and 32-bit/192kbit sample rate
I2S and TDM-modes support maximum 16 channels, and 32-bit/96kb
it sample rate
One OWA OUT interface, supporting 16-/20-/24-bit outputs
Integrated digital microphone, supporting maximum 8 digital PDM m
icrophones
Display
output
HDMI 2.0a up to 4K@60fps
TV CVBS output, supporting PAL/NTSC
LVDS interface with dual link, up to 1080p@60fps
RGB interface with DE/SYNC mode, up to 1080p@60fps
Security e
ngine
Supports Full Disk Encryption
AES, DES, 3DES, and XTS encryption and decryption algorithms
MD5, SHA, and HMAC tamper proofing

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RSA, ECC signature and verification algorithms
Supports 160-bit hardware pseudo random number generator(PRNG)
with 175-bit seed
Supports 256-bit hardware true random number generator(TRNG)
Integrated 2K-bit EFUSE for chip ID and security application
connectio
n
3 x USB2.0 Host, l x USB2.0 OTG
2 x Ethernet MAC (one 10/100 Mbps Ethernet port with RMII interf
ace, one 10/100/1000 Mbps
Ethernet port with RGMII and RMII interfaces)
SDIO 3.0, TSC, SCR, CIR Receiver
6 x TWI, 2 x SPI, 6 x UART
6-ch PWM, 4-ch GPADC. 1-ch LRADC
PMIC
Allwinner Power Management IC
encapsula
tion
TFBGA 421balls
15 mm x 15 mm size,0.65 mm ball pitch,0.35 mm ball size
Process
technology
28nm HPC
Table 2-1 T507-H resource
Refer to the chip manual for details.

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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2.2. Core Board Features
Item
features
CPU series
T5 Series
CPU model
T507-H
Processor CPU
x4 ARM CortexTM-A53
DDR storage
LPDDR4 1GB/2GB
eMMC
EMMC 8GB (Other capacity optional)
Core board size
43 x 45 x 3.5 mm (With shielded skeleton)
interface type
SMD patch，Stamp hole+LGA
PCB board specifications
10-layer board design, gold immersion process
operating system
Linux 4.9
Table 2-2 Core board features

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2.3. Block Diagram
Figure 2-2 Core board block diagram

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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2.4. Core Board Ordering Information
MYC-YT507H core board have 4 models according to the different parameters of core board
storage device and operating temperature. Please select the model most suitable for you from the
following list.
Table 2-3 MYC-YT507H core board ordering information 1
Part No.
Item
MYC-YT507H-8E1D-150-I
MYC-YT507H-8E1D-150-C
CPU
T507-H
T507-H
CPU series
T5 Series
T5 Series
Core
x4 CortexTM-A53
x4 CortexTM-A53
Frequency
1.5Ghz
1.5Ghz
System
Linux 4.9
Linux 4.9
DDR
1GB LPDDR4
1GB LPDDR4
eMMC
8GB eMMC
8GB eMMC
Video input
1 DVP camera input
1 MIPI CSI input
1 DVP camera input
1 MIPI CSI input
Display output
1 HDMI 2.0a，support 4K@60fps
1 TV CVBS output, support PAL/NTSC
2 LVDS / 1 HD LVDS / RGB888, up to
support 1080p@60fps
1 HDMI 2.0a，support 4K@60fps
1 TV CVBS output, support PAL/NTSC
2 LVDS / 1 HD LVDS / RGB888, up to su
pport 1080p@60fps
Touch screen
Support Capacitive touch
Support 4-wire resistive screen
(touch chip is required)
Support Capacitive touch
Support 4-wire resistive screen
(touch chip is required)
UART
6 way (Max)
6 way (Max)
CAN
NO
NO
USB2.0
3 USB Host +1 USB OTG
3 USB Host +1 USB OTG
Ethernet
1 RGMII +1 RMII
1 RGMII +1 RMII
I2C
6 (Max)
6 (Max)
SPI
2 (Max)
2 (Max)
GPIO
138
138
ADC
5
5
Power Supply
+5V
+5V
Mechanical size
43 x 45 x 3.5 mm
43 x 45 x 3.5 mm
Operating temp
erature
-40℃ - +85℃
0℃ - +70℃
Connector
Stamp hole+LGA （222 PIN）
Stamp hole+LGA （222 PIN）
Certification
CE
ROHS
CE
ROHS

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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Table 2-4 MYC-YT507H core board ordering information 2
Part No.
Item
MYC-YT507H-8E2D-150-I
MYC-YT507H-8E2D-150-C
CPU
T507-H
T507-H
CPU series
T5 Series
T5 Series
Core
x4 CortexTM-A53
x4 CortexTM-A53
Frequency
1.5Ghz
1.5Ghz
System
Linux 4.9
Linux 4.9
DDR
2GB LPDDR4
2GB LPDDR4
eMMC
8GB eMMC
8GB eMMC
Video input
1 DVP camera input
1 MIPI CSI input
1 DVP camera input
1 MIPI CSI input
Display output
1 HDMI 2.0a，support 4K@60fps
1 TV CVBS output, support PAL/NTSC
2 LVDS / 1 HD LVDS / RGB888, up to su
pport 1080p@60fps
1 HDMI 2.0a，support 4K@60fps
1 TV CVBS output, support PAL/NTSC
2 LVDS / 1 HD LVDS / RGB888, up to su
pport 1080p@60fps
Touch screen
Support Capacitive touch
Support 4-wire resistive screen
(touch chip is required)
Support Capacitive touch
Support 4-wire resistive screen
(touch chip is required)
UART
6 way (Max)
6 way (Max)
CAN
NO
NO
USB2.0
3 USB Host +1 USB OTG
3 USB Host +1 USB OTG
Ethernet
1 RGMII +1 RMII
1 RGMII +1 RMII
I2C
6 (Max)
6 (Max)
SPI
2 (Max)
2 (Max)
GPIO
138
138
ADC
5
5
Power Supply
+5V
+5V
Mechanical si
ze
43 x 45 x 3.5 mm
43 x 45 x 3.5 mm
Operating te
mperature
-40℃ - +85℃
0℃ - +70℃
Connector
Stamp hole+LGA （222 PIN）
Stamp hole+LGA （222 PIN）
Certification
CE
ROHS
CE
ROHS

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3. Pin Description
3.1. Pin Out
MYC-YT507H core board is welded to the carrier board in the form of SMD patch, and the pin
contains a stamp hole and a back pad. For bottom plate packaging design, refer to the instructions
in Section 7.2.
Figure 3-1 Module pin at top side

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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Figure 3-2 Module pin at bottom side

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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3.2. Pin List
The definition of MYC-YT507H core board interface pins is shown in the following table. The
pin functions of BSP development package are configured according to "Default functions" in the
following table. If you need to change the default pin functions, please modify the relevant driver
configuration code; otherwise, uncertain exceptions such as driver conflict may occur.
Pin
Signal
Default
Function
Description
Voltage
IO
Comments
1
VSOM-5V
VSOM-5V
5.0 V power supply
5V
I
2
VSOM-5V
VSOM-5V
5.0 V power supply
5V
I
3
VSOM-5V
VSOM-5V
5.0 V power supply
5V
I
4
VSOM-5V
VSOM-5V
5.0 V power supply
5V
I
5
VSOM-3V3
VSOM-3V3
3.3V output
3.3V
O
6
VSOM-3V3
VSOM-3V3
3.3V output
3.3V
O
7
VCC-USB2-3V3
VCC-USB2-3V3
USB2 supports standby
wake-up
3.3V
O
Design base plate this pin is
reserved not to use
8
GND
GND
GND
0V
9
CPU-RESET
CPU-RESET
Low level causes reset
1.8V
I
Design base plate this pin is
reserved not to use
10
CPU-ONOFF
CPU-ONOFF
External button
1.8V
I
11
PMIC-WAKEUP
NC
NC
—
—
Design base plate this pin is
reserved not to use
12
GND
GND
GND
0V
—
13
LVDS1-D1N
LVDS1-D1N
LVDS1 differential data 1-
3.3V
O
RGB multiplexing interface
14
LVDS1-D1P
LVDS1-D1P
LVDS1 differential data 1+
3.3V
O
RGB multiplexing interface
15
GND
GND
GND
16
LVDS1-D3N
LVDS1-D3N
LVDS1 differential data 3-
3.3V
O
RGB multiplexing interface
17
LVDS1-D3P
LVDS1-D3P
LVDS1 differential data 3+
3.3V
O
RGB multiplexing interface
18
GND
GND
GND
0V
—
19
LVDS1-D2N
LVDS1-D2N
LVDS1 differential data 2-
3.3V
O
RGB multiplexing interface
20
LVDS1-D2P
LVDS1-D2P
LVDS1 differential data 2+
3.3V
O
RGB multiplexing interface
21
GND
GND
GND
0V
—
22
LVDS1-CLKN
LVDS1-CLKN
LVDS1 differential clock -
3.3V
O
RGB multiplexing interface
23
LVDS1-CLKP
LVDS1-CLKP
LVDS1 differential clock +
3.3V
O
RGB multiplexing interface
24
GND
GND
GND
0V
—
25
LVDS1-D0N
LVDS1-D0N
LVDS1 differential data 1-
3.3V
O
RGB multiplexing interface
26
LVDS1-D0P
LVDS1-D0P
LVDS1 differential data 1+
3.3V
O
RGB multiplexing interface
27
GND
GND
GND
0V
—
28
LVDS0-D2N
LVDS0-D2N
LVDS0 differential data 2-
3.3V
O
RGB multiplexing interface
29
LVDS0-D2P
LVDS0-D2P
LVDS0 differential data 2+
3.3V
O
RGB multiplexing interface
30
GND
GND
GND
0V
—
31
LVDS0-D1N
LVDS0-D1N
LVDS0 differential data 1-
3.3V
O
RGB multiplexing interface
32
LVDS0-D1P
LVDS0-D1P
LVDS0 differential data 1+
3.3V
O
RGB multiplexing interface
33
GND
GND
GND
0V
—
34
LVDS0-D0N
LVDS0-D0N
LVDS0 differential data 0-
3.3V
O
RGB multiplexing interface
35
LVDS0-D0P
LVDS0-D0P
LVDS0 differential data 0+
3.3V
O
RGB multiplexing interface
36
GND
GND
GND
0V
—

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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37
LVDS0-CLKN
LVDS0-CLKN
LVDS0 differential clock -
3.3V
O
RGB multiplexing interface
38
LVDS0-CLKP
LVDS0-CLKP
LVDS0 differential clock +
3.3V
O
RGB multiplexing interface
39
GND
GND
GND
0V
—
40
LVDS0-D3N
LVDS0-D3N
LVDS0 differential data 3-
3.3V
O
RGB multiplexing interface
41
LVDS0-D3P
LVDS0-D3P
LVDS0 differential data 3+
3.3V
O
RGB multiplexing interface
42
GND
GND
GND
0V
—
43
NCSI0-SCK
NCSI0-SCK
Parallel CSI I2C clock
3.3V
O
44
NCSI0-SDA
NCSI0-SDA
Parallel CSI I2C data
3.3V
I/O
45
NCSI0-HSYNC
NCSI0-HSYNC
Parallel CSI Line sync signal
3.3V
I
46
NCSI0-D7
NCSI0-D7
Parallel CSI data 7
3.3V
I
47
NCSI0-PCLK
NCSI0-PCLK
Parallel CSI input pixel clock
3.3V
I
48
NCSI0-D6
NCSI0-D6
Parallel CSI data 6
3.3V
I
49
NCSI0-D5
NCSI0-D5
Parallel CSI data 5
3.3V
I
50
NCSI0-D3
NCSI0-D3
Parallel CSI data 3
3.3V
I
51
NCSI0-D2
NCSI0-D2
Parallel CSI data 2
3.3V
I
52
NCSI0-D4
NCSI0-D4
Parallel CSI data 4
3.3V
I
53
NCSI0-D0
NCSI0-D0
Parallel CSI data 0
3.3V
I
54
NCSI0-D1
NCSI0-D1
Parallel CSI data 1
3.3V
I
55
NCSI0-VSYNC
NCSI0-VSYNC
Parallel CSI field sync signal
3.3V
I
56
NCSI0-D15
NCSI0-D15
Parallel CSI data 15
3.3V
I
57
CSI-FSIN0
CSI-FSIN0
Reserved unused
3.3V
I
58
NCSI0-D14
NCSI0-D14
Parallel CSI data 14
3.3V
I
59
NCSI0-D13
NCSI0-D13
Parallel CSI data 13
3.3V
I
60
NCSI0-MCLK
NCSI0-MCLK
Parallel CSI output clock
3.3V
O
61
NCSI0-D12
NCSI0-D12
Parallel CSI data 12
3.3V
I
62
NCSI0-D11
NCSI0-D11
Parallel CSI data 11
3.3V
I
63
NCSI0-D10
NCSI0-D10
Parallel CSI data 10
3.3V
I
64
NCSI0-D9
NCSI0-D9
Parallel CSI data 9
3.3V
I
65
NCSI0-D8
NCSI0-D8
Parallel CSI data 8
3.3V
I
66
GND
GND
GND
0V
—
67
RGMII-MDC
RGMII-MDC
RGMII Manage Data Clock
3.3V
O
68
RGMII-RXD1
RGMII-RXD1
RGMII data receive 1
3.3V
I
69
GPHY_RST
GPHY_RST
PHY chip reset
3.3V
O
70
RGMII-RXCTL
RGMII-RXCTL
RGMII data receive effective
3.3V
I
71
RGMII-RXD2
RGMII-RXD2
RGMII data receive 2
3.3V
I
72
RGMII-RXD0
RGMII-RXD0
RGMII data receive 0
3.3V
I
73
GND
GND
GND
0V
—
74
RGMII-CLKIN-
125M
RGMII-CLKIN-
125M
RGMII MAC Parameter clock
3.3V
I
75
GND
GND
GND
0V
—
76
RGMII-RXD3
RGMII-RXD3
RGMII data receive 3
3.3V
I
77
RGMII-RXCK
RGMII-RXCK
RGMII Receive clock
3.3V
I
78
RGMII-MDIO
RGMII-MDIO
RGMII Manage Data
3.3V
I/O
79
GPHY-CLK-25M
GPHY-CLK-25M
25Mhz Clock output
3.3V
O
80
RGMII-TXD1
RGMII-TXD1
RGMII Data sent 1
3.3V
O
81
RGMII-TXD3
RGMII-TXD3
RGMII Data sent 3
3.3V
O

MYIR-MYC-YT507H-HW-PM-EN_V1.0
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82
RGMII-TXCTL
RGMII-TXCTL
RGMII Send control
3.3V
O
83
NC
NC
NC
84
GND
GND
GND
0V
—
85
RGMII-TXCK
RGMII-TXCK
RGMII Send clock
3.3V
O
86
GND
GND
GND
0V
—
87
RGMII-TXD0
RGMII-TXD0
RGMII Data sent 0
3.3V
O
88
RGMII-TXD2
RGMII-TXD2
RGMII Data sent 2
3.3V
O
89
GND
GND
GND
0V
—
90
SDIO0-D2
SDIO0-D2
SDIO0 Data 2
3.3V
I/O
91
SDIO0-CMD
SDIO0-CMD
SDIO0 command
3.3V
O
92
SDIO0-D1
SDIO0-D1
SDIO0 Data 1
3.3V
I/O
93
SDIO0-CLK
SDIO0-CLK
SDIO0 clock
3.3V
O
94
SDIO1-D3
SDIO1-D3
SDIO1 Data 3
3.3V
I/O
95
SDIO1-D1
SDIO1-D1
SDIO1 Data 1
3.3V
I/O
96
SDIO0-D3
SDIO0-D3
SDIO0 Data 3
3.3V
I/O
97
SDIO0-D0
SDIO0-D0
SDIO0 Data 0
3.3V
I/O
98
SDIO1-CLK
SDIO1-CLK
SDIO1 clock
3.3V
O
99
SDIO1-D2
SDIO1-D2
SDIO1 Data 2
3.3V
I/O
100
SDIO1-CMD
SDIO1-CMD
SDIO1 command
3.3V
O
101
SDIO1-D0
SDIO1-D0
SDIO1 Data 0
3.3V
I/O
102
SDIO0-DET
SDIO0-DET
SDIO0 Card Plug detection
3.3V
I
103
GND
GND
GND
0V
—
104
MCSI-MCLK
MCSI-MCLK
MIPI CSI Base clock output
-
I
105
MCSI-SDA
MCSI-SDA
MIPI CSI I2C Data
-
I
106
MCSI-SCK
MCSI-SCK
MIPI CSI I2C clock
-
I
107
GND
GND
GND
0V
—
108
MCSI-CLKP
MCSI-CLKP
MIPI CSI differential clock+
-
I
109
MCSI-CLKN
MCSI-CLKN
MIPI CSI differential clock-
-
I
110
GND
GND
GND
0V
—
111
MCSI-D0P
MCSI-D0P
MIPI CSI differential data 0+
-
I
112
MCSI-D0N
MCSI-D0N
MIPI CSI differential data 0-
-
I
113
GND
GND
GND
0V
—
114
MCSI-D1P
MCSI-D1P
MIPI CSI differential data 1+
-
I
115
MCSI-D1N
MCSI-D1N
MIPI CSI differential data 1-
-
I
116
GND
GND
GND
0V
—
117
MCSI-D2P
MCSI-D2P
MIPI CSI differential data 2+
-
I
118
MCSI-D2N
MCSI-D2N
MIPI CSI differential data 2-
-
I
119
GND
GND
GND
0V
—
120
MCSI-D3P
MCSI-D3P
MIPI CSI differential data 3+
-
I
121
MCSI-D3N
MCSI-D3N
MIPI CSI differential data 3-
-
I
122
GND
GND
GND
0V
—
123
TV-OUT
TV-OUT
Analog video output
0~1.8V
O
124
GND
GND
GND
0V
—
125
HDMI-CEC
HDMI-CEC
HDMI CEC signal
1.8V
I
126
HDMI-SDA
HDMI-SDA
HDMI Serial data
1.8V
I/O
127
HDMI-SCL
HDMI-SCL
HDMI serial clock
1.8V
O

MYIR-MYC-YT507H-HW-PM-EN_V1.0
- 20 -
128
HDMI-HPD
HDMI-HPD
HDMI Hot swap signal
1.8V
I
129
GND
GND
GND
0V
—
130
HTXCP
HTXCP
HDMI TMDS Differential
clock signal+
-
O
131
HTXCN
HTXCN
HDMI TMDS Differential
clock signal-
-
O
132
GND
GND
GND
0V
—
133
HTX1P
HTX1P
HDMI TMDS Differential
data 1+
-
O
134
HTX1N
HTX1N
HDMI TMDS Differential
data 1-
-
O
135
GND
GND
GND
0V
—
136
HTX0P
HTX0P
HDMI TMDS Differential
data 0+
-
O
137
HTX0N
HTX0N
HDMI TMDS Differential
data 0-
-
O
138
GND
GND
GND
0V
—
139
HTX2P
HTX2P
HDMI TMDS Differential
data 2+
-
O
140
HTX2N
HTX2N
HDMI TMDS Differential
data 2-
-
O
141
GND
GND
GND
0V
—
142
USB0-DN
USB0-DN
USB0 Differential signal-
-
I/O
143
USB0-DP
USB0-DP
USB0 Differential signal+
-
I/O
144
GND
GND
GND
0V
—
145
USB1-DN
USB1-DN
USB1 Differential signal-
-
I/O
146
USB1-DP
USB1-DP
USB1 Differential signal+
-
I/O
147
GND
GND
GND
0V
—
148
USB2-DN
USB2-DN
USB2 Differential signal-
-
I/O
149
USB2-DP
USB2-DP
USB2 Differential signal+
-
I/O
150
GND
GND
GND
0V
—
151
USB3-DN
USB3-DN
USB3 Differential signal-
-
I/O
152
USB3-DP
USB3-DP
USB3 Differential signal+
-
I/O
153
GND
GND
GND
0V
—
154
RMII-TXEN
RMII-TXEN
RMII send enable
3.3V
O
155
RMII-TXCK
RMII-TXCK
RMII send clock
3.3V
O
156
RMII-RXD1
RMII-RXD1
RMII Data receive 1
3.3V
I
157
RMII-CRS-
RXDV
RMII-CRS-RXDV
RMII Carrier sense data
received effective
3.3V
I
158
RMII-RXD0
RMII-RXD0
RMII Data receive 0
3.3V
I
159
RMII-RXER
RMII-RXER
RMII Receive error
3.3V
I
160
RMII-MDIO
RMII-MDIO
RMII Manage data
3.3V
I/O
161
RMII-MDC
RMII-MDC
RMII Manage clock
3.3V
O
162
RMII-TXD0
RMII-TXD0
RMII data send 0
3.3V
O
163
RMII-TXD1
RMII-TXD1
RMII data send 1
3.3V
O
164
EPHY_RST
EPHY_RST
PHY chip reset
3.3V
O
L1
UART5-TX
UART5-TX
UART5 data send
3.3V
O