N.A.T. NAT-AMC-ZYNQUP-FMC Product manual

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
N.A.T. Gesellschaft für Netzwerk- und Automatisierungs-Technologie mbH
Konrad-Zuse-Platz 9 | 53227 Bonn, Germany | Phone: [phone] - 0
[email protected] | www.nateurope.com
NAT-AMC-ZYNQUP-FMC
FMC CARRIER BOARD
DESIGNED BY N.A.T. GMBH
TECHNICAL REFERENCE MANUAL V1.1
HW REVISION 1.X

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
PREFACE - 2 -
TABLE OF CONTENTS
1. PREFACE ...................................................................................................6
1.1. Disclaimer ......................................................................................................... 6
1.2. About This Document ..................................................................................... 7
2. INTRODUCTION ......................................................................................8
2.1. Applications...................................................................................................... 8
2.1.1. IMAGE PROCESSING APPLICATIONS........................................................... 8
2.1.2. WIRELESS APPLICATIONS ..................................................................... 8
2.2. Main Features................................................................................................... 9
3. QUICK START.........................................................................................10
3.1. Unpacking.......................................................................................................10
3.2. Mechanical Requirements.............................................................................10
3.3. Voltage Requirements...................................................................................11
3.3.1. POWER SUPPLY ............................................................................. 11
3.3.2. HOT-SWAP................................................................................. 11
4. FUNCTIONAL DESCRIPTION ................................................................12
4.1. SoC...................................................................................................................12
4.1.1. PROCESSING SYSTEM (CPU)................................................................ 12
4.1.1.1. Memory................................................................................... 12
4.1.2. PROGRAMMABLE LOGIC (FPGA) ........................................................... 13
4.1.2.1. Programming ............................................................................ 13
4.1.2.2. Memory................................................................................... 13
4.2. PLL and Clocking............................................................................................17
4.3. IPMB-Interface and I2C-Devices...................................................................18
4.4. JTAG and UART ..............................................................................................19
4.5. Interconnect ...................................................................................................19
5. HARDWARE ...........................................................................................20
5.1. Front Panel and LEDs.....................................................................................20
5.2. AMC Port Definition ......................................................................................21

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
PREFACE - 3 -
5.3. Component-, Connector-, and Switch-Location ........................................22
5.3.1. J1: FMC CONNECTOR ...................................................................... 23
5.3.2. J3: JTAG PROGRAMMING HEADER ......................................................... 39
5.3.3. J6: MEMORY CONNECTOR.................................................................. 39
5.3.4. S1: AMC CONNECTOR ..................................................................... 40
5.3.5. S2: MICROSD-CARD SLOT ................................................................. 45
5.3.6. S3: USB-/ UART CONNECTOR............................................................. 46
5.3.7. SW1: HOT SWAP SWITCH .................................................................. 47
5.3.8. SW2: FMC CONFIGURATION SWITCH ...................................................... 47
5.3.9. SW3: JTAG MUX SWITCH ................................................................. 48
5.3.10. SW4 :BOOT MODE SELECT SWITCH........................................................ 49
5.3.11. SW6: UART MUX ......................................................................... 50
6. FMC OPERATION...................................................................................51
6.1. Front panel......................................................................................................51
6.2. Supported FMC’s............................................................................................ 51
6.3. Installing a FMC Module ...............................................................................51
6.4. FMC EEPROM Wizard ....................................................................................52
7. KNOWN ISSUES.....................................................................................54
8. SPECIFICATIONS AND COMPLIANCES ...............................................55
8.1. Internal Reference Documentation .............................................................55
8.2. External Reference Documentation.............................................................55
8.3. Standards Compliance...................................................................................55
8.4. Compliance to RoHS Directive .....................................................................55
8.5. Compliance to WEEE Directive .....................................................................56
8.6. Compliance to CE Directive........................................................................... 56
8.7. Product Safety................................................................................................ 56
8.8. Compliance to REACH ...................................................................................57
8.9. Abbreviation List............................................................................................57
9. DOCUMENT’S HISTORY........................................................................59

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
PREFACE - 4 -
LIST OF TABLES
Table 1 –Technical Data ............................................................................... 9
Table 2 –DDR4-Memory to FPGA Pin Assignment –Address CMD, REFCLK, RESET.......... 13
Table 3 –DDR4-Memory to FPGA Pin Assignment –DATA and Strobe........................ 14
Table 4 –Memory Card: DDR4-Memory to FPGA Pin Assignment –FPGA Bank 27 .......... 15
Table 5 –Memory Card: DDR4-Memory to FPGA Pin Assignment –FPGA Bank 28 .......... 16
Table 6 –LED Functionality .......................................................................... 20
Table 7 –AMC Port Definition....................................................................... 21
Table 8 –J1: FMC Connector –Overview........................................................... 23
Table 9 –J1A: FMC Connector....................................................................... 26
Table 10 –J1B: FMC Connector ..................................................................... 27
Table 11 –J1C: FMC Connector ..................................................................... 28
Table 12 –J1D: FMC Connector ..................................................................... 29
Table 13 –J1E: FMC Connector...................................................................... 31
Table 14 –J1F: FMC Connector...................................................................... 32
Table 15 –J1G: FMC Connector ..................................................................... 33
Table 16 –J1H: FMC Connector ..................................................................... 35
Table 17 –J1I: FMC Connector ...................................................................... 36
Table 18 –J1J: FMC Connector ...................................................................... 37
Table 19 –J3: JTGA Programming Header –Pin Assignment.................................... 39
Table 20 –S1A: AMC-Connector Top –Pin-Assignment ......................................... 40
Table 21 –S1B: AMC-Connector Bottom –Pin-Assignment ..................................... 43
Table 22 –S2: MicroSD-Card Slot –Pin Assignment.............................................. 45
Table 23 –S3: USB-/ UART Connector –Pin Assignment ........................................ 46
Table 24 –SW2 –Operating Parameters ........................................................... 47
Table 25 –SW2 –Configuration..................................................................... 47
Table 26 –SW3 –Operating Parameters ........................................................... 48
Table 27 –SW3 –Configuration..................................................................... 48
Table 28 –SW6 –Operating Parameters ........................................................... 50
Table 29 –SW6 –Configuration..................................................................... 50
Table 30 –Abbreviation List ......................................................................... 57

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
PREFACE - 5 -
Table 31 –Document’s History ...................................................................... 59
LIST OF FIGURES
Figure 1 –Block Diagram ............................................................................ 12
Figure 2 –PLL and Clocking ......................................................................... 17
Figure 3 –IPMB-Interface ............................................................................ 18
Figure 4 –JTAG Architecture......................................................................... 19
Figure 5 –Front Panel –Full Size.................................................................... 20
Figure 6 –Location Diagram –Top ................................................................. 22
Figure 7 –Location Diagram –Bottom ............................................................. 22
Figure 8 –J3: JTAG Programming Header.......................................................... 39
Figure 9 –S1: AMC-Connector (top view).......................................................... 40
Figure 10 –S2: MicroSD-Card Slot .................................................................. 45
Figure 11 –S3: USB-/ UART Connector............................................................. 46
Figure 12 –SW2: FMC Configuration Switch....................................................... 47
Figure 13 –SW3: JTAG MUX Switch ................................................................ 48
Figure 14 –SW4: Boot Mode Select Switch ........................................................ 49
Figure 15 –SW4: Boot Mode Select ................................................................ 49
Figure 16 –SW6: UART MUX ........................................................................ 50
Figure 17 –Installing FMC Module Part 1.......................................................... 51
Figure 18 –Installing FMC Module Part 2.......................................................... 52
Figure 19 –Serial Console COM Port Settings..................................................... 52

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
PREFACE - 6 -
1. PREFACE
1.1. Disclaimer
The following documentation, compiled by N.A.T. GmbH (henceforth called N.A.T.), represents
the current status of the product´s development. The documentation is updated on a regular
basis. Any changes which might ensue, including those necessitated by updated specifications,
are considered in the latest version of this documentation. N.A.T. is under no obligation to
notify any person, organization, or institution of such changes or to make these changes public
in any other way.
We must caution you, that this publication could include technical inaccuracies or typographi-
cal errors.
N.A.T. offers no warranty, either expressed or implied, for the contents of this documentation
or for the product described therein, including but not limited to the warranties of merchant-
ability or the fitness of the product for any specific purpose.
In no event will N.A.T. be liable for any loss of data or for errors in data utilization or processing
resulting from the use of this product or the documentation. In particular, N.A.T. will not be
responsible for any direct or indirect damages (including lost profits, lost savings, delays or
interruptions in the flow of business activities, including but not limited to, special, incidental,
consequential, or other similar damages) arising out of the use of or inability to use this
product or the associated documentation, even if N.A.T. or any authorized N.A.T.
representative has been advised of the possibility of such damages.
All registered names, trademarks etc. are property of their respective holders. The use of
registered names, trademarks, etc. in this publication does not imply, even in the absence of a
specific statement, that such names are exempt from the relevant protective laws and
regulations (patent laws, trade mark laws, etc.) and therefore free for general use. In no case
does N.A.T. guarantee that the information given in this documentation is free of such third-
party rights.
Neither this documentation nor any part thereof may be copied, translated, or reduced to any
electronic medium or machine form without the prior written consent from N.A.T. GmbH.
This product (and the associated documentation) is governed by the N.A.T. General Conditions
and Terms of Delivery and Payment.
Note:
The release of the Hardware Manual is related to a certain HW board revision given in
the document title. For HW revisions earlier than the one given in the document title
please contact N.A.T. for the corresponding older Hardware Manual release.

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
PREFACE - 7 -
1.2. About This Document
This document is intended to give an overview on the NAT-AMC-ZYNQUP-FMC’s functional
capabilities.
Preface
General information about this document
Introduction
Abstract on the NAT-AMC-ZYNQUP-FMC’s main functionality and application field
Quick Start
Important information and mandatory requirements to be considered before operating the
NAT-AMC-ZYNQUP-FMC for the first time
Functional Description
Detailed information on the individual devices and the NAT-AMC-ZYNQUP-FMC’s main
features
Hardware
Description of the connectors, switches, and LEDs located on the NAT-AMC-ZYNQUP-FMC
FMC Operation
Special information on mounting and operating a FMC module on the NAT-AMC-ZYNQUP-
FMC
Known Issues
List of known issues of the current PCB version
Specifications and Compliances
Detailed list of specifications, abbreviations, and datasheets of components referred to in this
document and standards, the NAT-AMC-ZYNQUP-FMC complies to
Document’s History
Revision record
Note:
It is assumed, that the NAT-AMC-ZYNQUP-FMC is handled by qualified personnel only!

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
INTRODUCTION - 8 -
2. INTRODUCTION
The NAT-AMC-ZYNQUP-FMC is a FMC carrier board in AMC form factor with integrated
hardware elements, which make it the ideal platform for sophisticated wireless, machine vision,
and SDR applications.
The carrier board can be expanded be several FMC mezzanine modules, which offer the
flexibility to address a broad range of applications.
2.1. Applications
An overview of the most common applications offered by the NAT-AMC-ZYNQUP-FMC is
given in the following paragraphs. Beyond these, customer applications are feasible as well.
2.1.1. Image Processing Applications
For machine vision applications, the NAT-AMC-ZYNQUP-FMC can be equipped with vision
FMC boards available at N.A.T. See NAT-AMC-ZYNQUP-VISION documentation for more
information.
2.1.2. Wireless Applications
For wireless applications, the NAT-AMC-ZYNQUP-FMC can be equipped with SDR FMC
boards available at N.A.T. See NAT-AMC-ZYNQUP-SDR4/8 documentation for more
information.

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
INTRODUCTION - 9 -
2.2. Main Features
Table 1 –Technical Data
Form Factor
•Single-width, full-size or mid-size AMC
•Width: 73.5 mm, Depth: 180.6 mm
Processing Resources
•Xilinx Zynq Ultrascale+ FPGA MPSoC; choice of ZU7EG, ZU11EG
•GTH transceiver speed: 12.5GHz
FPGA
•4 GB DDR4 SDRAM (x64)
Memory extension slot for additional SRAM or DDR4
CPU
•Quad-core ARM Cortex-A53 processor (application processing unit)
•Dual-core ARM Cortex-R5 (real-time processing unit)
•GPU
•4 GB DDR4 SDRAM (x64)
•QSPI or eMMC boot flash memory
•MicroSD card slot
Microcontroller
•Atmel ATxmega128 as MMC
Software /
Firmware
•IPMI 1.5 compliant
•Linux boot –Linux drivers
•API for all external/internal interfaces
FPGA Programming Interface
•Front panel USB/JTAG connector
•JTAG over backplane connections
•Onboard Xilinx header connector
FMC Slot
•Single HPC FMC slot
•VITA 57.1 compliant (with limitations, see chapter 5.3.1)
•HPC differential pairs (LA/HA/HB) are routed to the FPGA
•DP0 to DP9 are routed to the FPGA
•Support of region 1,2, and 3* FMC modules
Backplane Interconnect
•Ports 0/1: Dual 1GbE connect
•Ports 2/3: FPGA-LVDS-I/Os
•Ports 4-15: PCIe/Ethernet/custom protocol
•Ports 17-20: Custom protocol FPGA-LVDS-I/Os
•Any combinations of PCIe, SRIO, 10/40GbE (on request)
•AMC TCLKA-D and FCLKA connectivity
Front Panel
•Optional clock IN/OUT
•USB/JTAG-Connector
•SD card slot
•AMC front panel elements and application LEDs
Compliance
•AMC.0 R2.0, AMC.1, AMC.2, AMC.3, AMC.4, IMPI V1.5, HPM.1
•EN60950, UL1950, RoHS
Environmental
Operating
Environment
•0 to +55 degrees Celsius (extended temperature range on request)
•Humidity: 5% to 95% (non-condensing)
Storage
Environment
•-40 to +100 degrees Celsius
•Humidity: 5% to 95% (non-condensing)

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
QUICK START - 10 -
3. QUICK START
To ensure proper functioning of the NAT-AMC-ZYNQUP-FMC during its usual lifetime, take
the following precautions before handling the board.
3.1. Unpacking
Electrostatic discharge, incorrect board installation, and uninstallation can damage circuits or
shorten their lifetime. Before touching integrated circuits, ensure to take all required
precautions for handling electrostatic devices.
Avoid touching gold contacts of the AMC-Edge-Connector to ensure proper contact when
inserting the NAT-AMC-ZYNQUP-FMC onto the backplane.
Make sure that the board and its attachments are undamaged and complete according to
delivery note.
3.2. Mechanical Requirements
The NAT-AMC-ZYNQUP-FMC is designed to meet the requirements of µTCA systems, but
can be plugged onto any ATCA carrier board supporting AMC standards as well. So the
installation requires an ATCA-Carrier-Board or an µTCA-Backplane for connecting the NAT-
AMC-ZYNQUP-FMC, a power supply, and cooling devices.
Before installing or uninstalling the NAT-AMC-ZYNQUP-FMC, read the Installation Guide and
the User’s Manual of the carrier board used, or of the µTCA system the board will be plugged
into.
Check all installed boards and modules for steps that you have to take before turning on or
off the power. After taking those steps, turn on or off the power if necessary.
Make sure the part to be installed / removed is hot-swap-capable, if you do not switch off the
power.
Ensure that the NAT-AMC-ZYNQUP-FMC is connected to the carrier board or to the µTCA
backplane with the connector completely inserted.
When operating the board in areas of strong electromagnetic radiation, ensure that the
module is bolted to the front panel or rack, and shielded by closed housing.

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
QUICK START - 11 -
3.3. Voltage Requirements
3.3.1. Power supply
The power supply for the NAT-AMC-ZYNQUP-FMC must meet the following specifications:
+12V / 7A max.
+ 3,3V / 0.15A max.
3.3.2. Hot-Swap
The NAT-AMC-ZYNQUP-FMC supports hot-swapping, which means that the board can be
inserted or extracted during normal system operation without affecting other modules.
Make sure to follow the procedure exactly to prevent the NAT-AMC-ZYNQUP-FMC or the
system it is plugged into from damage!
Insertion of a hot-swap-capable Module
•Ensure the module and the backplane/carrier support hot-swapping
•Ensure that the hot-swap-handle is in “unlock”-position (pulled out)
•Push the NAT-AMC-ZYNQUP-FMC carefully into the dedicated connector until it is
completely inserted
•The blue HS-LED turns solid on
•With pushing the hot-swap-handle to “lock”-position, the HS-LED starts blinking and
the IPMI-Controller of the backplane/carrier detects the board
•If the information provided by the NAT-AMC-ZYNQUP-FMC is valid, the
backplane/carrier enables payload power and the blue HS-LED turns off
Extraction of a hot-swap-capable Module
•Pull the hot-swap-handle in “unlock”-position
•The blue HS-LED starts blinking
•The IPMI-Controller of the backplane/carrier disables payload power
•The HS-LED turns solid on
•Pull the NAT-AMC-ZYNQUP-FMC carefully out of the backplane/carrier

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 12 -
4. FUNCTIONAL DESCRIPTION
The NAT-AMC-ZYNQUP-FMC can be divided into a number of functional blocks, which are
described in the following paragraphs.
The following figure gives an overview on the functional blocks.
Figure 1 –Block Diagram
JTAG
IPMI
MMC
I²C
GPU
SD
Card
JTAG to
USB +
UART
USB
FMC Connector
VITA 57.1 - HPC
AMC Ports 0/1 GbE
AMC Ports 2/3, 12-20 Custom
AMC Ports 4-11
PCIe / Ethernet / Custom
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
FPGA SerDes
TCLKA-D
FPGA
XILINX
Zynq MPSoC
UltraScale+
FFVF1517
ZU7EG
ZU11EG
4x A53
ARM CPU
(Zynq)
2x
R5
2x
R5
CPU
Memory Extension Card:
2x 1GB DDR4 (x8) or
1x 144Mb QDR-IV SRAM (x18)
QSPI
FLASH
464
4GB
DDR4
64
4GB
DDR4
8 8 18
HPC IO
CLK_M2C
DP0-DP9
CLK2_BIDIR_C2M
GC
CLK0_M2C
Stratum III
CLK_BIDIR
Si5374
Clocking
4.1. SoC
The central component on the NAT-AMC-ZYNQUP-FMC is a Xilinx Zynq MPSoC Ultrascale+
FPGA device (ZYNQUP). This SoC provides a powerful general-purpose ARM-CPU, field-
programmable hardware accelerators (FPGA, DSP, and GPU), and flexible I/O.
GTH transceiver speed is 12.5 GHz per default assembly, other speed grades on request.
4.1.1. Processing System (CPU)
The CPU core of the SoC features a quad-core ARM Cortex-A53 processor as application
processing unit and a dual-core ARM Cortex-R5 for real-time processing. Moreover, it is
equipped with a dedicated GPU, realized by a Mali-400 MP2 graphics processing unit.
4.1.1.1. Memory
The Processing System is accompanied by up to 4GB DDR4 RAM (x64, 1600-2400Mb/s). On
board NAND and NOR flashes can be used for booting and configuring the SoC. The additional
MicroSD-Card slot at the front panel can also be used for that purpose but offers quicker
physical access, which is useful during the development.

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 13 -
4.1.2. Programmable Logic (FPGA)
4.1.2.1. Programming
The Programmable Logic of the ZYNQUP-SoC can be accessed via an onboard Xilinx
Programming Module (JTAG-SMT3). It allows to program and debug the FPGA using a Micro-
USB Cable, while it serves the same functionality as the Xilinx Platform Cable II programmer.
Moreover, it features a side UART channel that is connected to the PS UART0.
For more information, please refer to chapter 8.2 External Reference Documentation.
4.1.2.2. Memory
The Programmable Logic is accompanied by up to 4GB DDR4 RAM (x64, 1600-2400Mb/s). The
memory to FPGA pin assignment is shown in the tables below.
Table 2 –DDR4-Memory to FPGA Pin Assignment –Address CMD, REFCLK, RESET
DDR4 Pin#
FPGA Bank 65
Pin#
DDR4 Pin#
FPGA Bank 65
Pin#
DDR4_adr[16]
AR13
DDR4_bg[0]
AR15
DDR4_adr[15]
AR12
DDR4_bg[1]
AN13
DDR4_adr[14]
AP12
DDR4_ba[0]
AT13
DDR4_adr[13]
AT11
DDR4_ba[1]
AP15
DDR4_adr[12]
AT12
DDR4_cs_n[0]
AN12
DDR4_adr[11]
AU10
DDR4_odt[0]
AP16
DDR4_adr[10]
AT10
DDR4_cke[0]
AN16
DDR4_adr[9]
AW12
DDR4_act_n
AL15
DDR4_adr[8]
AV12
DDR4_ck_t[0]
AV14
DDR4_adr[7]
AU13
DDR4_ck_c[0]
AV13
DDR4_adr[6]
AU14
get_ports
DDR4_REFCLK_B65_clk_p
AP14
DDR4_adr[5]
AW10
get_ports
DDR4_REFCLK_B65_clk_n
AR14
DDR4_adr[4]
AW11
get_ports DDR4_reset_n
AN14
DDR4_adr[3]
AW14
DDR4_adr[2]
AW15
DDR4_adr[1]
AV11
DDR4_adr[0]
AU11

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 14 -
Table 3 –DDR4-Memory to FPGA Pin Assignment –DATA and Strobe
DDR4 Pin#
FPGA
Bank 65
Pin#
DDR4 Pin#
FPGA
Bank 64
Pin#
DDR4 Pin#
FPGA
Bank 63
Pin#
DDR4_dqs_t[0]
AW24
DDR4_dq[0]
AU24
DDR4_dq[32]
AW16
DDR4_dqs_c[0]
AW25
DDR4_dq[1]
AU25
DDR4_dq[33]
AV21
DDR4_dqs_t[1]
AR23
DDR4_dq[2]
AV22
DDR4_dq[34]
AV17
DDR4_dqs_c[1]
AT23
DDR4_dq[3]
AV27
DDR4_dq[35]
AV19
DDR4_dqs_t[2]
AL22
DDR4_dq[4]
AV23
DDR4_dq[36]
AV16
DDR4_dqs_c[2]
AL23
DDR4_dq[5]
AV26
DDR4_dq[37]
AU19
DDR4_dqs_t[3]
AH22
DDR4_dq[6]
AW22
DDR4_dq[38]
AW17
DDR4_dqs_c[3]
AJ22
DDR4_dq[7]
AV24
DDR4_dq[39]
AW21
DDR4_dqs_t[4]
AW20
DDR4_dq[8]
AT22
DDR4_dq[40]
AL17
DDR4_dqs_c[4]
AW19
DDR4_dq[9]
AR22
DDR4_dq[41]
AN17
DDR4_dqs_t[5]
AN21
DDR4_dq[10]
AR25
DDR4_dq[42]
AN18
DDR4_dqs_c[5]
AP21
DDR4_dq[11]
AP25
DDR4_dq[43]
AN19
DDR4_dqs_t[6]
AT21
DDR4_dq[12]
AR24
DDR4_dq[44]
AP17
DDR4_dqs_c[6]
AU21
DDR4_dq[13]
AP26
DDR4_dq[45]
AL21
DDR4_dqs_t[7]
AH19
DDR4_dq[14]
AT25
DDR4_dq[46]
AL18
DDR4_dqs_c[7]
AJ19
DDR4_dq[15]
AP24
DDR4_dq[47]
AM21
DDR4_dm_n[0]
AW26
DDR4_dq[16]
AP22
DDR4_dq[48]
AR18
DDR4_dm_n[1]
AT26
DDR4_dq[17]
AL25
DDR4_dq[49]
AP20
DDR4_dm_n[2]
AN23
DDR4_dq[18]
AM25
DDR4_dq[50]
AT17
DDR4_dm_n[3]
AK24
DDR4_dq[19]
AM24
DDR4_dq[51]
AU20
DDR4_dm_n[4]
AU18
DDR4_dq[20]
AN22
DDR4_dq[52]
AT26
DDR4_dm_n[5]
AM19
DDR4_dq[21]
AN26
DDR4_dq[53]
AT20
DDR4_dm_n[6]
AP19
DDR4_dq[22]
AM23
DDR4_dq[54]
AT18
DDR4_dm_n[7]
AK20
DDR4_dq[23]
AM26
DDR4_dq[55]
AR20
DDR4_dq[24]
AK23
DDR4_dq[56]
AG19
DDR4_dq[25]
AJ26
DDR4_dq[57]
AK18
DDR4_dq[26]
AK22
DDR4_dq[58]
AG20
DDR4_dq[27]
AJ25
DDR4_dq[59]
AH21
DDR4_dq[28]
AG23
DDR4_dq[60]
AK19
DDR4_dq[29]
AH24
DDR4_dq[61]
AJ21
DDR4_dq[30]
AG22
DDR4_dq[62]
AG21
DDR4_dq[31]
AJ24
DDR4_dq[63]
AJ20

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 15 -
On request, the NAT-AMC-ZYNQUP-FMC can be equipped with several memory extension
cards. Depending on the target application, different memory types can offer advantages;
QDR4 and RLDRAM3 memory offers low latency random access, which is useful for applications
requiring RAM look up tables (LUTs).
Currently, the NAT-MEM-DDR4-2x8 (Dual Channel, x8, 2 GB DDR4 memory card) is available.
The memory to FPGA pin assignment is described in the following tables.
Table 4 –Memory Card: DDR4-Memory to FPGA Pin Assignment –FPGA Bank 27
Address CMD, REFCLK, RESET, LED
DATA and Strobe
DDR4 Pin#
FPGA
Pin#
DDR4 Pin#
FPGA
Pin#
DDR4 Pin#
FPGA
Pin#
DDR4_B27_adr[16]
F32
DDR4_B27_ba[0]
F33
DDR4_B27_dm_n[0]
D36
DDR4_B27_adr[15]
G34
DDR4_B27_ba[1]
F35
DDR4_B27_dq[0]
C38
DDR4_B27_adr[14]
G33
DDR4_B27_bg [0]
F36
DDR4_B27_dq[1]
C39
DDR4_B27_adr[13]
H32
DDR4_B27_bg[1]
E35
DDR4_B27_dq[2]
C37
DDR4_B27_adr[12]
H31
DDR4_B27_cke[0]
E34
DDR4_B27_dq[3]
B38
DDR4_B27_adr[11]
H33
DDR4_B27_cs_n[0]
D35
DDR4_B27_dq[4]
C34
DDR4_B27_adr[10]
J32
DDR4_B27_odt[0]
D34
DDR4_B27_dq[5]
B35
DDR4_B27_adr[9]
E37
DDR4_B27_act_n
E32
DDR4_B27_dq[6]
A37
DDR4_B27_adr[8]
F37
DDR4_B27_ck_t[0]
E39
DDR4_B27_dq[7]
A38
DDR4_B27_adr[7]
G39
DDR4_B27_ck_c[0]
D39
DDR4_B27_dqs_t[0]
A35
DDR4_B27_adr[6]
G38
get_ports
{DDR4_REFCLK_B27
_clk_p[0]
G35
DDR4_B27_dqs_c[0]
A36
DDR4_B27_adr[5]
H37
get_ports
{DDR4_REFCLK_B27
_clk_n[0]
G36
DDR4_B27_adr[4]
H36
get_ports
DDR4_B27_reset_n
E33
DDR4_B27_adr[3]
E38
get_ports
DDR4_B27_CALIB_
COMP_LED
A32
DDR4_B27_adr[2]
F38
DDR4_B27_adr[1]
H39
DDR4_B27_adr[0]
H38

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 16 -
Table 5 –Memory Card: DDR4-Memory to FPGA Pin Assignment –FPGA Bank 28
Address CMD, RESET, LED
DATA and Strobe
DDR4 Pin#
FPGA
Pin#
DDR4 Pin#
FPGA
Pin#
DDR4 Pin#
FPGA
Pin#
DDR4_B28_adr[16]
D26
DDR4_B28_ba[0]
D27
DDR4_B27_dm_n[0]
K29
DDR4_B28_adr[15]
D30
DDR4_B28_ba[1]
F27
DDR4_B27_dq[0]
K25
DDR4_B28_adr[14]
D29
DDR4_B28_bg [0]
F28
DDR4_B27_dq[1]
J25
DDR4_B28_adr[13]
E30
DDR4_B28_bg[1]
G28
DDR4_B27_dq[2]
K28
DDR4_B28_adr[12]
E29
DDR4_B28_cke[0]
H28
DDR4_B27_dq[3]
J29
DDR4_B28_adr[11]
F31
DDR4_B28_cs_n[0]
G29
DDR4_B27_dq[4]
L27
DDR4_B28_adr[10]
F30
DDR4_B28_odt[0]
H29
DDR4_B27_dq[5]
L28
DDR4_B28_adr[9]
B28
DDR4_B28_act_n
G30
DDR4_B27_dq[6]
M25
DDR4_B28_adr[8]
C27
DDR4_B28_ck_t[0]
C28
DDR4_B27_dq[7]
L25
DDR4_B28_adr[7]
B30
DDR4_B28_ck_c[0]
C29
DDR4_B27_dqs_t[0]
M26
DDR4_B28_adr[6]
B29
get_ports
DDR4_B28_reset_n
G31
DDR4_B27_dqs_c[0]
L26
DDR4_B28_adr[5]
A31
get_ports
DDR4_B28_CALIB_
COMP_LED
B34
DDR4_B28_adr[4]
A30
DDR4_B28_adr[3]
A28
DDR4_B28_adr[2]
A27
DDR4_B28_adr[1]
B31
DDR4_B28_adr[0]
C31

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 17 -
4.2. PLL and Clocking
The NAT-AMC-ZYNQUP-FMC features a SI5347 PLL, which is user-configurable by the FPGA
via I²C.
Figure 2 –PLL and Clocking
Si5347
PLL
33.333MHz
Osc.
125MHz
Osc.
125MHz
Osc. CLK_MGT_224
CLK_PS_REF
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
IN3
IN2
IN1
IN0
CLK_SI5347_FPGA
I2C_SCL_3V3
I2C_SDA_3V3
ZYNQUP
FPGA
Bank 223 / AH10
Bank 223 / AH9
Bank 226 / AA11
Bank 226 / AA12
CLK_MGT_223
CLK_MGT_226
Bank 227 / W12
Bank 227 / W11
CLK_MGT_227
CLK_MGT_228 Bank 227 / V10
Bank 227 / V9
CLK_DDR4Bank 65 / AP14
Bank 65 / AR14
CLK_RAMCON Bank 27 / G36
Bank 27 / G35
Bank 503 / AG28
Bank 224 / AF10
PCIe REFCLK 125MHz Bank 224 / AF9
CLK_MGT_225
Ethernet REFCLK 125 MHz
Bank 225 / AD10
Bank 225 / AD9
CLK2_BIDIR
FP_CLK_REF_OUT S4
FMC Connector
K4
K5
Bank 87 / D10
Bank 87 / D11
H4
H5
C30
C31
CLK0_M2C_P
12.8 MHz
Stratum3 Ref CLK
AMC Connector
TCLKD
TCLKC
TCLKA Bank 66 / AT5
Bank 66 / AT7
TCLKB
Bank 66 / AT6
Bank 66 / AT8
Bank 66 / AV7
Bank 66 / AV8
Bank 66 / AV6
Bank 66 / AU6
PS_MIO10 – Bank 500 / Y28
PS_MIO11 – Bank 500 / T30
I2C_SCL_3V3
I2C_SDA_3V3
75
74
78
77
135
136
138
139
FCLKA Bank 224 / AE11
Bank 224 / AE12
80
81
PS System REFCLK 33.333MHz
CLK3_BIDIR
CLK1_M2C
Bank 87 / F10
Bank 87 / E10
Bank 87 / G11
Bank 87 / F11
J2
J3
G2
G3

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 18 -
4.3. IPMB-Interface and I2C-Devices
The NAT-AMC-ZYNQUP-FMC implements an IPMB interface consisting of an IPMI-µC
(ATXMega128) and a couple of I2C devices connected via I²C.
The following figure shows the architecture in detail.
Figure 3 –IPMB-Interface
MMC
0x61
Master
PLL
0x6D
FPGA
SDA: AJ12
SCL: AK12
Temp
0x1E
EEPROM
0x53
FPGA
PS
PL
SDA: PS_MIO11
SCL: PS_MIO10
Custom
Custom
The external channel of the temperature sensor monitors the FPGA temperature, the internal
channel measures the local PCB temperature.
The IPMI controller also manages the geographical address as requested by the AMC
specification.

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
FUNCTIONAL DESCRIPTION - 19 -
4.4. JTAG and UART
The NAT-AMC-ZYNQUP-FMC supports JTAG and serial UART via the front panel USB
connector or the on-board JTAG programming header. Both interfaces can be used
simultaneously and can be configured using on-board DIP switches.
Configuration of the JTAG Master is possible via the JTAG MUX Switch; for detailed information
on this switch, please refer to chapter 5.3.9 SW3: JTAG MUX.
Configuration of the UART Master is possible via the UART MUX Switch; for detailed
information on this switch, please refer to chapter 5.3.11 SW6: UART MUX.
Figure 4 –JTAG Architecture
FPGA-SoC
AMC Connector
JTAG MUX
JTAG MUX
Switch
JTAG Header
Front USB
JTAG and UART
to
USB Converter
PS_JTAG_TCK – Bank 503 / AG31
PS_JTAG_TDI – Bank 503 / AE30
PS_JTAG_TDO – Bank 503 / AF31
PS_JTAG_TMS – Bank 503 / AE29
AMC_TCK / 165
AMC_TMS / 166
AMC_TDO / 168
AMC_TDI / 169
JTAG_Select JTAG_Disable
UART_RX: PS_MIO6
UART_TX: PS_MIO7
UART
MUX
MMC
UART
UART_Select UART_Disable
UART MUX
Switch
4.5. Interconnect
The SoC interfaces directly to the FMC slot via a VITA 57.1 compliant High Pin Count (HPC)
connector, and to the µTCA backplane via its high-speed SerDes lanes.

NAT-AMC-ZYNQUP-FMC
TECHNICAL REFERENCE MANUAL V1.1
HARDWARE - 20 -
5. HARDWARE
5.1. Front Panel and LEDs
The front plate appearance and the labelling vary depending on the number and variant(s) of
installed FMCs. The figure below shows the full-size version of the NAT-AMC-ZYNQUP-FMC
carrier board.
Figure 5 –Front Panel –Full Size
HS
Stat
Flt
NAT-AMC-ZYNQUP-FMC
1 2 3
Table 6 –LED Functionality
LED
Colour
Function
1 (User)
Red/Green
FPGA LED4 (FPGA Pin AR4, VADJ)
FPGA LED5 (FPGA Pin AR5, VADJ)
2 (User)
Green
FPGA LED2 (FPGA Pin AR8, VADJ)
3 (User)
Green
FPGA LED3 (FPGA Pin AP7, VADJ)
Stat
(User)
Green/Yellow
FPGA LED1 (FPGA Pin AP6, VADJ)
FPGA LED0 (FPGA Pin AP4, VADJ)
Flt
(Fault Indication)
Red ON
Board over temperature or
error during board initialization
OFF
Normal operation